A zero-overhead self-timed 160-ns 54-b CMOS divider

The authors describe the design of a custom integrated circuit for the arithmetic operation of division. The chip uses self-timing to avoid the need for high-speed clocks and directly concatenates precharged function blocks without latches. Internal stages form a ring that cycles without any external signaling. The self-timed control introduces no serial overhead, making the total chip latency equal just the combinational logic delays of the data elements. The ring's data path uses embedded completion encoding and generates the mantissa of a 54-b (floating-point IEEE double-precision) result. Fabricated in 1.2-μm CMOS, the ring occupies 7 mm² and generates a quotient and done indication in 45 to 160 ns, depending on the particular data operands     

On-chip timing reference for self-timed microprocessor

A calibratable on-chip timing reference circuit has been developed to enable a self-timed microprocessor to interface to standard offchip memory and peripheral devices. The circuit exhibits several of the desirable properties of self-timed circuitry such as low power consumption and low electromagnetic interference (EMI). In addition, it is highly testable.     

Low-power self-timed circuit design technique

An implementation of self-timed circuits whose hardware and control signals are significantly reduced is proposed. A globally asynchronous locally synchronous design using the proposed self-timed circuits is also demonstrated. A design example shows that in this implementation less power is consumed with only a small circuit overhead     

Using FPGAs to implement self-timed systems

Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in a variety of applications. In order to ease the complexity of this style of design, however, suitable self-timed circuit primitives must be available to the system designer. This article describes a technique for building self-timed circuits and systems using a library of circuit primitives implemented using Actel field programmable gate arrays (FPGAs). The library modules use a two-phase transition signaling protocol for control signals and a bundled protocol for data signals. A first-in first-out (FIFO) buffer and a simple routing chip are presented as examples of building self-timed circuits using FPGAs.This work was supported in part by NSF award MIP-9111793.     

Performance of iterative computation in self-timed rings

The computation of iterative functions need not be limited by the rate at which external signals, such as a clock, can be supplied to an on-chip circuit. Instead, self-timed structures can compute without clock or latch delays. In particular, a self-timed ring is a loop of logical stages that, after initialization with operands, computes multiple cycles of an iterative computation without further external handshaking. Viewed as a whole, a self-timed ring has a total latency and throughput dependent not only on the individual stages' latencies and cycle times, but also on the total number of stages, tokens, and extra bubbles in the ring. This article derives the performance characteristics of self-timed rings, illustrates them with graphs, and discusses the implications for designing rings with optimal performance. Certain suggested ring configurations allow iteration with no latches and zero delay overhead, achieving a total latency equal to just the sum of the raw function-block delays. This property has been verified by measurements on a chip that demonstrates a self-timed ring for the example function of floating-point division. Fabricated in 1.2 CMOS, the ring occupies 7 mm² and generates a quotient bit every 2.8 ns.     

Bubbles can make self-timed pipelines fast

We explore the practical limits on throughput imposed by timing in a long, self-timed, circulating pipeline (ring). We consider models with both fixed and random delays and derive exact results for pipelines where these delays are fixed or exponentially distributed random variables. We also give relationships that provide upper and lower bounds on throughput for any pipeline where the delays are independent random variables. In each of these cases, we show that the asymptotic processor utilization is independent of the length of the pipeline; thus, linear speedup is achieved. We present conditions under which this utilization approaches 100%.This work was supported in part by NSF Grant MIP-8705454, U.S. Army Research Office—Durham Contract DAAG29-85-K-0191, and DARPA Contract N00014-82-K-0549.     

基于盲源分离的多跳频信号网台分选算法

针对欠定条件下多跳频信号的网台分选问题,该文利用跳频信号在时频域上的稀疏性,提出了一种基于盲源分离的自适应信噪比网台分选算法。首先,用Gabor变换作为系统的时频变换建立欠定条件下跳频信号网台分选的模型;然后,采用了自适应信噪比的时频支撑点阈值设定方法寻找源信号的时频单源点,根据时频单源点的时频比矩阵估计出混合矩阵;最后,利用与信源相对功率偏差相结合的改进的子空间投影法进行网台分选。仿真实验验证了该算法在低信噪比条件下的有效性。      

基于模糊KHM聚类的跳频网台分选方法

针对聚类分析实现跳频网台分选时,分选结果对初始聚类中心敏感且某些样本点“既可以属于类A也可以属于类B”的问题,提出了一种基于模糊K调和均值(KHM)聚类的跳频网台分选方法。首先利用搜索统计直方图位置法预估聚类数目和聚类中心,减少了算法的迭代次数;然后根据跳频信号的各项参数,应用模糊KHM聚类算法对跳频网台进行分选,有效解决了样本点的隶属度问题;最后通过类内类间距法估计得到准确的聚类数目K、聚类中心位置,大幅提升了聚类算法准确度。仿真结果表明,该算法聚类中心接近实际类中心,分选正确率高,迭代次数少。     

Data-driven self-timed RSFQ high-speed test system

Functional testing of rapid single-flux-quantum (RSFQ) logic circuits at high speed is necessary to further optimize circuit design, but it is not easy to do off-chip testing because of the high speed and small amplitude of SFQ pulses. This paper will present the design and test results of an 20 Gb/s bit-by-bit on-chip high-speed digital test system based on data-driven self-timed (DDST) circuits     

Design techniques for high-throughput BiCMOS self-timed SRAMs

Design techniques for a high-throughput BiCMOS self-timed SRAM are described. A new BiCMOS read circuit using a pipelined read architecture and a BiCMOS complementary clocked driver (BCCD) are proposed to reduce the operating cycle time. A 8192×9-b dual-port self-timed SRAM designed using the proposed techniques achieved a clock cycle time of 3.0 ns, that is, a 333-MHz operating frequency, by SPICE simulation on model parameters for 0.8-μm BiCMOS technology. A high-speed built-in self-test (BIST) circuit was studied and designed for the 3.0-ns cycle SRAM. It is confirmed that the BIST circuit allows the 3.0-ns cycle SRAM to test at its maximum operating frequency     

A self-timed divider using a new fast and robust pipeline scheme

This paper investigates the potential of self-timed property of differential cascode voltage switch logic (DCVSL) circuits, and examines architectural techniques for achieving self-timing in DCVSL circuits. As a result, a fast and robust handshake scheme for dynamic asynchronous circuit design is proposed. It is novel and more general than other similar schemes. The proposed self-timed datapath scheme is verified by an 8-bit divider which is implemented using AMS 0.6-μm CMOS technology, and the chip size is about 1.66 mm×1.70 mm. The chip testing results show that the divider functions correctly and the latency for 8-bit quotient-digit generation is 17 ns (about 58.8 MHz)     

A neural network approach to real-time condition monitoring ofinduction motors

A neural network-based incipient fault detector for small and medium-size induction motors is developed. The detector avoids the problems associated with traditional incipient fault detection schemes by employing more readily available information such as rotor speed and stator current. The neural network design is evaluated in real time in the laboratory on a 3/4 hp permanent magnet induction motor. The results of this evaluation indicate that the neural-network-based incipient fault detector provides a satisfactory level of accuracy, greater than 95%, which is suitable for real-world applications     

Efficient sorting on the star graph interconnection network

Two algorithms for sorting n! numbers on an n-star interconnection network are described. Both algorithms are based on arranging the n! processors of the n-star in a virtual (n - 1)- dimensional array. The first algorithm runs in O(n ³ log n time. This performance matches that of the fastest previously known algorithm for the same problem. In addition to providing a new paradigm for sorting on the n-star, the proposed algorithm has the advantage of being considerably simpler to state while requiring no recursion in its formulation. Its idea is to sort the input by repeatedly sorting the contents of all rows in each dimension of the (n - 1>algorithm presented in this paper is more efficient. It runs in O(n ²) time and thus provides an asymptotic improvement over its predecessors. However, it is more elaborate as it uses an existing result for sorting optimally on an (n-1)-dimensional array. This revised version was published online in June 2006 with corrections to the Cover Date.     

一种基于网络的实时限速牌识别算法

针对现有关于车载限速牌识别算法所存在的检测速度慢、准确率低、无法应用于嵌入式系统等问题,提出了一种基于网络的实时限速牌识别算法。该算法基于SSD_MobileNet_v1网络框架进行改进,对原来的网络进行架构裁剪以去除冗余结构;同时引入了特征金字塔网络结构,并使用focal loss作为网络训练的分类损失。实验表明,提出的识别算法准确率可达88.11%,虽然略低于目前主流目标检测算法的检测精度,但是网络的每秒帧率(Frame per Second,FPS)可以达到35.13,拥有较快的检测速度,而权重文件只有24 MB 。因此,与其他算法相比,该算法不仅适合小型的嵌入式人工智能（Artifical Intelligence,AI）设备,而且更贴近真实车载场景下的识别。     

An elastic pipeline mechanism by self-timed circuits

An elastic pipeline mechanism that is especially suitable for data-driven processors is described. With the elastic pipeline scheme, a large processing rate and a smooth data stream in the pipeline are realized at the same time. Two types of self-timed circuits, which are used for data-transfer control circuits in the elastic pipeline, are proposed. Using different types of transfer control circuits, two loop-shaped elastic pipeline mechanisms have been implemented on test chips and are compared with each other. One of these chips demonstrated that the data throughput in the pipeline was 55 megawords per second and that the critical path within a pipeline stage corresponded to 16 inverter delays. This indicates the possibility of high-performance data-driven processors     

Power reduction in self-timed circuits using early-open latchcontrollers

An early-open latch controller for use in self-timed micropipeline circuits is described. It switches into normally-open mode shortly before the arrival of the data. Preventing energy dissipation due to data propagation down the pipe, but preserves the speed advantage of a normally-open latch controller. This is confirmed by comparing the throughput and power for a large circuit with those obtained using other latch controllers     

Self: a self-timed systems design technique

An asynchronous CMOS circuit technique that can realise both combinatorial and sequential logic is introduced. Circuits so designed exhibit correct operation that is independent of wiring delays. An example of a first-in, first-out (FIFO) memory will be used to illustrate the technique.