Characteristics of a 1-Mbit bubble memory chip

The design and characterization of a 1-Mbit block-replicate (swap) chip organized as 584 loops of 2048 bits each is described. Double period propagation elements are employed in both input and output tracks. All propagation elements employed outside of the storage area have a period in excess of 14 μm to minimize step coverage and conductor induced stress problems. A semi-planar polyimide based process is used to fabricate the chips. The replicate gate is subdivided to reduce the voltage requirements. By using copper conductors and simple voltage boosting techniques, the chip can be operated from a 12-V supply. The swap gate is a slight modification of an existing double period design and the replicate gate is based upon a modification of Bonyhard's sideways replicator design. A half-shorted (backside) chevron stretcher detector is employed. Operating characteristics of these components are given over temperature for both chip and package testing. Two programmable map loops are included on-chip to enhance yield, either one of which may be loaded by selecting the transfer-in pulse parity with respect to an alternate bit data stream. The write pulses are multiplexed on the same control line as the map loop read pulses thus saving pins. The design details and the operating margins for the map loops are given.     

Diagnostic testing of a 10-kbit bubble memory chip

A 10-kbit bubble memory chip has been designed and fabricated. Testing was accomplished using a new diagnostic test system, which can drive the bubble chip at two different speeds with bias fields switched synchronously with the bubble propagation. Bias margins of the fabricated chips were analyzed and it was confirmed that a sufficient bias-margin window could be assured in long-term operation.     

Temperature distributions in a megabit bubble chip

For a large-capacity large-size bubble chip, various operating parameter nonuniformities across the chip as well as garnet material and device processing inhomogeneities could be a source of considerable bias margin loss. An example is chip temperature nonuniformity due to detector heating. In an attempt to estimate the chip margin loss due to local temperature nonuniformities, temperature distributions in a Mbit chip have been mapped as a function of detector current amplitude. Temperatures at several regions in the chip were monitored by measuring the resistance of active device components, such as transfer-in gate and replicate/transfer-out gate conductors, and detectors themselves that are of full-shorted 200-element chevron stretchar type. A simple physical model has been developed which, together with various measured local temperatures, provides complete two-dimensional mapping of temperature distributions in the chip. Nonnegligible temperature differences are shown to exist among minor loops (especially at the replicate/transfer-out gate), and those minor loops located close to the detectors are shown to suffer considerable margin losses even at moderate detector-current amplitudes. Operating margin measurements of the minor loops have confirmed the finding.     

A fast access memory design using 3µm bubble 80K chip

A fast-access, non-volatile memory system using 3- μm bubble 80-kbit chips has been designed for an experimental model and evaluated from a systems viewpoint. The goal of this project is to investigate from both the side of technology and cost if the memories built with major-minor organized 3 μm bubble chips are acceptable in the commercial market. This paper describes the practical design of a bubble memory system, with a capacity of 8-Mbits and an average access time of approximately 1 ms at drive frequencies of up to 500 kHz, which involves memory system organization, redundancy design using chips with excess minor loops, packaging, electronic circuits scheme and other considerations. The results of the experiment and the system cost estimate based on this design are also described.     

Major-minor loop, single-level-masking bubble chip

A major-minor loop chip design is presented which requires one high resolution masking step and no critical mask alignments. This design may therefore be implemented with electron-beam, X-ray, or deep-UV conformable-contact lithography to define the submicron linewidths required in ultra-high density devices. Chips with 20-μm period were fabricated with a layered Au-first, NiFe-second structure in a design which provided 6 percent overall margins; substitution of an improved merge component would allow a 10 percent margin overlap of all functions. Tests of components with 8 μm periods show margins of similar percentage values. Current requirements for the devices are low (10 mA for 8 μm period) so that the designs appear extendable to much higher densities.     

Temperature dependence of Ba-ferrite bubble memory bias magnets as a function of magnet geometry

The coefficient of the linear variation of field strength with temperature in Ba-ferrite is shown to have a simple functional dependence upon the permeance coefficient (B/H ratio) of the magnet structure. Using cylindrical magnets with aspect ratios of 0.030 to 4.00 and measuring the field strength from -35 °C to +65 °C, we observe temperature coefficients varying by about 40% from -0.150%/°C to -0.207%/°C These values have a simple relationship to calculated magnet permeance coefficients. An analog circuit approach is presented for calculating the permeance coefficients of complex bias magnet systems. The temperature coefficients predicted from the calculated permeance coefficients and the measured bias field temperature dependences are in good agreement.     

Magnetic bubble mass memory

An experimental magnetic bubble mass memory module complete with all control function and detection electronics has been built and operated. The module contains twenty-eight 16 448-bit mass memory chips and operates at a nominal rotating field frequency of 100 kHz. The module has an average access time of 2.7 ms, a read/write cycle time of 5.14 ms, and a data rate of 700 kbit/sec. A read error rate of <1.6 × 10¹²and error-free propagation in excess of 8.4 × 10¹⁵bubble cycles have been demonstrated.     

Fabrication of bubble memory chips

Investigations have been made on the fabrication of accurate and uniform T-bar circuits. Chrome masks are preferable to emulsion masks, and furthermore, a minimum exposure and intimate contact have been demonstrated to be necessary for accurate and uniform pattern imaging on the AZ1350 resist. A newly developed chemical etchant, a nitric acid-base solution without ferric chloride, can almost eliminate undercutting of permalloy elements. Application of spin-on-glass prior to Permalloy evaporation can result in excellent step coverage at the places where T-bar circuits overlap conductors. Large memory chips having a capacity of 16 × 10³bits and a storage density of 10⁵bits/cm²have successfully been fabricated.     

Block oriented bubble domain memory organization

A block oriented bubble domain memory organization is proposed which provides a block access time improvement over existing major/minor loop designs and which exhibits built-in redundancy. Wafer level integration is utilized to reduce the module lead count.     

A hybrid decoder bubble memory organization

A hybrid bubble organization is proposed which combines the advantages of both major-minor loop and decoder organizations while eliminating some of the complexity of the decoder organization. The organization consists of multiplexed decoder sections in which the selection of different blocks is performed in part by decoding and in part by a major-minor type time domain selection. The number of decoder steps can be reduced at the expense of a modest increase in access time. This organization allows the use of a low current retarding type decoder element, thus reducing the on-chip power consumption. Also, a number of decoder conductors can share the same driver, reducing the number of external chip connections.     

A self-contained magnetic bubble-domain memory chip

All the functions essential for the operation of a memory (viz., storage, access, write, read, and detection) can be performed within a bubble-domain memory chip. This enables the design of a memory with a minimum number of peripheral circuits and interconnections, and a short access time. It is conceivable to achieve a 10⁶-bit memory with fewer than 20 circuits (and interconnections), and with a few hundreds of microseconds access time. The present paper describes the devices required to implement such a memory, experimental data to demonstrate the operability of such devices, and the design criteria.     

Bias magnet design for bubble memory devices

A study has been made of a system consisting of a pair of magnets with thin plates of permeable material on their inner faces. The effect of the plates on the profile of the field between the magnets is predicted as a function of the geometry and the permeability and the way in which the uniformity can be improved is demonstrated.The effect of the permeability is very limited.     

The properties of X-bar bubble memory chips

The properties of a 16-kbit bubble memory chip having a conventional major-minor loop organization are described. The chip can be operated up to a shift rate of 300 kHz which corresponds to a mean access time of 0.5 ms to blocks of 128 bits. Overall bias field margins of 13 percent were obtained, especially as the result of an appropriately selected layout of the transfer gates which is described in detail. Additional data are given concerning the influence of ambient temperature and of the number of propagation steps. The possibility of fabricating X-bar transfer gates using a single photomask step is demonstrated.     

A battery operated bubble memory data-acquisition system

A low-power microprocessor-controlled data-acquisition system, using nonvolatile bubble memory cartridges for mass data storage, is described. The system is battery powered and can operate unattended in a field environment for two months. An analog voltage, which is derived from a gamma-ray ionization chamber or other moderately high-output transducer, is the system input. By using CMOS technology and power switching techniques, the system achieves very low power consumption (<10 mW)     

A high speed drive coil for a large capacity bubble memory

We calculated an eddy current loss in a wire as a function of an applied ac field. Estimating the field at an actual coil wire and summing the losses in all points of wires we obtained a formula representing a coil loss. Based on the calculated results, we designed coils which drive thirty-two 64 kb chips. The observed loss of the coils was in good accord with the calculated one. This 2 Mb module was operated at 40 Oe rotation field of 500 kHz with the coil loss of 8 W.     

68 kbit capacity 16 µm-period magnetic bubble memory chip design with 2 µm minimum features

A bubble propagating structure that operates well on a 14 μm to 18 μm propagate period with a nominal 2 μm minimum feature size has been designed. The structure consists of only 1 discrete permalloy feature per circuit period. Sixty-eight kbit-capacity memory chips based on such structures have been designed, built, characterized, packaged and the packages have been characterized. The chip is organized as a set of minor (storage) loops with separate write and read major lines. The bubble manipulating functions, of which the replicate and transfer gates are the most critical, have also been designed with 2 μm minimum features. The design is adequate to provide a 14 Oe bias field margin range with drive fields of about 35 Oe, using a bubble garnet material with approximately 170 Oe free bubble collapse field. Sixty-eight kbit single loop shift register type chips designed using similar propagating structures, however, provide over 20 Oe bias field margin ranges with drive fields of about 35 Oe.     

Ion-implanted and permalloy hybrid magnetic bubble memory devices

Hybrid bubble memory devices have been proposed and operated with the memory density of 4 Mbit/cm². In the hybrid bubble memory devices, minor loops are composed of ion-implanted tracks with 4-µm period, and major lines and functional parts including block-replicate and swap gates are composed of Permalloy tracks with a longer period of 12 µm. Passive junctions between ion-implanted and Permalloy tracks have been developed, introducing the tapered ion-implantation technique. Improving the characteristics of the functional parts composed of Permalloy tracks, the hybrid bubble memory devices with block-replicate and swap gates have been operated, and the feasibility of the devices has been confirmed. In addition, the possibility of higher memory density has been shown.     

Theoretical analysis of longevity testing on bubble memory devices

Theoretical results of magnetic bubble device long-term reliability testing are reported. The bubble during propagation along Permalloy tracks is represented by a simple, one-dimensional stochastic model. An equation to describe fluctuation in cylindrical bubble radius is approximated in the Langevin type stochastic differential equation, in which a set of small effects, such as interaction among bubbles and crystal nonuniformity, are considered as a white noise forcing term. Estimating the average time to bubble annihilation or runout (bubble memory mean time to failure) is reduced to a level-crossing problem for a random process. Calculated bias field margin degradation shows a qualitative agreement with experimental results for an actual bubble device. Bubble material parameters for obtaining maximum operation time are suggested.     

A true swap gate for magnetic bubble memory chips

The design of a true swap gate suitable for incorporation into magnetic bubble memory chips with 16-μm to 18-μm circuit periods is reported. The swap operation is true in that the outcoming bubble takes the position vacated by the ingoing bubble, as well as vice versa. Swap gates of this design have been operated successfully at temperatures from 0°C to 70°C, and frequencies up to 100 kHz.