A pile-up masking technique for the fabrication of sub-half-micron gate length GaAs MESFET's

A pile-up masking technique, using conventional optical lithography and a two-step evaporation process, has been developed to produce sub-half-micron gates of controllable dimensions. The new approach allows a high-yield production of self-aligned and deep-recess gates with multi-layered metallization systems. By using this technique, GaAs single-gate and dual-gate MESFET's with Cr/Au gates 0.2 µm long and 0.9 µm thick (i.e., an aspect-ratio of 4.5) have been fabricated. The technique can be applied to the production of high-frequency low-noise MESFET's.     

GaAs dual-gate MESFET's

Performance of GaAs dual-gate MESFET, including high-frequency noise behavior, was analyzed on the basis of Statz's model. Under the design considerations developed from the analysis, fabrication and characterization of a prototype device were carried out. The present analysis was confirmed to reproduce satisfactorily the performance observed. Minimum noise figure and associated gain observed in the device with two 1-µm gates were; 1.2 dB and 16.7 dB at 4 GHz, 2.2 dB and 16.3 dB at 8 GHz, and 3.2 dB and 12.6 dB at 12 GHz, respectively. More than 35-dB gain controllability was also obtained at 8 GHz.     

Electron-beam fabrication of GaAs low-noise MESFET's using a new trilayer resist technique

A LO/HI/LO resist system has been developed to produce sub-half-micrometer T-shaped cross section metal lines using e-beam lithography. The system provides T-shaped resist cavities with undercut profiles. T-shaped metal lines as narrow as 0.15 µm have been produced. GaAs MESFET's with 0.25-µm T-shaped Ti/Pt/Au gates have also been fabricated on MBE wafers using this resist technique. Measured end-to, end 0.25-µm gate resistance was 80 ω/mm, dc transconductance gmas high as 300 mS/mm was observed. At 18 GHz, a noise figure as low as 1.4 dB with an associated gain of 7.9 dB has also been measured. This is the lowest noise figure ever reported for conventional GaAs MESFET's at this frequency. These superior results are mainly attributed to the high-quality MBE material and the advanced T-gate fabrication technique employing e-beam lithography.     

A subnanosecond integrated switching circuit with MESFET's for LSI

Using a simple channel implantation step, the choice of the threshold voltage determines speed and power. Illustrations are given by the example of a 3-input NOR-gate with 1/spl times/5-/spl mu/m/SUP 2/ channel geometry for the switching transistors. A design with dual threshold voltages allowing the optimization of power consumption while keeping subnanosecond propagation delay times is presented and applied to a speed- and power-optimized dual-type MESFET NOR-gate. Examples are presented of experimental d.c. characteristics measured on fabricated samples exhibiting an average power consumption of 150 /spl mu/W. A propagation delay time of 0.8 ns is deduced for a fan-out of 3. This performance is discussed in conjunction with a set of parameters including geometry, technological reproducibility, and circuit design requirements. It appears that geometries of about 1 /spl mu/m lead to the best compromise for fast switching and optimized LSI organization.     

Scaled performance for submicron GaAs MESFET's

Scaling schemes for GaAs MESFET's below the submicron gate length are proposed. The corresponding switching times are calculated accurately down to 0.25µm gate length devices using an ensemble Monte Carlo simulation program. It is demonstrated that the proposed scaled devices offer ultrashort switching time due to the nonstationary carrier transport effects.     

Low-Noise MESFET's for Ion-Implanted GaAs MMIC's

Fabrication considerations for low-noise FET's in ion-implanted GaAs monolithic microwave integrated circuits (MMIC'S) are presented. Processes that can deteriorate FET performance have been identified and some solutions proposed. Low-noise MMIC FET's fabricated along these lines show good microwave performance tbrongh 18 GHz, approaching the performance available from similar discrete FET's. 0.8- µm gate-length MMIC FET's with a noise figure of 2.9 dB and associated gain of 6.1 dB at 18 GHz have been fabricated. These devices are suitable for low-noise applications in ion-implanted GaAs MMIC's.     

A capacitance model for GaAs MESFET's

We present a new analytical model for small signal capacitances of GaAs MESFET's. This model may be used for epitaxially grown as well as ion-implanted FET's because the effects related to the nonuniform doping profile are included. We also take into account backgating, capping, velocity saturation in the conducting channel, and possible Gunn domain formation in the channel at the drain side of the gate. The model explains complicated voltage dependences of the gate-source and gate-drain capacitances of GaAs microwave FET's and is in fair agreement with the experimental results. This analytical model is quite suitable for the computer-aided design of GaAs microwave FET's and integrated circuits.     

Monolithic optoelectronic circuit design and fabrication byepitaxial growth on commercial VLSI GaAs MESFET's

A technique for realizing large-scale monolithic OEIC's, which involves epitaxially growing GaAs-based heterostructures on fully metallized commercial VLSI GaAs MESFET integrated circuits, has recently been reported. In the initial work the circuits and LED's occupied distinct halves of a chip, the dielectric growth window was wet-etched after circuit fabrication, and the LED's required both n and p ohmic contacts to be formed after epitaxial growth. In this letter we report the use of standard foundry process etches to open dielectric growth windows intermixed with circuitry and the growth of n-side-down LED's on a source/drain ion-implanted n⁺ region serving as the n ohmic contact. A winner-take-all neural circuit is demonstrated using these advances, which are important steps toward realizing higher levels of circuit integration     

Backgating in GaAs MESFET's

The phenomenon of backgating in GaAs depletion mode MESFET devices is investigated. The origin of this effect is electron trapping on the Cr²⁺and EL(2) levels at the semi-insulating substrate-channel region interface. A model describing backgating, based on DLTS and spectral measurements, is presented. Calculations based on this model predict that closely compensated substrate material will minimize backgating. Preliminary experimental data support this prediction.     

Backdating in GaAs MESFET's

The phenomenon of backgating in GaAs depletion mode MESFET devices is investigated. The origin of this effect is electron trapping on the Cr/sup 2+/ and EL(2) levels at the semi-insulating substrate-channel region interface. A model describing backdating, based on DLTS and spectral measurements, is presented. Calculations based on this model predict that closely compensated substrate material will minimize backgating. Preliminary experimental data support this prediction.     

Degradation mechanism of GaAs MESFET's

The degradation mechanism of X-band low-noise GaAs MESFET's is examined to obtain meaningful information on a common mode of failure. The devices tested have a half-micrometer gate (Au/ Mo) and source and drain ohmic contacts (Au/Ni/Au-Ge). Zero bias drain conductanceg_{D0}is considered as a representative parameter for degradation during aging. The major failure mode is an increase in series resistance of the ohmic contacts. The amount of degradation, decrease ing_{D0}, is proportional to the square root of aging time, and accompanied by an increase in minimum noise figureF_{min}. A degradation model based on the formation of a high-resistance layer between the ohmic metals and GaAs crystal by a diffusion reaction mechanism is proposed, resulting in excellent agreement between calculated and experimental results. Using ion-microspectroscopy analysis (IMA), diffusion of Ni into GaAs crystal is revealed. Mean time to failure (MTTF) is estimated to be 10⁷-10⁸h at channel temperature of 80°C with an increase inF_{min}of 0.5 dB as failure criterion.     

Analytical model of GaAs MESFET's

A simple analytical model of GaAs MESFET's is proposed. The model is based on the assumption that the current saturation in GaAs MESFET's is related to the stationary Gunn domain formation at the drain side of the gate rather than to a pinchoff of the conducting channel under the gate. The saturation current, channel conductance, transconductance, charge under the gate, gate-to-source and drain-togate capacitances, cutoff frequency, characteristic switching time, power-delay product, and breakdown voltage are calculated in the frame of this model. The results are verified by two-dimensional computer calculations. They agree well with the results of the computer analysis and experimental data for a 1-µm gate GaAs MESFET. It is shown that a stray gate-to-drain and gate-to-source capacitance sets up a limitation of a gate length which must be larger than or about 0.1 µm for a GaAs MESFET.     

Reliability Study of GaAs MESFET's

Failure modes have been studied phenomenologically on a small-signal GaAs MESFET with a 1mu m aluminum gate. Three major failure modes have been revealed, i.e., gradual degradation due to source and drain contact degradation, catastrophic damage due to surge pulse, and instability or reversible drift of electrical characteristics during operation. To confirm the product quality and to assure the device reliability, a quality assurance program has been designed and incorporated in a production line. A cost-effective lifetime prediction method is presented that utilizes correlations between RF parameters and dc parameters calculated using an equivalent circuit model. Mean time to failure (MTTF) value of over 10/sup 8/ h has been obtained for the GaAs MESFET for an operating channel temperature of 100/spl deg/C.     

Optical Control of GaAs MESFET's

Theoretical and experimental work for the performance of GaAs MESFET's under illumination from light of photon energy greater than the bandgap of the semiconductor is described. A simple model to estimate the effects of light on the dc and RF properties of MESFET'S is presented. Photoconductive and photovoltaic effects in the active channel and substrate are considered to predict the change in the dc equivalent circuit parameters of the FET, and from these the new Y- and S-parameters under illumination are calculated. Comparisons with the measured S-parameter's without and under illumination show very close agreement. Optical techniques can he used to control the gain of an FET amplifier and the frequency of an FET oscillator. Experimental results are presented showing that the gain of amplifiers can be varied up to around 20 dB and that the frequency of oscillators can be varied (tuning) around 10 percent when the optical absorbed power in the active region of the FET is varied by a few microwatts. When the laser beam is amplitude-modulated to a frequency close to the free-running FET oscillation frequency, optical injection locking can occur. An analytical expression to estimate the locking range is presented. This shows a fair agreement with the experiments. Some suggestions to improve the optical locking range are presented.     

A subthreshold current model for GaAs MESFET's

A GaAs MESFET model capable of accurately describing currents in the subthreshold region is described. The model is based on the concept of drain-induced barrier lowering (DIBL) together with the reverse-bias Schottky diode conduction. Agreement between measured and calculated data based on this model was excellent.     

Quasi-two-dimensional modeling of GaAs MESFET's

A numerical simulation of GaAs MESFET structures is presented. The approach taken in this paper combines an analytical solution with a full simulation. Poisson's equation, the current continuity equation, and an electron-temperature equation are formulated in terms of a geometry factor that defines the shape of the conducting channel in the MESFET. The transport equations are then solved in one dimension and the channel geometry factor is found analytically. This method was found to be considerably faster than full two-dimensional simulations. The model has been compared to full two-dimensional drift-diffusion and energy-momentum results to determine its validity.     

New modeling of GaAs MESFET's

A first theoretical analysis is given based on a new model of GaAs MESFET's which considers the inherent effects of a free-surface depletion layer between source and gate as well as between gate and drain. Change of surface potential according to the input gate voltage causes variable series resistance and variable gate capacitance to be added to the intrinsic FET. The parasitic effects are now quantitatively estimated and an improved guideline for the design and the fabrication process is given. Detailed calculation of the effects of device parameters for recessed gate structure and some comments on the optimization of n⁺-layers in self-aligned structure are included. The effects of the interfacial depletion layer between active layer and substrate is also estimated in terms of drain voltage and the ratio of total deep levels density in the substrate to donor density in the active layer.     

Optimization of low-noise GaAs MESFET's

This paper presents a device design which is an effective way of reconciling the two conflicting requirements for low-noise GaAs MESFET's. Decreasing the effective value of gate length can be achieved, without penalty of increased gate metallization resistance, by the virtue of a proper gate-recess structure. This effect can be explained by the "effective gate length" concept. The pertinent fabrication techniques and the optimal noise-figure expression are given for an optimized structure with illustrated examples.     

Beyond-punchthrough current in GaAs MESFET's

In a recent letter published in this journal, Patrick et al. reported on a maximum drain voltage for pinchoff Which varied exponentially with gate length in very short-gate GaAs MESFET's. The I-V characteristics given showed that this variation is associated with beyond-punchthrough drain current. Current flowing across a depleted region is an instance of the triode mode of FET operation described by other researchers in 1966. Triode-mode theory can help in the understanding of the behavior of GaAs MESFET's near pinchoff, including the devices of Patrick et al.     

Very short gate-length GaAs MESFET's

GaAs MESFET's with gate lengths ranging from 0.36 µm down to 0.055 µm, the smallest so far reported, have been fabricated using electron-beam lithography. DC output characteristics were obtained from all of the devices tested and transconductances up to 300 mS/mm were measured. However it was observed that there is a maximum drain-source voltage that can be pinched off in these short gate devices. This voltage varies exponentially from 1 V in the 0.055-µm gate devices to 6 V in the 0.36-µm device. It is speculated that this effect is due to current injection into the buffer layer.