A 90 ns 256K /spl times/ 1 bit DRAM with double-level Al technology

A high-performance 256K /spl times/ 1bit DRAM with double-level Al technology is described. It has a small die size of 8.5 /spl times/ 4.0 mm/SUP 2/, an access time of 90 ns, and a soft error rate of less than 1000 FITs. The first and second Al layers are used as bit lines and word lines, respectively. Double-level Al technology is also applied to periphery circuit regions and contributes to a 15 percent reduction of die size in conjunction with a simplified sense-restore circuit. A compact memory cell (10.9 /spl times/ 6.1/spl mu/m /SUP 2/) with a storage capacitance of over 50 fF is obtained through the use of wafer stepping and dry etch techniques.     

3-D integrated optical interconnect induced by self-focused beam

The realisation of a 1/spl times/4 optical integrated routing circuit is reported. The router is composed of multiple adjacent circular waveguides formed with self-focused beams by photorefractive effect inside a congruent photonic-grade lithium niobate wafer. The routing ability of the 3-D optical component is demonstrated and characterised.     

Electron image projection systems for microcircuit lithography

High-resolution electron-beam microfabrication requires long process times when using a single scanning beam to expose large-area integrated circuits. Exposure times for a 2-in wafer by a scanning beam system are typically between 30 min to 3 h, depending on the area and complexity of the circuit. This paper describes an electron projection system that projects the whole electron image of the integrated circuit mask onto the wafer at once, enabling exposure times of 1 s or less to be attained. The system incorporates a photocathode patterned into an integrated circuit mask. The pattern is projected and focused onto the wafer using axial magnetic and electrostatic fields. Described herein are factors affecting photocathode life and exposure times. A technique for automatic alignment of the mask to the wafer is also described which has achieved 0.25-µ alignment accuracies.     

200-mm wafer-scale transfer of 0.18-/spl mu/m dual-damascene Cu/SiO/sub 2/ interconnection system to plastic substrates

We report a low-temperature (<200/spl deg/C) 200-mm wafer-scale transfer of a 0.18-/spl mu/m dual-damascene Cu/SiO/sub 2/ interconnection system to FR-4 plastic substrates using adhesive bonding. We demonstrate removal of the silicon bulk layer to leave behind a flexible 3-/spl mu/m-thick Si back-end-of-line (BEOL) circuit on a 0.1-mm-thick FR-4 wafer. The mechanical and electrical integrity of the thin Si BEOL circuit on FR-4 are confirmed by focused ion beam scanning electron microscope microscopy and current-voltage characterization on a variety of test structures, which include serpentine, via chain and Kelvin test structures on different locations on the wafer. This process will pave the path to allow integration of high-performance submicrometer Si electronics on plastic substrates.     

Novel current-mode background suppression for 2-D LWIR applications

A new readout circuit involving two-step current-mode background suppression is studied for two-dimensional long-wavelength infrared focal plane arrays (2-D LWIR FPAs). Buffered direct injection (BDI) and a feedback amplifier are used for the input circuit and background suppression circuit, respectively. The readout circuit has been fabricated using a 0.6-/spl mu/m 2-poly 3-metal CMOS process for a 64/spl times/64 LWIR HgCdTe IR array with a pixel size of 50 /spl mu/m/spl times/50 /spl mu/m. The simple pixel circuit has a very small skimming error of less than 0.3% and low noise characteristics for an adequate calibration range and integration time.     

Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

The authors report the first demonstration of integrating wafer stacking via Cu bonding with strained-Si/low-k 65-nm CMOS technology. Sets of 330 mm wafers with active devices such as 65-nm MOSFETs and 4-MB SRAMs were bonded face-to-face using copper pads with size ranging between 5 /spl mu/m/spl times/5 /spl mu/m and 6 /spl mu/m/spl times/40 /spl mu/m. The top wafers were thinned to different thicknesses in the range 5 to 28 /spl mu/m. Through-silicon-vias (TSVs) and backside metallization were used to enable electrical testing of both wafers in the Cu-stacked configuration. We tested individual transistors in the thinned silicon of bonded wafer pairs where the thinned silicon thickness ranged from 14 to 19 /spl mu/m. All results showed that both n- and p-channel transistors preserved their electrical characteristics after Cu bonding, thinning, and TSV integration. We also demonstrated the functionality of stacked 65-nm 4-MB SRAMs by independently testing the cells in both the thinned wafer and the bottom wafer. For the SRAM, we tested a wider thinned wafer thickness range from 5 to 28 /spl mu/m. On all tested samples, we did not find any impact to the electrical performance of the arrays resulting from the three-dimensional (3-D) integration process. The stacked SRAM is an experimental demonstration of the use of 3-D integration to effectively double transistor packing density for the same planar footprint. The results presented in this letter enable further exploratory work in high-performance 3-D logic, which takes advantage of the improved interconnect delays offered by this Cu-bonding stacking scheme integrated with modern CMOS processes.     

Low-Temperature Polymer-Based Three-Dimensional Silicon Integration

We describe a low-temperature polymer-based 3D integration technique for wafer-scale transplantation of micrometer thick circuit and device layers onto another host wafer. The maximum temperature of this approach is 340 ^oC. It incorporates a low-k semiconductor compatible dielectric bonding media, employs tools that are readily available within a fabrication environment, and is very simple to implement. Another unique characteristic of the approach is the simultaneous separation of the transplanting layer from the donor assembly with the bonding to the host assembly. Alignment registration of several micrometers between device layers is demonstrated. Electrical results of 3D inverter circuit along with demonstration of four-device-layer 3D integrated stack are presented.     

A CMOS image sensor for high-speed active range finding using column-parallel time-domain ADC and position encoder

In this paper, a smart image sensor for real-time and high-resolution three-dimensional (3-D) measurement to be used for sheet light projection is presented. It realizes not only a sufficiently high frame rate for real-time 3-D measurement, but also high pixel resolution due to a small pixel circuit and high subpixel accuracy due to gravity center calculation using an intensity profile. Simulation results show that the ultimate frame rate is 32.6 k frames/s (i.e., 31.8 range/spl I.bar/map/s) in a 1024/spl times/1024 pixel sensor. A 3-b intensity profile allows subpixel accuracy under 0.1 pixel. The sensor using this architecture can acquire a two-dimensional (2-D) image as well, so a texture-mapped 3-D image can be reproduced by the same sensor. A 128/spl times/128 smart image sensor has been developed and successfully tested. A 2-D image, a range map, and a texture-mapped 3-D image have been acquired by the 3-D measurement system using the fabricated sensor.     

A high-speed P-channel random access 1024-bit memory made with electron lithography

A switched capacitor, p-channel, 1024 bit random access memory has been made with electron lithography. The basic circuit was the same as that described by Boll and Lynch (see abstr. B35355 or C22818 fo 1973) but with halved lateral dimensions. The gate length of the switching transistor was 4 /spl mu/m, and the chip size was 1.2/spl times/1.8 mm. In order to fabricate the device, a 1 /spl mu/m alignment accuracy was required. Even with this modest shrinking of feature size, the minimum access time of the memory was reduced from 100 ns to less than 50 ns.     

Highly integrated three-dimensional MMIC technology applied tonovel masterslice GaAs- and Si-MMICs

A novel three-dimensional (3-D) masterslice monolithic microwave integrated circuit (MMIC) is presented that significantly reduces turnaround time and cost for multifunction MMIC production. This MMIC incorporates an artificial ground metal for effective selection of master array elements on the wafer surface, resulting in various MMIC implementations on a master-arrayed footprint in association with thin polyimide and metal layers over it. Additionally, the 3-D miniature circuit components of less than 0.4 mm² in size provide a very high integration level. To clearly show the advantages, a 20-GHz-band receiver MMIC was implemented on a master array with 6×3 array units including a total of 36 MESFETs in a 1.78×1.78 mm area. Details of the miniature circuit components and the design, closely related to the fabrication process, are also presented. The receiver MMIC exhibited a 19-dB conversion gain with an associated 6.5-dB noise figure from 17 to 24 GHz and an integration level four times higher than conventional planar MMICs. This technology promises about a 90% cost reduction for MMIC because it can be similarly applied to large-scale Si wafers with the aid of an artificial ground     

A channel unit signal controller for shared codec D-type channel banks

The channel unit signal controller is a 2.56 mm/spl times/2.56 mm beam-leaded silicon integrated circuit fabricated using the complementary bipolar integrated circuit (CBIC) technology with buried injector logic (BIL). The circuit handles the distribution of signals within a channel unit of a digital telecommunications system. Several diverse circuit functions are incorporated on this device including high-speed emitter-coupled logic, lower speed buried injector logic. JFET switches, high-speed pulse amplifiers to drive the JFETs, a voltage limiter, and a comparator circuit. The channel unit signal controller is described from system and circuit points of view and the CBIC/BIL process is described.     

A defect-tolerant design for full-wafer memory LSI

Automatic defect-tolerant techniques are described for the realization of full-wafer LSI. These techniques, which are based on duplication redundancy, feature automatic inspection, detection, shift, and selection. Using these techniques, a 1.5-Mb frame static memory on a 4-in. silicon wafer (512/spl times/512 dot plane, 64 color) has been realized. The device has been fabricated using n-well CMOS technology with double-level polysilicon, double-level aluminum, and photolithography of 3-/spl mu/m dimensions. It provides typical access time of 520 ns and operating power of 5.8 W.     

Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method. Five key technologies for 3-D integration were developed, namely, the formation of vertical buried interconnections, metal microbump formations, stacked wafer thinning, wafer alignment, and wafer bonding. Deep trenches having a diameter of 2 mum and a depth of approximately 50 mum were formed in the silicon substrate using inductively coupled plasma etching to form vertical buried interconnections. These trenches were oxidized and filled with n+ polycrystalline silicon or tungsten. The 3-D devices and 3-D shared-memory test chips with three-stacked layers were fabricated by bonding the wafers with vertical buried interconnections after thinning. No characteristic degradation was observed in the fabricated 3-D devices. It was confirmed that fundamental memory operation and broadcast operation between the three memory layers could be successfully performed in the fabricated 3-D shared-memory test chip     

A Ka-band InP MMIC 180/spl deg/ phase switch

A new type of Ka band (26 to 36 GHz) 180 degree phase switch (bi-phase modulator) monolithic microwave integrated circuit has been developed for the EC funded FARADAY radio astronomy project. This integral component forms part of a chip set for a very low noise switching radiometer operating at a temperature of approximately 15 K. To maximize the sensitivity of the radiometer lattice-matched indium phosphide HEMT technology has been used: all of the active components of the radiometer, with the exception of the detectors, have been manufactured on a single wafer process. Design principles are described, together with a comparison of modeled and measured results. The results show an average insertion loss of 3.5 dB, return loss of better than 10 dB and an average phase difference close to 170/spl deg//spl plusmn/10/spl deg/ the 26-36 GHz band.     

A metallisation providing two levels of interconnect for beam-leaded silicon integrated circuits

A two-level-metal structure is described for beam-leaded silicon integrated circuits. The two-level structure consists of a Ti-Pt first level, plasma-deposited silicon nitride as interlevel dielectric, and Ti-Pt-Au as a second level. The Ti-Pt layers of both levels are sputter deposited. Sputter etching is used for pattern definition of the Pt layer of the first level and the Pt-Au layers of the second level. Two examples are presented of the application of the structure to bipolar integrated circuits. One is a LSI circuit consisting of a 24/spl times/9-bit sequential access memory implemented in a Schottky I/SUP 2/L technology and the other is a seven-gate inverter implemented in a standard buried collector technology.     

Laser-patterned interconnect for thin-film hybrid wafer-scale circuits

High-performance electronic systems are often constrained by conventional packaging and interconnection technologies. A new technique is described for electrically connecting integrated circuit chips to a silicon wafer interconnection substrate, enabling future fabrication of hybrid wafer-scale circuits to be performed exclusively with thin-film interconnection technology. Thin-film wiring is fabricated down beveled edges of the chips and patterned using discretionary laser etching techniques. Interconnections on a 25-µm pitch (1600 wires around a 1-cm square chip) were achieved with this approach. Functioning hybrid memory modules have been fabricated to demonstrate feasibility of the technology.     

A 25 ns 64K static RAM

A high-performance 64K/spl times/1-bit CMOS SRAM is described. The RAM has an access time of 25 ns with active power of 350 mW and standby power of 15 mW. The access time has been obtained by using a 1.5 /spl mu/m rule CMOS process, advanced double-level A1 interconnection technology, an equalizer circuit, and a digit line sense amplifier that is the first sense amplifier directly connected to digit lines. The WRITE recovery circuit is effective in improving WRITE characteristics, and a block selecting circuit was used for low power dissipation.     

Packaging of MMICs in multilayer LCP substrates

A 13-25-GHz GaAs bare die low noise amplifier is embedded inside a multilayer liquid crystal polymer (LCP) package made from seven layers of thin-film LCP. This new packaging topology has inherently unique properties that could make it an attractive alternative in some instances to traditional metal and ceramic hermetic packages. LCP is a near-hermetic material and its lamination process is at a relatively low temperature (285/spl deg/C versus >800/spl deg/C for ceramics). The active device is enclosed in a package consisting of several laminated C0/sub 2/ laser machined LCP superstrate layers. Measurements demonstrate that the LCP package and the 285/spl deg/C packaging process have minimal effects on the monolithic microwave integrated circuit radio frequency (RF) performance. These findings show that both active and passive devices can be integrated together in a homogeneous laminated multilayer LCP package. This active/passive compatibility demonstrates a unique capability of LCP to form compact, vertically integrated (3-D) RF system-on-a-package modules.     

PCB integrated inductors for low power DC/DC converter

This paper discusses the use of printed circuit board (PCB) integrated inductors for low power DC/DC buck converters. Coreless, magnetic plates and closed core structures are compared in terms of achievable inductance, power handling and efficiency in a footprint of 10 /spl times/ 10 mm/sup 2/. The magnetic layers consist of electroplated NiFe, so that the process is fully compatible with standard PCB process. Analytic and finite element method (FEM) methods are applied to predict inductor performance for typical current waveforms encountered in a buck converter. Conventional magnetic design procedures are applied to define optimum winding and core structures for typical inductor specifications. A 4.7 /spl mu/H PCB integrated inductor with dc current handling of up to 500 mA is presented. This inductor is employed in a 1.5 W buck converter using a commercial control integrated circuit (IC). The footprint of the entire converter measures 10 /spl times/ 10 mm/sup 2/ and is built on top of the integrated inductor to demonstrate the concept of integrated passives in power electronic circuits to achieve ultra flat and compact converter solutions.     

Technology for very dense hybrid detector arrays using electroplated indium solderbumps

This paper presents a detailed overview of the process steps involved in the hybrid integration process of III-V infrared detector arrays and silicon readout electronics. This process is divided in distinct parts: the postprocessing of the Silicon readout circuit, the Indium solderbump formation by electroplating and the flip-chip process. In contrast to commercially available hybrid arrays, the indium solderbump technology is applied to the III-V array only and not to the silicon readout. This causes specific requirements to the III-V metallization sequence prior to electroplating in order to obtain proper reflow. Two different silicon postprocessing schemes are described. Arrays of 128/spl times/128, 256/spl times/256 and 320/spl times/256 In(Ga)As and InAsSb photovoltaic infrared detectors have been integrated with dedicated in-house and commercial readout using this process. The feasibility of achieving 10 /spl mu/m hybrid integration pitch is also shown.