低功耗优先的片上网络映射优化方法

在分析片上网络通讯功耗与通讯流量的关系模型的基础上,针对片上网络设计中的映射问题,提出了一种新的降低通讯功耗的映射方法,该方法首先对映射过程做预处理,划分成若干候选图,将通讯量大的IP核映射到与其他资源节点距离较短的位置上,利用预处理的结果产生初始解,结合流量估算技术对映射空间动态搜索,从而实现将通讯任务图中的IP核映射到NoC结构图的资源节点上.实验结果表明该方法能有效地降低NoC的通讯流量,从而更加适合求解片上网络的低功耗映射问题.     

面向通信能耗的3D NoC映射研究

对于传统的平面结构,三维片上网络(3D NoC)具有更好的集成度和性能,在单芯片内部可以集成更多的处理器核。3D NoC作为2D NoC的结构拓展,在性能提高和低功耗设计方面更具优越性,成为多核系统芯片结构的主流架构。映射就是应用某种算法寻找一种最优方案,将通信任务图的子任务分配到NoC的资源节点上,保证NoC的通信能耗最小。参照2D NoC的研究方法,提出了针对3D网格NoC的通信能耗模型,采用蚁群算法实现了面向通信能耗的NoC映射。实验结果表明,面向不同网络规模的3D网格NoC平台,蚁群映射同随机映射相比,通信能耗降低可以达23%～42%。     

基于网络监控器的专用片上网络动态容错路由

针对专用片上网络（Network on Chip,NoC）全局通信事务管理和可靠性设计问题,提出片上网络监控器的概念,用于获取全局网络实时状态信息及执行路径分配算法,基于此提出一种动态路由机制DyRS-NM.该机制能检测和定位NoC中的拥塞和故障链路,并能区分瞬时和永久性链路故障,采用重传方式避免瞬时故障,通过重新路由计算绕开拥塞和永久性故障.设计实现了RTL级网络监控器和与之通信的容错路由器模块,并将MPEG4解码器应用映射至基于网络监控器的4×4Mesh结构NoC体系结构中,验证了系统性能以及面积功耗开销.相比静态XY路由和容错动态路由FADR,DyRS-NM机制在可接受的开销代价下获得了更优的性能.     

片上网络存储器的BIST电路设计

片上网络（Network-on-Chip ,NoC）作为解决片上系统存在的问题而提出的一种解决方案,正受到越来越多的关注,测试技术是NoC设计工作的重要组成部分。该设计针对NoC系统中SRAM存储器模块,研究了SRAM的故障模型,建立了片上网络通信架构的功能模型,复用片上网络作为测试存取路径,设计完成了基于M arch C＋算法的BIST电路设计。该方案采用Verilog语言完成设计,并且在基于FPGA的NoC系统平台上实现了对SRAM的测试。实验结果表明,在面积开销增加较小的情况下,该方法具有较高的故障覆盖率。     

NoC系统设计的研究

片上网络研究涉及从物理设计到体系结构、系统应用、设计方法和工具等诸多方面.文中从系统结构的角度总结了片上网络设计的一些主要研究内容和NoC技术研究发展方向.     

基于FPGA的NoC验证平台的构建

针对基于软件仿真片上网络NoC（Network on Chip）效率低的问题,提出基于FPGA的NoC验证平台构建方案。该平台集成可重用的流量产生器TG（Traffic Generation）,流量接收器TR（Traffic Receiver）以及NoC软件,用于对NoC原型系统进行功能验证和性能评估。实际设计一个多核NoC,并用该平台对其进行FPGA验证,结果表明该平台的验证速度比软件仿真提高16000倍以上,并能对多种不同结构、路由算法、流控策略的NoC进行功能验证和性能评估。     

不规则2D Mesh NoC映射算法研究

片上网络(NoC)因其分层通讯结构而有望成为未来动态重构片上系统的支撑技术,针对复杂片上系统中可能集成各种规模IP的实际情况,对不规则2D mesh拓扑结构的NoC进行了研究,建立了其映射算法的数学模型和优化目标函数,提出了保证网格不重叠约束条件的数学表达和IP间通信距离的求解方法,采用一个视频解码器实例,给出了映射算法模拟结果和分析,并探讨了布局结果的FPGA实现.     

基于通讯的NoC设计

近年来，一种全新的集成电路体系结构——Network on Chip（NoC）已经成为徽电子学科研究的热点佃题之一，其核心思想是将计算机网络技术移植到芯片设计中来，从体系结构上彻底解决片上通讯的瓶颈问题。文章提出了一种基于通讯的NoC设计方法，通过监控和协调NoC的网络通讯来获得更好的性能．并总结了实现该设计方法所必须研究的关键技术。     

片上网络技术发展现状及趋势浅析

半导体制造工艺的快速发展使得片上可以集成更大规模的硬件资源,片上网络的研究试图解决芯片中全局通信问题,使得从基于计算的设计转变为基于通信的设计,并实现可扩展的通信架构.本文回顾和总结了现有NoC研究工作,指出NoC是当前片上通信发展的主流趋势,并分析了当前NoC关键技术瓶颈,最后预测了多核的技术和产业发展趋势.     

应用于片上网络的BCH码的设计与实现

本文对差错控制编码技术在片上网络(NoC)中的应用进行了研究。通过对三种纠错码在纠错能力、码率、面积和功耗等方面的折中,本文设计实现了适用于片上网络通信的BCH码,并给出了仿真结果。最后将BCH码应用在Hermes NoC平台上,成功地实现了一个基于BCH码的交换—交换的NoC差错控制系统。     

A multiobjective scatter search algorithm for fault-tolerant NoC mapping optimisation

Mapping IP cores to an on-chip network is an important step in Network-on-Chip (NoC) design and affects the performance of NoC systems. A mapping optimisation algorithm and a fault-tolerant mechanism are proposed in this article. The fault-tolerant mechanism and the corresponding routing algorithm can recover NoC communication from switch failures, while preserving high performance. The mapping optimisation algorithm is based on scatter search (SS), which is an intelligent algorithm with a powerful combinatorial search ability. To meet the requests of the NoC mapping application, the standard SS is improved for multiple objective optimisation. This method helps to obtain high-performance mapping layouts. The proposed algorithm was implemented on the Embedded Systems Synthesis Benchmarks Suite (E3S). Experimental results show that this optimisation algorithm achieves low-power consumption, little communication time, balanced link load and high reliability, compared to particle swarm optimisation and genetic algorithm.     

面向实时数字信号系统关键链路延时的NoC映射方法研究

该文在面向功耗优化的经典NoC设计平台和映射算法基础上,针对实时数字信号处理电路固有的实时性特征,提出了一种新的面向最小化系统关键链路延时的NoC自主映射模型MM-Map。该模型在满足处理单元处理容限和链路带宽的约束下,采用基本遗传算法完成延时目标的优化求解。实验结果表明,该模型能节约一定硬件资源的消耗,得到近似全局最优延时解,映射过程简单,收敛效果好。     

A multi-objective adaptive immune algorithm for multi-application NoC mapping

Current SoC design trends are characterized by the integration of larger amount of IPs targeting a wide range of application fields. Such multi-application systems are constrained by a set of requirements. In such scenario network-on-chips (NoC) are becoming more important as the on-chip communication structure. Designing an optimal NoC for satisfying the requirements of each individual application requires the specification of a large set of configuration parameters leading to a wide solution space. It has been shown that IP mapping is one of the most critical parameters in NoC design, strongly influencing the SoC performance. IP mapping has been solved for single application systems using single and multi-objective optimization algorithms. In this paper we propose the use of a multi-objective adaptive immune algorithm (M²AIA), an evolutionary approach to solve the multi-application NoC mapping problem. Latency and power consumption were adopted as the target multi-objective functions. To compare the efficiency of our approach, our results are compared with those of the genetic and branch and bound multi-objective mapping algorithms. We tested 11 well-known benchmarks, including random and real applications, and combines up to 8 applications at the same SoC. The experimental results showed that the M²AIA decreases in average the power consumption and the latency 27.3 and 42.1 % compared to the branch and bound approach and 29.3 and 36.1 % over the genetic approach.     

Hardware implementation of fault tolerance NoC core mapping

Due to performance and reliability, network on chip (NoC) is considered to be the future generation interconnect technique for multiple cores in a chip. This paper proposes a system level core mapping technique which improves the performance of the whole system, while rectifying the temporary faults and permanent faults in the system using error correcting codes and spare core. This technique mainly focuses on the core mapping and faults on the system. This results in reliable core mapping and improved performance when a fault-related error occurs on an NoC. At last, the proposed core mapping technique is simulated and verified on FPGA board (Kintex-7 FPGA KC705 Evaluation Kit).     

Optimized mapping algorithm to extend lifetime of both NoC and cores in many-core system

Fast aging of components has become one of the major concerns in Systems-on-Chip with further scaling of the submicron technology, which is accelerated when the working conditions are improper, such as unbalanced components’ utilization. Moreover, in the process of the applications of mapping algorithm, the imbalance of component utilization is more likely to occur. The reason is that the mapping algorithm in the Network-on-Chip (NoC) domain may frequently select some routers/links for mapping while others are underutilized. Consequently, the highly utilized components may age faster than others that results in disconnecting the related cores from the network. To solve this problem, we have proposed a lifetime-aware mapping algorithm named LBC + LBL, which has simultaneously taken the aging of core and link into account when applying the mapping. In this paper, the lifetime is modeled as a resource consumed over time and a lifetime budget metric is accordingly defined. A suitable node, which has the maximum lifetime budget, is selected for mapping. Experimental results show that the proposed lifetime-aware mapping algorithm (LBC + LBL) could improve the minimal mean time to failure (MTTF) of NoC about 15.1%, compared with the mapping algorithm only considering the aging of cores.     

Dynamic adaptive discrete particle swarm optimization algorithm based method on low-power mapping in network-on-chip

Compared to 2D NoC, 3D NoC has better integrated density and system performance, which was a reliable method to solve the problem about low-power mapping. On the basis of the traditional particle swarm optimization algo-rithm (PSOA), a dynamic adaptive discrete particle swarm optimization algorithm (DADPSOA) was proposed . Parame-ter in this algorithm was adjusted dynamically based on the degree of early convergence and the charge of individual adap-tive value to approach the optimal solution. At the same time, the reasonable structure of the particles was made aiming at reducing the time complexity of this algorithm. Experimental results show that comparing with the random mapping, genetic algorithm (GA), PSOA and dynamic ant colony algorithm (DACA), DADPSOA can save the execution time, reduce the communication power consumption of mapping results. The power consumption of the task graph is reduced.     

连接圭从IP核的片上网络路由器结构

随着单个芯片上集成的元器件数目不断增加,功耗问题也变得越来越突出。片上网络虽然能够从理论上解决传统总线结构带来的种种问题,但其功耗问题在某些具体应用中却变成了关键的制约因素。路由器作为片上网络的核心部件,其结构直接影响片上网络的性能。路由器的功耗问题已经成为片上网络领域一个热点问题。本文运用最优化理论对连接主从IP核的片上网络路由器结构进行优化设计,并运用路由器的功耗模型对功耗问题进行了分析。最后运用OPNET仿真软件对路由器的交换机制和路由算法进行分析对比,得出最终结论。