Process study and optimization for fabrication of poly‐Si thin‐film transistors on plastic substrates

Abstract— A complete poly‐Si thin‐film transistor (TFT) on plastic process has been optimized to produce TFT arrays for active‐matrix displays. We present a detailed study of the poly‐Si crystallization process, a mechanism for protecting the plastic substrate from the pulsed laser used to crystallize the silicon, and a high‐performance low‐temperature gate dielectric film. Poly‐Si grain sizes and the corresponding TFT performance have been measured for a range of excimer‐laser crystallization fluences near the full‐melt threshold, allowing optimization of the laser‐crystallization process. A Bragg reflector stack has been embedded in the plastic coating layers; its effectiveness in protecting the plastic from the excimer‐laser pulse is described. Finally, we describe a plasma pre‐oxidation step, which has been added to a low‐temperature (<100°C) gate dielectric film deposition process to dramatically improve the electrical properties of the gate dielectric. These processes have been integrated into a complete poly‐Si TFT on plastic fabrication process, which produces PMOS TFTs with mobilities of 66 cm² /V‐sec, threshold voltages of ?3.5 V, and off currents of approximately 1 pA per micron of gate width.     

Amorphous‐silicon thin‐film transistor on soda‐lime glass

Abstract— Amorphous‐silicon (a‐Si:H) thin‐film transistors (TFTs) on soda‐lime glass were fabricated by using a diffusion barrier and a low‐temperature process at 200°C. The silicon nitride barrier was optimized in terms of diffusion blocking effectiveness, film adhesion, and surface finish. TFTs on soda‐lime glass achieved a saturation mobility 0.47 cm²/V‐sec, threshold voltage of 0 V, an off‐current of 7.7×10^?11 A, and a sub‐threshold swing of 1.0 V/dec. From diffusion experiments, a 30,000‐hour lifetime for the TFT device at 80°C was estimated, and the robustness of the silicon nitride barrier against long‐term migration of sodium was demonstrated.     

Organic thin‐film devices on paper substrates

Abstract— A high‐performance polymer thin‐film transistor fabricated on a paper substrate has been demonstrated. As a water barrier layer, parylene was coated on a paper substrate by using a vacuum deposition process. Using poly (3‐hexylthiophene) as an active layer, a polymer thin‐film transistor with a field‐effect mobility of up to 0.086 cm²/V‐sec and an on/off ratio of 10⁴ was achieved. The fabrication of a polymer thin‐film transistor built on an inexpensive paper substrate is expected to open a channel for future applications in flexible and disposable electronics with extremely low cost.     

Effects of gate‐bias stress on ZnO thin‐film transistors

Abstract— The effects of gate‐bias and thermal stress on the stability issues of zinc oxide thin film transistors (ZnO TFTs) deposited on glass substrates were investigated. The shift in threshold voltage for devices undergoing various post‐growth annealing conditions using a stretched‐exponential formalism was analyzed. The analysis indicated that the extracted parameters such as the time constant and the effective energy barrier (E^τ) can be correlated to the device trap states associated with the annealing conditions. Improvement in the channel conductance and interface quality, hence the resultant device stability, can therefore be resumed when subject to a thermal treatment at 400°C for 30 minutes compared with those annealed for a shorter time.     

Compact modeling of amorphous‐silicon thin‐film transistors with BSIM3

Abstract— A novel approach of modeling a‐Si:H TFTs with the industry‐standard BSIM3 compact model is presented. The described approach defines the a‐Si:H TFT drain current and terminal charges as explicit functions of terminal voltages using a minimum set of BSIM3 parameters. The set of BSIM3 parameters is chosen based on the electrical and physical characteristics of the a‐Si:H TFT and their values extracted from measured data. By using the selected BSIM3 model parameters, the a‐Si:H TFT is simulated inside SPICE to fit the simulated I‐V and C‐V curves with the measured results. Finally, the extracted BSIM3 model is validated by simulating the kickback voltage effect in an AMLCD pixel array.     

Letter: Solution‐processed flexible zinc‐tin oxide thin‐film transistors on ultra‐thin polyimide substrates

In this letter, solution‐processed flexible zinc‐tin oxide (Z_0.35T_0.65O_1.7) thin‐film transistors with electrochemically oxidized gate insulators (AlOx:Nd) fabricated on ultra‐thin (30 µm) polyimide substrates are presented. The AlOx:Nd insulators exhibited wonderful stability under bending and excellent insulating properties with low leakage current, high dielectric constant, and high breakdown field. The device exhibited a mobility of 3.9 cm²/V · s after annealing at 300 °C. In addition, the flexible device was able to maintain the electricity performance under various degrees of bending, which was attributed to the ultra‐thin polyimide substrate.     

Stress control for overlay registration in a‐Si:H TFTs on flexible organic‐polymer‐foil substrates

Abstract— Mechanical stress in hydrogenated amorphous‐silicon (a‐Si:H) thin‐film transistors (TFTs) is becoming an important design parameter, especially when the TFTs are made on compliant substrates. Excessive stress always has been avoided to prevent film fracture and peeling. Now, attention is turning to the effects of stress on the TFT backplane dimensions and hence on the overlay alignment. The goal is to keep the size of the circuit‐on‐substrate composite structure the same at successive critical photolithographic steps. This is done most easily by keeping the structure flat. We show that a compensating stress can be dialed into the silicon nitride SiN_x) gate dielectric to also keep the substrate size constant. Varying the stress in the SiN_x gate dielectric did not significantly change the as‐fabricated TFT characteristics.     

Flexible thin‐film transistors application of amorphous tin oxide‐based semiconductors

The structural, optical, and electrical properties of Si‐doped SnO₂ (STO) films were investigated in terms of their potential applications for flexible electronic devices. All STO films were amorphous with an optical transmittance of ~90%. The optical band gap was widened as the Si content increased. The Hall mobility and carrier density were improved in the SnO₂ with 1 wt% Si film, which was attributed to the formation of donor states. Si (1 wt%) doped SnO₂ thin‐film transistor exhibited a good device performance and good stability with a saturation mobility of 6.38 cm²/Vs, a large I_on/I_off of 1.44 × 10⁷, and a SS value of 0.77 V/decade. The device mobility of a‐STO TFTs at different bending radius maintained still at a high level. These results suggest that a‐STO thin films are promising for fabricating flexible TFTs.     

Fabrication of low‐temperature‐polysilicon thin‐film transistors on flexible substrates using excimer‐laser crystallization

Abstract— Low‐temperature‐polysilicon thin‐film transistors (LTPS TFTs) were fabricated on polymer substrates using sputtered amorphous‐Si (a‐Si) films and excimer‐laser crystallization. The in‐film argon concentration of a‐Si films was minimized as low as 1.6% by using an argon/helium gas mixture as the sputtering gas. By employing XeCl excimer‐laser crystallization, poly‐Si films were successfully fabricated on polymer substrates with an average grain size of 400 nm. With a four‐mask process, a poly‐Si TFT was fabricated with a fully self‐aligned top‐gate structure, and the pMOS TFT device showed a field‐effect mobility of 63.6 cm²/V‐sec, ON/OFF ratio of 10⁵, and threshold voltage of ?1.5 V.     

Flexible electrophoretic display driven by solution‐processed organic thin‐film transistors

Abstract— An organic thin‐film‐transistor (OTFT) backplane has been fabricated by using a solution‐processed organic semiconductor (OSC) and organic insulators. The OSC, a peri‐xanthenoxanthene derivative, provides a mobility of 0.5 cm²/V‐sec. These organic materials enhance the mechanical flexibility of the backplane. The developed backplane successfully drives a 13.3‐in. flexible UXGA electrophoretic display that can operate when bent at a radius of 5 mm.     

Modeling of threshold‐voltage‐shift dependency on drain bias in amorphous‐silicon thin‐film transistors in active‐matrix organic light‐emitting‐diode displays

Abstract— A theoretical model to interpret appearances of the threshold voltage shift in hydrogenated amorphous‐silicon (a‐Si:H) thin‐film transistors (TFTs) is developed to better understand the instability of a‐Si:H TFTs for the driving transistors in active‐matrix organic light‐emitting‐diode (AMOLED) displays. This model assumes that the defect creation at channel in a‐Si:H is proportional to the carrier concentration, leading to the defect density varying along the channel depending on the bias conditions. The model interprets a threshold‐voltage‐shift dependency on the drain‐stress bias. The model predicts the threshold voltage shift stressed under a given gate bias applying the drain saturation voltage is 66% of that with zero drain bias, and it even goes down to 50–60% of that when stressed by applying twice the drain saturation voltage.     

Organic‐polymer thin‐film transistors for active‐matrix flat‐panel displays?

Abstract— Organic‐polymer‐based thin‐film transistors (OP‐TFTs) look very promising for flexible, large‐area, and low‐cost organic electronics. In this paper, we describe devices based on spin‐coated organic polymer that reproducibly exhibit field‐effect mobility values around 5 × 10^?3 cm²/V‐sec. We also address fabrication, performance, and stability issues that are critical for the use of such devices in active‐matrix flat‐panel displays.     

High‐performance vacuum‐processed metal oxide thin‐film transistors: A review of recent developments

Since 2010, vacuum‐processed oxide semiconductors have greatly improved with the publication of more than 1,300 related papers. Although the number of researches on oxide semiconductors has continued to increase year by year, the average field‐effect mobility of oxide semiconductor thin‐film transistors (TFTs) has not shown significant improvement; from 2010 to 2018; the average field‐effect mobility of vacuum‐processed n‐type oxide TFTs is around 20 cm²/Vs. To investigate the obstacles for performance improvements, the latest progress and researches on vacuum‐processed oxide semiconductor TFTs for high performance over the past decade are highlighted, along with the pros and cons of each technology. Finally, complementary metal oxide semiconductor (CMOS) logic circuits composed of both n‐ and p‐type oxide semiconductor TFTs are introduced, and future prospects for this state‐of‐the‐art research on the oxide semiconductors are presented.     

Temporary bond—debond technology for high‐performance transistors on flexible substrates

Abstract— A processing technology based upon a temporary bond—debond approach has been developed that enables direct fabrication of high‐performance electronic devices on flexible substrates. This technique facilitates processing of flexible plastic and metal‐foil substrates through automated standard semiconductor and flat‐panel tool sets without tool modification. The key to processing with these tool sets is rigidifying the flexible substrates through temporary bonding to carriers that can be handled in a similar manner as silicon wafers or glass substrates in conventional electronics manufacturing. To demonstrate the power of this processing technology, amorphous‐silicon thin‐film‐transistor (a‐Si:H TFT) backplanes designed for electrophoretic displays (EPDs) were fabricated using a low‐temperature process (180°C) on bonded‐plastic and metal‐foil substrates. The electrical characteristics of the TFTs fabricated on flexible substrates are found to be consistent with those processed with identical conditions on rigid silicon wafers. These TFTs on plastic exhibit a field‐effect mobility of 0.77 cm²/V‐sec, on/off current ratio >10⁹ at Vds = 10 V, sub‐threshold swing of 365 mV/dec, threshold voltage of 0.49 V, and leakage current lower than 2 pA/μm gate width. After full TFT‐array fabrication on the bonded substrate and subsequent debonding, the flexible substrate retains its original flexibility; this enables bending of the EPD display without loss in performance.     

Experimental decomposition of the positive bias temperature stress‐induced instability in self‐aligned coplanar InGaZnO thin‐film transistors and its modeling based on the multiple stretched‐exponential functions

Decomposition of the positive gate‐bias temperature stress (PBTS)‐induced instability into contributions of distinct mechanisms is experimentally demonstrated at several temperatures in top‐gate self‐aligned coplanar amorphous InGaZnO thin‐film transistors by combining the stress‐time‐divided measurements and the subgap density‐of‐states (DOS) extraction. It is found that the PBTS‐induced threshold voltage shift (ΔV_T) consists of three mechanisms: (1) increase of DOS due to excess oxygen in the active region; (2) shallow; and (3) deep charge trapping in the gate insulator components. Corresponding activation energy is 0.75, 0.4, and 0.9 eV, respectively. The increase of DOS is physically identified as the electron‐capture by peroxide. Proposed decomposition is validated by reproducing the PBTS time‐evolution of I–V characteristics through the technology computer‐aided design simulation into which the extracted DOS and charge trapping are incorporated. It is also found that the quantitative decomposition of PBTS‐induce ΔV_T accompanied with the multiple stretched‐exponential models enables an effective assessment of the complex degradation nature of multiple PBTS physical processes occurring simultaneously. Our results can be easily applied universally to any device with any stress conditions, along with guidelines for process optimization efforts toward ultimate PBTS stability.     

Single‐source dual‐layer amorphous IGZO thin‐film transistors for display and circuit applications

In this study, the authors report on high‐quality amorphous indium–gallium–zinc oxide thin‐film transistors (TFTs) based on a single‐source dual‐layer concept processed at temperatures down to 150°C. The dual‐layer concept allows the precise control of local charge carrier densities by varying the O₂/Ar gas ratio during sputtering for the bottom and top layers. Therefore, extensive annealing steps after the deposition can be avoided. In addition, the dual‐layer concept is more robust against variation of the oxygen flow in the deposition chamber. The charge carrier density in the TFT channel is namely adjusted by varying the thickness of the two layers whereby the oxygen concentration during deposition is switched only between no oxygen for the bottom layer and very high concentration for the top layer. The dual‐layer TFTs are more stable under bias conditions in comparison with single‐layer TFTs processed at low temperatures. Finally, the applicability of this dual‐layer concept in logic circuitry such as 19‐stage ring oscillators and a TFT backplane on polyethylene naphthalate foil containing a quarter video graphics array active‐matrix organic light‐emitting diode display demonstrator is proven.     

Characteristics and stability of improved re‐crystallized metal‐induced laterally crystallized polycrystalline‐silicon thin‐film transistors for display applications

Abstract— The performance of high‐temperature re‐crystallized (RC) metal‐induced laterally crystallized (MILC) polycrystalline‐silicon (poly‐Si) thin‐film transistors (TFT) have been improved by (1) patterning the active islands before MILC, (2) removing nickel‐containing residues using acid cleaning, (3) using heavily boron‐doped poly‐Si gates to achieve threshold voltage symmetry, and (4) double‐implanting n‐type source/drain junctions. A 30‐MHz driver circuit based on this improved technology was demonstrated. The reliability of optimized RC‐MILC poly‐Si TFTs has not been adversely affected by residual nickel‐containing contaminants in the TFT channel regions.     

100‐MHz CMOS circuits directly fabricated on plastic using sequential laterally solidified silicon

Abstract— CMOS TFT circuits were fabricated on plastic using sequential laterally solidified silicon combined with a low‐temperature CMOS process. The unity‐gain frequencies of the best of NMOS TFTs are greater than 250 MHz, and the CMOS ring oscillators operate at 100 MHz. To the best of the authors' knowledge, these are the highest‐frequency circuits ever fabricated directly on plastic. This high‐performance CMOS‐on‐plastic process can be applied to the fabrication of AMLCD integrated drivers and AMOLED pixels on plastic substrates.     

A framework for assessing amorphous oxide semiconductor thin‐film transistor passivation

Amorphous oxide semiconductor thin‐film transistors (TFTs) are moving towards commercialization for a variety of display applications. Invariably, display applications require a bottom‐gate TFT configuration in which passivation of the top channel layer surface is required. The objective of this work is to propose a conceptual model framework for assessing TFT passivation schemes, within the context of amorphous oxide semiconductor electronics. This model involves first estimating the energy of the charge neutrality levels (CNLs) for the channel and passivation layers. Then, an energy band diagram is drawn to establish the relative position of these CNLs prior to their establishment of intimate contact. A situation in which the passivation layer CNL is below that of the channel layer CNL is considered undesirable because interface state electronic transfer from the channel to the passivation layer leads to formation of an accumulation layer at this interface. Although the opposite case in which the passivation layer CNL is above that of the channel layer CNL is more desirable, the ideal situation would be when both CNLs align because no interface state electronic transfer would occur. This framework is then employed in a discussion of the passivation of indium gallium zinc oxide and zinc tin oxide bottom‐gate TFTs.     

Process development of inverted‐staggered amorphous InGaZnO thin‐film transistors with wet‐etched electrodes

Process development of inverted‐staggered amorphous InGaZnO thin‐film transistors (a‐IGZO TFTs) with wet‐etched electrodes was employed in this paper. Five metals (Al, Cu, Ti, Ta, and Cr) as well as various etchants were comparatively investigated, indicating H₂O₂ based solution etched Ta films were good candidates for the wet‐etched electrodes of a‐IGZO TFTs. The aforementioned findings along with other improving attempts successfully established inexpensive processing steps and conditions with which stable a‐IGZO TFTs were finally fabricated. The device performance was reasonably good enough (μ_FE of 6.0 cm²/V·s, V_th of 2.5 V, SS of 1.8 V/decade, and I_on/I_off of 10⁶) to meet the requirements of applications especially for small‐sized flat panel displays.