Fault Detection for a Class of Nonlinear Singular Systems Over Networks with Mode-Dependent Time Delays

In this paper, the fault detection problem is investigated for a class of nonlinear discrete-time singular systems over networks with mode-dependent time delays. The transmission delays are modeled as a Markov chain with partly known distribution, which takes values in a finite state space. By augmenting the original nonlinear singular system and the fault detection filter, the resulting fault detection dynamics is formulated as an \(H_{\infty }\) filtering problem of a singular Markov jump system. Regular, casual, stochastically stable of the fault detection dynamics and the prescribed \(H_{\infty }\) attenuation level are obtained by the mode-dependent Lyapunov functional approach. The desired fault detection filter is obtained in terms of a series of feasible LMIs. A numerical example is presented to show the effectiveness of the developed technique.     

Non-Fragile H_{\infty } Filter Design for Uncertain Stochastic Nonlinear Time-Delay Markovian Jump Systems

This paper investigates the problem of non-fragile and mode-dependent \(H_{\infty }\) filter design for a class of nonlinear stochastic Markovian jump systems with mode-dependent time-varying delays and norm-bounded parameter uncertainties. The non-fragile and mode-dependent filter to be designed is assumed to include multiplicative gain variations which result from inaccuracies in filter implementation, and the desired filter ensures the filtering error system is not only exponentially mean-square stable, but also satisfies a prescribed \(H_{\infty }\) -norm level for all admissible uncertainties. A stochastic Lyapunov–Krasovskii function is proposed to reflect the information of Markovian jump modes and the mode-dependent time-varying delays, and a set of strict linear matrix inequalities are utilized to derive sufficient conditions that guarantee the desired filter can be constructed. A numerical example and a vertical take-off and landing (VTOL) helicopter system are utilized to illustrate the effectiveness and usefulness of the main results obtained.     

Robust H_{\infty } filtering for uncertain two-dimensional continuous systems with time-varying delays

This paper deals with the problem of delay-dependent robust $H_{\infty }$ H ∞ filtering for uncertain two-dimensional (2-D) continuous systems described by Roesser state space model with time-varying delays, with the uncertain parameters assumed to be of polytopic type. A sufficient condition for $H_{\infty }$ H ∞ noise attenuation is derived in terms of linear matrix inequalities, so a robust $H_{\infty }$ H ∞ filter can be obtained by solving a convex optimization problem. Finally, some examples are provided to illustrate the effectiveness of the proposed methodology.     

Delay-dependent robust H_\infty control for 2-D discrete nonlinear systems with state delays

This paper investigates the problem of robust \(H_\infty \) control for a class of 2-D (two-dimensional) discrete state delayed systems with sector nonlinearity described by a model of Roesser type. Firstly, a delay-dependent sufficient condition of robust exponential stability for such 2-D discrete systems is derived in linear matrix inequalities (LMIs) form. Secondly, a delay-dependent exponential stability criterion with \(H_\infty \) performance for the considered systems is also proposed. Then a state feedback \(H_\infty \) controller is constructed based on the above results. Finally, numerical examples are given to illustrate the effectiveness of the proposed method.     

Efficient Reverse Converters for 4-Moduli Sets {2^{2n-1}-1, 2^{n}, 2^{n}+1, 2^{n}-1} and {2^{2n-1}, 2^{2n-1}-1, 2^{n}+1, 2^{n}-1} Based on CRTs Algorithm

Speed and complexity of a reverse converter are two important factors that affect the performance of a residue number system. In this paper, two efficient reverse converters are proposed for the 4-moduli sets {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } and {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } with 5 \(n\) -bit and 6 \(n\) -bit dynamic range, respectively. The proposed reverse converter for moduli set {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed based on CRT and New CRT-I algorithms and in two-level structure. Also, an efficient reverse converter for moduli set {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed by applying New CRT-I algorithm. The proposed reverse converters are based on adders and hence can be simply implemented by VLSI circuit technology. The proposed reverse converters offer less delay and hardware cost when compared with the recently introduced reverse converters for the moduli sets {2 \(^{n}+1\) , 2 \(^{n}-1\) ,2 \(^{n}\) , 2 \(^{2n+1}-1\) } and {2 \(^{n}+1\) , 2 \(^{n}-1\) , 2 \(^{2n}\) , 2 \(^{2n+1}-1\) }.     

Method for Designing Efficient Mixed Radix Multipliers

The multiplication of two signed inputs, \(A {\times } B\) , can be accelerated by using the iterative Booth algorithm. Although high radix multipliers require summing a smaller number of partial products, and consume less power, its performance is restricted by the generation of the required hard multiples of B ( \(\pm \phi B\) terms). Mixed radix architectures are presented herein as a method to exploit the use of several radices. In order to implement efficient multipliers, we propose to overlap the computation of the \(\pm \phi B\) terms for higher radices with the addition of the partial products associated to lower radices. Two approaches are presented which have different advantages, namely a combinatory design and a synchronous design. The best solutions for the combinatory mixed radix multiplier for \(64\times 64\) bits require \(8.78\) and \(6.55~\%\) less area and delay in comparison to its counterpart radix-4 multiplier, whereas the synchronous solution for \(64\times 64\) bits is almost \(4{\times }\) smaller in comparison with the combinatory solution, although at the cost of about \(5.3{\times }\) slowdown. Moreover, we propose to extend this technique to further improve the multipliers for residue number systems. Experimental results demonstrate that best proposed modulo \(2^{n}{-}1\) and \(2^{n}{+}1\) multiplier designs for the same width, \(64{\times }64\) bits, provide an Area-Delay-Product similar for the case of the combinatory approach and \(20~\%\) reduction for the synchronous design, when compared to their respective counterpart radix-4 solutions.     

Decentralized \mathcal{L}_{2}–\mathcal{L}_{\infty} Filtering for Interconnected Markovian Jump Systems with Delays

This paper deals with the problem of decentralized $\mathcal{L}_{2}$ – $\mathcal{L}_{\infty}$ filtering for a class of interconnected (or large-scale) Markovian jump systems with constant time delays. The purpose is to present delay-dependent conditions for the existence of mode-dependent decentralized filters, which guarantees that the filtering error system is stochastically stable with a prescribed $\mathcal{L}_{2}$ – $\mathcal{L}_{\infty}$ disturbance attenuation level. Such a purpose is achieved by using a mode-dependent centralized Lyapunov functional together with the so-called Jensen’s inequality. The obtained synthesis conditions are expressed in terms of linear matrix inequalities (LMIs), which leads to a convex design method for the concerned filters. An example including numerical and simulation results is provided finally to illustrate the effectiveness of the proposed design method.     

A 5 GHZ CMOS Power VCO with Novel Frequency-Modulation for RF Transmitter

A 5 GHz transformer-feedback power oscillator with novel frequency modulation (FM) up to 10 MHz is presented in this paper. The novel FM is achieved by a CMOS transistor between transformer and ground, which is designed for varying the equivalent inductance and mutual inductance of the transformer and shows no DC connection with the oscillation circuit. The major frequency tuning is realized by the variable capacitor which is controlled by a phase lock loop. The RF VCO with 210 MHz tuning range operates in class-E mode to achieve a cost-effective transmitter, which demonstrates a high DC-to-RF conversion efficiency of 39 %. A RF power of 15.1 dBm and phase noise better than \(-\) 109 dBc/Hz @ 100 kHz from the central frequency of 5.5 GHz is obtained with the biasing conditions V \(_\mathrm{ds}\) = 1.8 V and V \(_\mathrm{gs}\) = 0.65 V. The VCO also demonstrates an ultra-low voltage operation capability: with V \(_\mathrm{ds}\) = V \(_\mathrm{gs}\) = 0.6 V and DC power consumption of 9 mW, the output power is 4.5 dBm and the phase noise better than \(-\) 93 dBc/Hz @ 100 kHz. The die size of the transformer-feedback power oscillator is only \(0.4\times 0.6\) mm \(^{2}\) .     

Nanovoid Formation and Dynamics in He+-Implanted Nanocrystalline Silicon

Helium implantation in single crystal silicon is known to lead, after a proper thermal treatment, to the formation of voids with diameters ranging between 10 nm and 30 nm. Formation of voids is governed by the coalescence of vacancies created by implantation, initially trapping helium atoms. At high temperatures ( \({\ge}700^{\circ }\hbox {C}\) ), helium leaves the nanobubbles and outdiffuses, while the now empty voids grow in size and eventually change their shape to form tetrakaidecahedra (Wulff construction). In this communication, we report how He⁺ implantation in heavily boron-doped nanocrystalline silicon shows a completely different dynamics. Annealing at \(500^{\circ }\hbox {C}\) leads to the formation of large voids, located around grain boundaries, along with a large number of nanovoids with an average diameter of 2–4 nm and an estimated density of \(3\times 10^{17}\,\hbox {cm}^{-3}\) distributed throughout the grains. Annealing at higher temperature (up to \(1000^{\circ }\hbox {C}\) ) also induces a decrease of the void size with a change in their density, finally accounting to \(2\times 10^{18}\,\hbox {cm}^{-3}\) . The high temperature annealing also causes vacancy evaporation down to a depth of 80–100 nm from the outer surface. The possibility of obtaining a stable, uniform distribution of nanometer-sized voids is of major relevance as a novel tool for phonon and electron engineering in thermoelectric materials.     

Design of An Arcak-Type Generalized H_2 Filter for Delayed Static Neural Networks

In this paper, an Arcak-type generalized \(H_2\) filter is designed for a class of static neural networks with time-varying delay. By employing some inequalities and constructing a suitable Lyapunov functional, a delay-dependent condition is derived by means of linear matrix inequalities such that the filtering error system is globally asymptotically stable and a prescribed generalized \(H_2\) performance is achieved. It is shown that the design of such a desired filter for a delayed static neural network is successfully transformed into solving a convex optimization problem subject to some linear matrix inequalities. It is thus facilitated readily by some standard algorithms. A numerical example is finally provided to show the effectiveness of the developed approach. A comparison on the generalized \(H_2\) performance for different gain parameters of the activation function is also given.     

A 97 dB 400 MHz rail to rail fully differential opamp based on split length FGMOS-MOS cell

Recently introduced MOS-FGMOS split length cell has been used to increase the DC gain of a fully differential op amp. Resultant proposed opamp structure exhibits gain of 97 dB and unity gain bandwidth of 400 MHz with power consumption of 1.2 mW. An opamp design has been verified with Cadence Spectre using a 130 nm technology at 1.2 V and has a slew rate of \(53\,\hbox {V}/\mu \hbox {s}\) with a phase margin of \(78^{\circ }\) .     

Extended Robust \mathcal{H}_{2} and \mathcal{H}_{\infty} Filter Design for Discrete Time-Invariant Linear Systems with Polytopic Uncertainty

This paper is concerned with the problem of robust $\mathcal{H}_{2}$ and $\mathcal{H}_{\infty}$ filter design for discrete-time linear time-invariant systems with polytopic parameter uncertainties. Less conservative robust $\mathcal{H}_{2}$ and $\mathcal{H}_{\infty}$ filter design procedures are proposed in terms of single-parameter minimization problems with linear matrix inequality constraints. To this end, we generalize the filter structures available in the literature to date in such a way that the filter’s next state is built by summing the filter’s states over several samples from the past to the present. For stability of the filtering error system, the homogeneous polynomial parameter-dependent Lyapunov functions are employed. Finally, illustrative examples are given to demonstrate the merits of the proposed methods.     

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing

We propose an ultra-low power memory design method based on the ultra-low ( \(\sim \) 0.2 V) write-bitline voltage swing to reduce the write power dissipation for read-decoupled SRAM (RD-SRAM) cells. By keeping the write bitlines at ground level (0 V) during standby and charging them to a low voltage \(V_\mathrm{L}\) ( \(\sim \) 0.2 V) during write operations, the power dissipation for the write bitlines is greatly reduced (0.2 V/ \(V_\mathrm{DD})^{ 2 }\,\times \) 100 %) due to reduced voltage swing (from \(V_\mathrm{DD }\)  = 1.2 to 0.2 V) on the write bitlines. The proposed method is applicable to both dual-voltage and single-voltage operations. We analyze the proposed ultra-low write-bitline voltage swing method and investigate its reliability based on 10K Monte-Carlo simulations. We further verify the functionality and performance of our proposed design through measurements on the fabricated prototypes based on the 65 nm CMOS process. By means of a \(256 \times 64\) bit RD-SRAM memory implementation, we show that our proposed method reduces 87 % write power dissipation when compared to a conventional design.     

Positive L_1 Observer Design for Positive Switched Systems

This paper investigates the problem of \(L_1\) observer design for positive switched systems. Firstly, a new kind of positive \(L_1\) observer is proposed for positive switched linear delay-free systems with observable and unobservable subsystems. Based on the average dwell time approach, a sufficient condition is proposed to ensure the existence of the positive \(L_1\) observer. Under the condition obtained, the estimated error converges to zero exponentially, and the \(L_1\) -gain from the disturbance input to the estimated error is less than a prescribed level. Then the proposed design result is extended to positive switched systems with mixed time-varying delays, where the mixed time-varying delays are presented in the form of discrete delay and distributed delay. Finally, two numerical examples are given to demonstrate the feasibility of the obtained results.     

Construction of (2k,k, 2) Convolutional Codes with Double-Loop Cyclic Codes

In this paper, by taking multiple-time information in blocks into the coding of linear block codes, a new class of (2 \(k\) , \(k\) , 2) convolutional codes is constructed, by which a new way of constructing long codes with short ones is obtained. After that, the type of embedded codes is determined and the optimal values of the linear combination coefficients are derived by using a three-dimensional state transfer matrix to analyze and testify the constructing mechanism of the codes. Finally, the simulation experiment tests the error-correcting performance of the (2 \(k\) , \(k\) , 2) convolutional codes for different value of \(k\) , it is shown that the performance of the new convolutional codes compares favorably with that of traditional (2, 1, \(l\) ) convolutional codes.     

A Novel 2.5–3.1 GHz Wide-Band Low-Noise Amplifier in 0.18 \upmu \hbox {m} CMOS

Aiming for the simultaneous realization of constant gain, accurate input and output impedance matching and minimum noise figure (NF) over a wide frequency range, the circuit topology and detailed design of wide broadband low noise amplifier (LNA) are presented in this paper. A novel 2.5–3.1 GHz wide-band LNA with unique characteristics has been presented. Its design and layout are done by TSMC 0.18  \(\upmu \hbox {m}\) technology. Common gate stage has been used to improve input matching. In order to enhance output matching and reduce the noise as well, a buffer stage is utilized. Mid-stages which tend to improve the gain and reverse isolation are exploited. The proposed LNA achieves a power gain of 15.9 dB, a NF of 3.5 dB with an input return loss less than \(-\) 11.6, output return loss of \(-\) 19.2 to \(-\) 19 and reverse isolation of \(-\) 38 dB. The LNA consumes 54.6 mW under a supply voltage of 2 V while having some acceptable characteristics.     

Minimum payment collaborative sensing network using mobile phones

Mobile phones with embedded sensors have been applied in various collaborative sensing applications. To encourage mobile phone users to perform collaborative sensing, the data demanders usually pay mobile phone users for required data. In this paper, we study the Minimum Payment of Attaining the Required Data with mobile phones (MPARD) problem in collaborative sensing network: given sensing regions \(R = \{R_1, R_2, \ldots , R_m\}\) , the set of requisite data \(D_i\) for each sensing region \(R_i\) and a set of mobile phones \(M\) , the \(MPARD\) problem studies how to select mobile phones to obtain all the required data such that the data demanders’ total payment to mobile phone users is minimized. In reality, some systems need the fresh sensing data from mobile phones at each pre-determined time slot, and others don’t require the real-time data and the sensing data from previous time slots is also deemed useful. Based on the above two different requirements of data timeliness, we first define two subproblems derived from \(MPARD\) problem: \(MPARD_t\) and \(MPARD_p\) . After that, for each subproblem, we propose an approximation algorithm for the situation where the trajectories of mobile phones are determinate and a heuristic for the situation where trajectories are unknown. Simulation results demonstrate that our algorithms are efficient.     

A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

A fully integrated 0.18- \(\upmu \hbox {m}\) CMOS LC-tank voltage-controlled oscillator (VCO) suitable for low-voltage and low-power S-band wireless applications is proposed in this paper. In order to meet the requirement of low voltage applications, a differential configuration with two cross-coupled pairs by adopting admittance-transforming technique is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed VCO can operate at 0.4 V supply voltage. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosting circuit and the standard mode PMOS varactors in the proposed oscillator architecture. The simulation results show that the proposed VCO achieves phase noise of \(-\) 120.1 dBc/Hz at 1 MHz offset and 39.3 % tuning range while consuming only \(594~\upmu \hbox {W}\) in 0.4 V supply. Figure-of-merit with tuning range of the proposed VCO is \(-\) 192.1 dB at 3 GHz.     

E-TCAM: An Efficient SRAM-Based Architecture for TCAM

Ternary content addressable memories (TCAMs) perform high-speed search operation in a deterministic time. However, when compared with static random access memories (SRAMs), TCAMs suffer from certain limitations such as low-storage density, relatively slow access time, low scalability, complex circuitry, and higher cost. One fundamental question is that can we utilize SRAM to combine it with additional logic to achieve the TCAM functionality? This paper proposes an efficient memory architecture, called E-TCAM, which emulates the TCAM functionality with SRAM. E-TCAM logically divides the classical TCAM table along columns and rows into hybrid TCAM subtables and then maps them to their corresponding memory blocks. During search operation, the memory blocks are accessed by their corresponding subwords of the input word and a match address is produced. An example design of \(512\times 36\) of E-TCAM has been successfully implemented on Xilinx Virtex- \(5\) , Virtex- \(6\) , and Virtex- \(7\) field-programmable gate arrays (FPGAs). FPGA implementation results show that E-TCAM obtains \(33.33\)  % reduction in block-RAMs, \(71.07\)  % in slice registers, \(77.16\)  % in lookup tables, \(53.54\)  % in energy/bit/search, and offers \(63.03\)  % improvement in speed, compared with the best available SRAM-based TCAM designs.     

An Ideal Multi-secret Sharing Scheme Based on Connectivity of Graphs

Secure communication has become more and more important for many modern communication applications. In a secure communication, every pair of users need to have a secure communication channel (each channel is controlled by a server) In this paper, using monotone span programs we devise an ideal linear multi-secret sharing scheme based on connectivity of graphs. In our proposed scheme, we assume that every pair of users, \(p\) and \(q\) , use the secret key \(s_{pq} \) to communicate with each other and every server has a secret share such that a set of servers can recover \(s_{pq} \) if the channels controlled by the servers in this set can connect users, \(p\) and \(q\) . The multi-secret sharing scheme can provide efficiency for key management. We also prove that the proposed scheme satisfies the definition of a perfect multi-secret sharing scheme. Our proposed scheme is desirable for secure and efficient secure communications.