核心硅片的突破时机？

核心硅片赋予电子系统关键功能的芯片一是今年全球半导体产业中最热门的领域之一，预计其热度将保持到2010年。 核心硅片三剑客专用标准产品（ASSP），可编程逻辑器件（PLD）和专用集成电路（ASIC），第二季度销售额比第一季度增长3％，而第二季度通常是淡季。相比之下，据iSuppli，第二季度整体半导体产业仅比第一季度增长1．1％。更重要的是，第二季度核心硅片销售额比2005年同期上升12．7％，同比增幅再度高于整体半导体产业。     

关于EV Group

EV Group于1980年建立，EV Group是面对全球提供产品的供应商，主要产品包括片半导体硅片键合机（Wafer Bonder）、紫外对位曝光系统（Aligner）、光刻胶镀胶设备、清洗及检测系统，主要应用于半导体行业，微机电系统和纳米压印等技术领域。EV Group在硅片焊接市场（特别是S01焊接）拥有统治地位，在高级封装的平板印刷技术。微机电系统和纳米技术方面也处于领先地位。EV Group独一无二的三“I”策略，发明-创新-实施（Invent．Innovate—Implement）由垂直的基础构架支持。使得EV Group能快速回应新技术的发展。同时把新技术应用于生产制造的挑战中并加快大量生产的进度。EV Group总部设在Sch？rding。奥地利（Austria），EV Group的运作通过一个全球客户支持网络，     

大尺寸硅片背面磨削技术的应用与发展

集成电路芯片不断向高密度、高性能和轻薄短小方向发展，为满足IC封装要求，图形硅片的背面减薄成为半导体后半制程中的重要工序。随着大直径硅片的应用，硅片的厚度相应增大，而先进的封装技术则要求更薄的芯片，超精密磨削作为硅片背面减薄主要工艺得到广泛应用。本文分析了几种常用的硅片背面减薄技术，论述了的基于自旋转磨削法的硅片背面磨削的加工原理、工艺特点和关键技术，介绍了硅片背面磨削技术面临的挑战和取得的新进展。     

片架片盒的正确使用

在硅片加工过程中，大部分时间硅片是放在花兰及传片盒内的。如果花兰维护不当，会对成品率产生相当大的负作用。不过，大部分半导体厂家对周转硅片用品（花兰、传片盒等）很少引起重视。不恰当的处理会导致：a）加速花兰表面磨损，在硅片表面产生很多颗粒，b）花兰发生畸变，致使硅片装载出错，设备停机时间延长；（c）降低周转硅片用品的使用寿命。本文报道一些习惯作法，并提供一些可使这些问题产生的影响传至最小的建议。如今，一般认为管理部门应采取积极的态度，工作环境必须要求有正确的硅片处理方式。简单地改变一下操作方式——有…     

半导体硅片退火后检测工艺的发展探讨

半导体硅片退火工艺对生产硅片具有十分重要的作用,为此,本文加强对硅片的退火技术检测,希望能够控制硅片技术质量。因为自然界当中并不存在单体硅,硅主要以氧化物或者是硅酸盐的形式出现,需要通过提纯与精炼的方式才能够形成硅片。这个过程中硅需要进行退火工艺处理,消除硅片中氧施主的影响,内部缺陷也在这个过程中减少。这个工艺流程是制造半导体硅片的重要环节。退火后的技术检测则是实现硅片生产的最后一个环节,是确保硅片质量的重要基础。本文侧重对半导体硅片退火检测工艺发展情况进行具体阐述。     

硅片超精密磨床的发展现状

硅片超精密磨床是半导体集成电路(IC)制造中的关键装备,主要应用于IC制程中的硅片制备加工和IC后道制程中图形硅片的背面减薄。国外硅片超精密磨床制造技术发展很快,具有高精度化、集成化、自动化等特点。介绍了超精密磨床在大尺寸(≥φ300mm)硅片超精密加工中的应用状况,详细评述了国外先进硅片超精密磨床的特点,并指出了大尺寸硅片超精密加工技术的发展趋势。     

硅片在背面减薄工序中降低破片率的研究

随着半导体工业的发展,对芯片的厚度要求愈来愈薄。在半导体制造中通过对硅片进行背面减薄达到芯片变薄的目的。然而由于硅片的厚度变薄,在后续的制造过程中也增加了硅片破裂的概率。对于已经几乎加工完毕的芯片,破片造成的成本显然是相当高昂的。文章对硅片在背面减薄工序和流通环节中可能产生破片的因素进行了研究探索,通过对设备的部分装置进行改造,改进流通环节中的一些方法,经过总结数据,验证了硅片在背面减薄工序中降低破片率的可行性。     

硅材料的目前状况及发展趋势—1992年6月赴美考察情况报告

本文根据１９９２年ＳＥＭＩ国际会议和在旧金山举行的国际半导体设备和材料展览会上了解的情况，对目前硅片、多晶硅、ＳＯＩ和硅片技术标准规范的水平和发展趋势作了介绍。     

12英寸晶圆生产将进入快速增长阶段

近几年来,12英寸晶圆成为最具成本效益的半导体材料,产量也进入快速增长阶段。近日,市场研究公司iSuppli发布报告,预计2015年半导体代工厂商和集成设备制造商（IDM）将生产87．53亿平方英寸的硅片,较2010年产量增长近1倍（2010年硅片产量为47．994亿平方英寸）。     

盛美推出12英寸单片清洗技术用于清洗10nm超微颗粒

盛美半导体（上海）有限公司近日发表了十二英寸单片兆声波清洗设备的最新工艺，本工艺用于45nm技术及以下节点的十二英寸高端硅片清洗。盛美独家具有自主知识产权的清洗技术可以去除数十纳米超微小颗粒，同时使硅片表面的材料损失降到最低，并且不影响硅片表面的平整度。     

Wafer temperature measurement in a rapid thermal processor with modulated lamp power

Pyrometry methods utilizing modulated lamp power (“ripple”) were used to improve wafer temperature measurement and control in rapid thermal processing (RTP) for silicon integrated circuit production. Data from a manufacturing line where ripple pyrometers have been tested show significantly reduced wafer to wafer and lot to lot variations in final test electrical measurements and increased yields of good chips per wafer. The pyrometers, an outgrowth of Accufiber’s ripple technique, are used to compensate for ordinary production variations in the emissivities of the backsides of wafers, which face the pyrometers. Power to the heating lamps is modulated with oscillatory functions of time at either the power line frequency or under software control. Fluctuating and quasi-steady components in detected radiation are analyzed to suppress background reflections from the lamps and to correct for effective wafer emissivity. Sheet resistances of annealed wafers with high dose shallow As implants were used to infer temperature measurement capability over a range in backside emissivity. Emissivities are varied when depositing or growing one or more layers of silicon dioxide, silicon nitride, or polycrystalline silicon on the backsides of the wafers.     

Relationship between wafer fracture reduction and controlling during the edge manufacturing process

Given the trend towards wafers of a larger diameter, microelectronics circuits are driven by modern IC manufacturing technology. Silicon wafer breakage has become a major concern of all semiconductor fabrication lines because silicon wafer is brittle and high stresses are induced in the manufacturing process. Additionally, the production cost is increasing. Even a breakage loss of a few per cent drives up device costs significantly if wafers are broken near completion, but wafer breakage even near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength empolying a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.This work presents an approach for characterizing silicon wafer failure strength using a simple drop test, to improve our understanding of the stress accumulated in wafer bulk before failure. However, this work will describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unknown reasons. According to an analysis based on the material mechanical theory for the bevel lengths (A1, A2), the edge length and the bevel angle (θ) are optimized to design the edge profile of the produced wafer, to prevent wafer breakage. Restated, when proper material and process control techniques are utilized, silicon wafer breakage should be prevented. This work is the first to demonstrate the importance of understanding wafer strength using a simple mechanical approach.     

Prediction of the thickness for silicon wafers sawn by diamond wire saw

A higher yield and lower processing cost for the production of the silicon wafer can be realized by reducing the sliced thickness. However, a larger fracture probability is accompanied with the thinner silicon wafer, which limits the wafer thickness to be reduced. The contradiction between reducing wafer thickness and keeping a smaller fracture probability is an important problem for the industrial production of the silicon wafer. This paper investigates the influences of silicon wafer size and machining defects on the fracture probability in order to understand the essential relationship between damage information and fracture probability adequately. A theoretical model of the fracture probability for silicon wafer is proposed based on the probabilistic fracture mechanics to determine a proper thickness for wafers with different size. Furthermore, one method of predicting a proper thickness for silicon wafers sawn by diamond wire saw is developed. The thickness of 450-mm silicon wafer obtained by this proposed method is 920 µm, which is comparable with the value 925 µm specified by the International Technology Roadmap for Semiconductor. The comparison of these two values reveals the feasibility and correctness of this proposed method. The proposed model in this paper can be used to evaluate the fracture probability and predict a proper thickness for silicon wafers with different size, which is benefit to optimize the processing technology and decrease the breakage ratio for the wafer production.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

Experiment study on electroplated diamond wire saw slicing single-crystal silicon

This paper conducted the slicing experiments of single-crystal silicon using a reciprocating electroplated diamond wire saw. The machined wafer topography and wire wear were observed by using scanning electron microscope (SEM). The influences of process parameters and cutting fluids on single-crystal silicon wafer surface roughness (SR), subsurface micro-crack damage (SSD) depth, total thickness variation (TTV) and warp were investigated. The bonded interface sectioning technique was used to examine the cut wafers SSD depth. Study results show that a higher wire speed and lower ingot feed speed can produce lower wafer SR and SSD; the lower warp of wafer needs lower wire speed and ingot feed speed; and low wafer TTV can be obtained by an appropriate matching relationship between wire speed and ingot feed speed. The synthetic cutting fluid has a better total effect to improve the wafer quality. The pulled-out of diamond abrasives is the main wear form of wire, which indicates that more research on improving the abrasives retaining strength on wire surface should be investigated in fixed-abrasive wire manufacturing process, in order to improve the wire life and wire saw machining process.     

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100 μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100 μm can decrease the wafer warpage by 51.4%.     

高温离子注入靶盘设计

简要介绍了高温离子注入靶室的设计。通过设计辅助加热装置使离子注入时晶片表面温度达到500℃以上,并通过靶盘旋转和往返平移扫描的方式实现了晶片片内和片间的温度均匀性,满足了碳化硅掺杂、SOI晶片制造等特殊需要。     

线切割硅片表面探究

硅片的表面损伤层,关系到切割后破片率及面的形状等。通过对硅片表面分析,发现硅片表面呈蜂窝状,有大孔、小孔和微孔。硅片侧面边缘呈山峰山沟状,并伴随有裂纹,从外向里分为表面镶嵌层和缺陷应力层。通过对硅片表面损伤的形成机理研究,发现通过以下调整可以减小表面损伤和提高表面质量:一是减小切割时的晶体所受到的垂直压力;二是调整碳化硅的直径分布系数,圆度系数,堆积密度。     

提高晶圆扫描效率的方法研究

从测试晶圆上未划切的手机摄像头芯片引出一个问题:如何快速确定晶圆的有效测试范围,提出了"全片扫描"和"边缘扫描"两种方法,阐述实现原理后,分析各自的优缺点,利用实验数据进行效率对比,发现"边缘扫描"效率更高。