RG64—High Count Rate Low Noise Multichannel ASIC With Energy Window Selection and Continuous Readout Mode

We report on the performance of a low noise and high count rate readout ASIC with binary architecture and energy window selection for X-ray imaging applications using semiconductor detectors. The ASIC called RG64 is designed in 0.35 mum CMOS process and its total area is 3900times5000 mum². The core of RG64 consists of 64 readout channels. Each channel is built of a charge sensitive amplifier with a second order shaper of peaking time 75 ns, two independent discriminators with an 8-bit offset correction circuit and two independent 20-bit counters with RAM memory buffers. The ENC of the circuit reaches the value of about 126 el. rms with 1 pF input load and 5 mW power consumption per single channel. The mean gain in the multichannel ASIC is about 50 muV/el., with the dispersion from channel to channel of 0.9% (on one sigma level). The deviation of the effective threshold voltage spread for given energy can be reduced to less than 7 el. rms (calculated to the charge sensitive amplifier input). High count rate measurements have been performed up to 2 Mcps of average rate of input pulses, both for AC and DC coupled silicon strip detectors with X-ray photons of energy 8.04 keV. The RG64 can operate both in the continuous readout mode and in the readout mode separate from exposure.     

基于APV25多通道读出电子学系统设计

介绍了基于APV25芯片的多通道读出电子学系统的设计方法,利用ASIC芯片与可扩展读出系统相结合,实现多通道信号的处理。在该系统中,基于PXI机箱的单个读出板可实现2 048路信号的读出及处理,并具有集成度高、低功耗、可扩展等优点。电子学测试结果表明,本系统电荷输入线性动态范围为0~12 fC,APV25等效输入噪声408 e,可适应大型物理实验微结构气体探测器、硅像素探测器等探测器的读出需求。     

GERO: a general SCA-based readout ASIC for micro-pattern gas detectors with configurable storage depth and on-chip digitizer

The paper presents GEneral Read Out(GERO), a general readout ASIC based on a switched capacitor array for micro-pattern gas detectors. It aims at providing general readout electronics for low-to-medium event-rate gas detectors with high sampling frequency, configurable storage depth, and data digitalization. The first prototype GERO chip integrates 16 channels and was fabricated using a 0.18-lm CMOS process. Each channel consists of a sampling array working in a ping-pong mode, a storage array with a 1024-cell depth, and 32 Wilkinson analog-todigital converters. The detailed design and test results are presented in the paper.     

用于GEM探测器的电容积分式读出芯片的研究

介绍了GEM探测器阵列结构的一种读出方案,重点介绍了该读出方案中开关阵列芯片的设计.主要内容包括PAD前端读出电子学结构,开关电容阵列结构工作原理,开关阵列芯片设计,文章的最后给出了芯片测试结果.该10通道开关电容阵列芯片可以扩展为更多的通道,以满足更大规模的GEM探测器的阵列方式读出需要.     

基于峰值保持电路的GEM探测器前端读出ASIC设计

介绍了一种用于多层GEM探测器的低噪声前端读出ASIC芯片.针对GEM探测器输出信号特点,设计了电荷灵敏放大器、整形电路和峰值保持电路,并对其噪声、成形时间等设计指标参数进行了分析.     

XA readout chip characteristics and CdZnTe spectral measurements

The authors report on the performance of a CdZnTe (CZT) array readout by an XA (X-ray imaging chip produced at the AMS foundry) application specific readout chip (ASIC). The array was designed and fabricated at NASA/Goddard Space Flight Center (GSFC) as a prototype for the Burst Arc-Second Imaging and Spectroscopy gamma-ray instrument. The XA ASIC was obtained from Integrated Detector and Electronics (IDE), in Norway. Performance characteristics and spectral data for ²⁴¹Am are presented both at room temperature and at -20°C. The measured noise (σ) was 2.5 keV at 60 keV at room temperature. This paper represents a progress report on work with the XA ASIC and CZT detectors. Work is continuing and in particular, larger arrays are planned for future NASA missions     

基于FELIX的微结构气体探测器读出电子学系统设计

微结构气体探测器因其精度高、面积大等优点,在粒子物理实验中得到了非常广泛的应用。微结构气体探测器的未来应用将面临ASIC种类多、通道数多、数据量大等问题,给读出电子学系统的设计带来了很大的挑战,已成为微结构气体探测器进一步发展应用的瓶颈。FELIX系统具有数据带宽大、通道数多等特点,可很好解决这一问题。基于FELIX的电子学系统由完成探测器信号数字化的前端电子学模块、完成数据汇总的GBT模块、完成数据读出的FELIX系统、完成数据处理的数据处理终端组成,可完成10 240路半数字通道读出或4 096路模拟通道读出。该系统与Micromegas探测器一起实现宇宙线径迹探测,验证了该系统的通用性和兼容性,为微结构气体探测器的应用需求提供了一个通用的解决方案。     

A 64-Channel Wide Dynamic Range Charge Measurement ASIC for Strip and Pixel Ionization Detectors

In this paper we report a 64-channel application specified integrated circuit (ASIC) for the readout of parallel plate strip and pixel ionization detectors. The detectors measure the intensity and the geometrical characteristics of a hadron beam for hadrontherapy cancer treatments. The ASIC is based on a current to frequency converter followed by a counter. It uses a charge balancing integration technique to obtain a dynamic range in excess of$10^5$with a nonlinearity of less than 1%. The ASIC has been designed in a CMOS 0.8$mu m$technology and it has been used for the readout of both strip ionization detectors for beam calibration and pixel detectors for beam monitoring during treatment. A new version of the chip in CMOS 0.35$mu m$technology which allows bipolar input currents has been designed and is currently under test.     

基于3D Si PIN阵列热中子探测器的变增益宽动态前端读出电子学设计

基于Si CMOS技术的前端读出ASIC主要是根据3D Si PIN阵列热中子探测器的输出信号特性设计的。所设计的读出ASIC的主要电路模块包括电荷灵敏放大器（CSA）、模拟开关设计、具有三级电荷灵敏自动转换的自动增益控制模块（AGC）、相关双采样（CDS）和基准电流源电路。仿真结果表明,前端电路的输入动态范围为10 fC~80 pC。根据热中子探测器输出信号特性设计的ASIC的3个增益系数分别为19 V/pC、039 V/pC和94 mV/pC。所设计的ASIC的积分非线性小于 1%。单通道静态功耗约为 536 mW。零输入探测器电容时的等效噪声电荷为2416e-。计数率可达1 MHz 。     

A 16-Channel high-resolution time and charge measurement module for the external target experiment in the CSR of HIRFL

High precision time measurement is required in the readout of the neutron wall and TOF walls in the ex- ternal target experiment of the Cooling Storage Ring （CSR） project in the Heavy Ion Research Facility in Lanzhou （HIRFL）. Considering the time walk correction, both time and charge are measured in the readout electronics. In this 16-channel measurement module, time and charge information are digitized by TDCs at the same time based on the Time-Over-Threshold （TOT） method; meanwhile, by employing high-density ASIC chips, the electronics complexity is effectively reduced. Test results indicate that this module achieves a time resolution better than 25 ps and a charge resolution better than 5% over the input amplitude range from 50 mV to 3V.     

Test system of the front-end readout for an application-specific integrated circuit for the water Cherenkov detector array at the large high-altitude air shower observatory

The water Cherenkov detector array (WCDA) is an important part of the large high-altitude air shower observatory (LHAASO),which is in a research and development phase.The central scientific goal of LHAASO is to explore the origin of high-energy cosmic rays of the universe and to push forward the frontier of new physics.To simplify the WCDA's readout electronics,a prototype of a front-end readout for an application-specific integrated circuit (ASIC) is designed based on the timeover-threshold method to achieve charge-to-time conversion.High-precision time measurement and charge measurement are necessary over a full dynamic range [1-4000 photoelectrons (P.E.)].To evaluate the performance of this ASIC,a test system is designed that includes the front-end ASIC test module,digitization module,and test software.The first module needs to be customized for different ASIC versions,whereas the digitization module and test software are tested for general-purpose use.In the digitization module,a field programmable gate array-based time-todigital converter is designed with a bin size of 333 ps,which also integrates an inter-integrated circuit to configure the ASIC test module,and a universal serial bus interface is designed to transfer data to the remote computer.Test results indicate that the time resolution is better than 0.5 ns,and the charge resolution is better than 30％root mean square (RMS) at 1 P.E.and 3％ RMS at 4000 P.E.,which are beyond the application requirements.     

高计数率气体探测器读出电子学原型机研制

研制一套可用于高计数率气体探测器的读出电子学原型机系统,包括前端板、数据采集板和上位机。前端板采用一款先进的前端读出专用集成电路(ASIC)芯片实现对探测器信号的测量和模数转换;数据采集板利用现场可编程门阵列（FPGA）实现对数据的分析、处理和传输;上位机实现控制指令发送、PC端数据接收及存储等。在22~99 fC的输入范围内,原型机各通道积分非线性均好于024%;联合探测器使用55Fe放射源测试,结果好于相同条件下的商用电子学。可满足20 kHz计数率下GEM TPC探测器的读出需求。     

Application of CMOS charge-sensitive preamplifier in triple-GEM detector

1 Introduction With novel materials and advanced technique of printed circuit board (PCB) and micro-electronics be- ing used in MPGD, over the past two decades, great progress has been made in MPGD[1], and as a new type of MPGD, the GEM[2] detector was developed during the late 1990s. Standard GEM from CERN is a thin, two-side copper-coated Kapton foil, perforated with a high density of holes etched using a photolitho- graphic process. The diameter of these holes is about 70 μm (ext…     

双面硅条探测器读出系统设计

双面硅条探测器(DSSD)用于实现中国电磁监测试验卫星高能粒子探测器载荷的望远镜系统。为了实现DSSD读出电子学低功耗、高集成度的要求,设计了一种基于ASIC VA64TA2的电子学读出系统,使用²⁴¹Am 5.486 MeV α源对DSSD读出系统进行了测试。DSSD探测器结面分辨率为1%~2%,欧姆面分辨率为3%~4%,达到了探测器额定性能。     

Semiconductor drift detectors for X- and gamma-ray spectroscopy and imaging

The semiconductor drift detectors (SDDs) show basic advantages, in terms of spectroscopic resolution and detection rate, with respect to other semiconductor detectors. These advantages are strictly related to the very low values of the output capacitance of these devices. In this paper the working principles and the performance of the SDDs are presented and the most recent devices (“droplet type” SDDs and monolithic arrays of SDDs) are introduced. The requirements of front-end electronics for the readout of the SDDs signals are then discussed and the most recent implementations (pulsed-reset preamplifiers, multi-channel ASIC readout circuits) are introduced. Some relevant applications of SDDs in the field of X-ray spectroscopy for material analysis and for nuclear physics experiments, and in the field of gamma-ray imaging, are presented as a conclusion.     

A Data Acquisition System for Elementary Particle Physics

The data acquisition system experiment 605 at the Fermi National Accelerator Laboratory employs a set of data transfer protocols developed at Columbia University and implemented in the Nevis Laboratories Data Transport System. We describe the logical design of the Transport System, its physical realization, and its particular application during the Spring, 1982 data run of experiment 605. During that run it served as the interface between the data latches and a megabyte of fast memory, operating at a data transfer rate of 200 nsec/16-bit word. Up to two thousand events were read out during the one second beam spill, each event consisting of about 250 words. We include details of proposed improvements to the data acquisition system and append a brief comment of the need for inexpensive, versatile readout systems in experimental elementary particle physics.     

带增益的气体探测器读出ASIC的研制

设计了用于带增益的气体探测器比如GEM、RPC等读出的ASIC,实现对探测器信号的放大、成形和对后续实时采样ADC的驱动电路.电荷增益和成形时间可调,有利于探测器不同增益下性能的研究,也扩展了芯片的应用范围.由于成形电路引入的噪声变得显著,在低电荷增益下,ENC会随增益下降而增加.芯片采用Chartered 0.35μm2P4M CMOS工艺,论文介绍了芯片的详细设计和仿真结果.     

Development of readout electronics for bunch arrival-time monitor system at SXFEL

A bunch arrival-time monitor(BAM) system,based on electro-optical intensity modulation scheme, is under study at Shanghai Soft X-ray Free Electron Laser.The aim of the study is to achieve high-precision time measurement for minimizing bunch fluctuations. A readout electronics is developed to fulfill the requirements of the BAM system. The readout electronics is mainly composed of a signal conditioning circuit, field-programmable gate array(FPGA), mezzanine card(FMC150), and powerful FPGA carrier board. The signal conditioning circuit converts the laser pulses into electrical pulse signals using a photodiode. Thereafter, it performs splitting and low-noise amplification to achieve the best voltage sampling performance of the dual-channel analog-to-digital converter(ADC) in FMC150. The FMC150 ADC daughter card includes a 14-bit 250 Msps dual-channel high-speed ADC,a clock configuration, and a management module. The powerful FPGA carrier board is a commercial high-performance Xilinx Kintex-7 FPGA evaluation board. To achieve clock and data alignment for ADC data capture at a high sampling rate, we used ISERDES, IDELAY, and dedicated carry-in resources in the Kintex-7 FPGA. This paper presents a detailed development of the readout electronics in the BAM system and its performance.     

RX64DTH -a fully integrated 64-channel ASIC for a digital X-ray imaging system with energy window selection

We report on the multichannel IC (RX64DTH) designed for position sensitive X-ray measurements with silicon strip detectors and dedicated to medical imaging applications. This integrated circuit has a binary readout architecture with a double threshold allowing on selection energy window for measured signals. The design was realized in a 0.8 /spl mu/m CMOS process. The core of the RX64DTH IC consists of 64 readout channels. The single channel is built with four basic blocks: charge sensitive preamplifier, shaper, two independent discriminators, and two independent 20-bit counters. Each readout channel counts pulses which are above the low discriminator threshold and counts pulses independently above the high discriminator threshold. The energy resolution in such architecture is limited by the noise of a single channel and by channel to channel threshold spread. We present the noise and matching performance of a 384-channel module built with a silicon strip detector and six RX64DTH ICs. In the 384-channel module an equivalent noise charge of about 200 el. rms is achieved for the shaper peaking time of 0.8 /spl mu/s and strip capacitance of 3 pF. The deviation of discriminator thresholds for the whole system is only 87 el. rms. The obtained results show that the energy resolution and uniformity of analog parameters (noise, gain, offset) are sufficient for medical diagnostic applications such as dual energy mammography and angiography.     

Pulse Height Analyzer with Internal Storage for Space Use

A pulse height analyzer has been designed for space use which is able to handle input count rates in excess of 5 X 104 counts per second with low power consumption and very small size. It can operate in the temperature range of -15 to + 70°C and survive storage temperature from -55 to + 125°C. A parallel-serial, coincident current, wide-temperature-range, ferrite core memory of 256 channels, 16 bits per channel is provided. A digitizing rate of 0. 5 microsecond per channel plus an average 25.5 microsecond storage time is used. An internal, nonoverloading linear amplifier is provided to handle up to 100 millivolt negative pulses for full scale storage. Control logic is provided for external commands for power, accumulate, nondestructive readout, and destructive readout functions. All input-output logic levels are compatible with conventional integrated circuits. All components are run at a fraction of their ratings in order to obtain maximum reliability.