GaAs pHEMT工艺6～18GHz有源倍频器MMIC

基于GaAs pHEMT工艺,设计了一个6～18 GHz宽带有源倍频器MM IC,最终实现了较高的转换增益和谐波抑制特性。芯片内部集成了输入匹配、有源巴伦、对管倍频器和输出功率放大器等电路。外加3.5 V电源电压下的静态电流为80 mA;输入功率为6 dBm时,6～18 GHz输出带宽内的转换增益为6 dB;基波和三次谐波抑制30 dBc。当输出频率为12 GHz时,100 kHz频偏下的单边带相位噪声为-143 dBc/Hz。芯片面积为1 mm×1.5 mm。     

一种基于BiFET工艺的高输入阻抗运算放大器

针对CMOS运算放大器存在的输入失调电压高、噪声性能差等问题,提出了一种基于双极结型场效应晶体管(BiFET)工艺的高输入阻抗运算放大器。采用P沟道JFET差分对作为输入级,实现了pA量级的极低输入偏置电流/失调电流和nV/Hz量级的极低输入噪声电压谱密度。采用双极晶体管构成的共集-共射增益级和互补推挽输出级,实现了100 dB的开环增益、10 V/μs的输出电压转换速率和10 MHz的带宽。该运算放大器适用于对微弱模拟信号的采集和放大。     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

Rail-to-rail BiCMOS operational amplifier using input signal adapters with floating outputs

An operational amplifier with rail-to-rail input and output voltage range in 0.6 μm BiCMOS technology is presented. Two simple input signal adapters with floating outputs serving as pre-stages are introduced. They are followed by a differential amplifier. The adapters translate the input signals into a floating level within the operating region of the differential amplifier, enabling rail-to-rail operation. An inverter-based simple rail-to-rail class AB output stage has been used. With a single supply of 1.5 V, the proposed rail-to-rail operational amplifier achieves 72 dB DC open-loop gain, 2.54 MHz unity-gain frequency, 62° phase margin, 2.5 V/μs slew rate, and 147 μW power consumption.     

High-gain,high-bandwidth,rail-to-rail,constant-gm CMOS operational amplifier

This study presents a high-gain, high-bandwidth, constant-g_m , rail-to-rail operational amplifier (op-amp). The constant transconductance is improved with a source-to-bulk bias control of an input pair. A source degeneration scheme is also adapted to the output stage for receiving wide input range without degradation of the gain. Additionally, several compensation schemes are employed to enhance the stability. A test chip is fabricated in a 0.18?µm complementary metal-oxide semiconductor process. The active area of the op-amp is 181?×?173?µm² and it consumes a power of 2.41?mW at a supply voltage of 1.8?V. The op-amp achieves a dc gain of 94.3?dB and a bandwidth of 45?MHz when the output capacitive load is connected to an effective load of 42.5?pF. A class-AB output stage combining a slew rate (SR) boost circuit provides a sinking current of 6?mA and an SR of 17?V/µs.     

A CMOS Active Balun Using Bond Wire Inductors and a Gain Boosting Technique

An active balun with a single-ended input and a pair of differential outputs is presented for the input stages of differential circuits. The active balun, which is composed of an input resonator and cascaded common-gate amplifiers, was implemented using 0.18-mum CMOS technology and bond wire inductors. A body-source cross-coupled configuration was used to enhance the gain of the active balun. The gain is 9.3 dB at 1.8 GHz, and the phase and the amplitude error are less than 2deg and 1 dB, respectively, in the frequency range of 1 to 2 GHz, even for a P_1dB of -2.7 dBm. The balun consumes 9 mA for 3-V supply voltage.     

Transconductance enhancement in bulk-driven input stages and its applications

Two different circuit techniques to enhance the effective transconductance of a CMOS bulk-driven differential input stage are presented in this paper. Both approaches rely on a partial positive feedback, which leads to improved values for the DC gain and the gain-bandwidth product. The operation principle of the first solution is based on modifying the effective conductance of the active load of the input stage, while the second method acts directly on the input differential pair. The suitability of the presented techniques is demonstrated by the design of operational transconductance amplifiers operating at two different supply voltages, i.e., 2.4 and 1.0 V. Besides, the overall design of two applications, namely a 3 V input/output rail-to-rail operational amplifier with high linearity and a 1.2 V second-order OTA-C low-pass filter, is addressed. Simulated results obtained in standard 0.35 μm CMOS technology demonstrate the applicability of the solutions introduced.     

A FG-MOS Based Fully Differential Current Controlled Conveyor and Its Applications

This paper presents a new fully differential second generation current controlled conveyor (FDCCCII) based on differential pair topology, which employs floating gate MOS transistors (FG-MOS). It uses floating gate MOSFETs at the input stage and has rail-to-rail structure which performs with both positive and negative signals. This circuit has tunable parasitic resistance at its input port. It operates with low supply voltage (±0.8 V), low power consumption (lower than 3 mW at current bias of 1 mA), and wide range parasitic resistance (R _X ). This circuit has less MOSFET than the previous similar circuits and is suitable for integrated circuit design. To demonstrate the application of the proposed circuit, a fully differential current mode LC-ladder filter and a fully differential multifunction biquad filter are designed. Simulation results by HSPICE confirm validity of the proposed circuit and its application.     

一种低失调高压大电流集成运算放大器

基于结型场效应晶体管(JFET)和双极型晶体管(BJT)兼容工艺,设计了一种低失调高压大电流集成运算放大器。电路输入级采用p沟道JFET (p-JFET)差分对共源共栅结构;中间级以BJT作为放大管,采用复合有源负载结构;输出级采用复合npn达林顿管阵列,与常规推挽输出结构相比,在输出相同电流的情况下,节省了大量芯片面积。基于Cadence Spectre软件对该运算放大器电路进行了仿真分析和优化设计,在±35 V电源供电下,最小负载电阻为6Ω时的电压增益为95 dB,输入失调电压为0.224 5 mV,输入偏置电流为31.34 pA,输入失调电流为3.3 pA,单位增益带宽为9.6 MHz,具有输出9 A峰值大电流能力。     

Recursive Receiver Down-Converters With Multiband Feedback and Gain-Reuse

Receiver down-converter topologies are presented that provide simultaneous frequency conversion and baseband amplification within a mixer, in order to reduce power dissipation for a given dynamic range. The down-converted IF output of a mixer is reapplied to its input stage in a recursive manner, which significantly enhances the conversion gain, with current requirement determined primarily by the input transconductor of the mixer. Two down-converter topologies based on this technique are presented. One topology utilizes common-source NMOS devices as the RF input stage of the mixer, and reuses their transconductance for providing baseband gain. The second topology utilizes differential pairs as the RF input stage, and employs the transconductance of the tail current-source devices for baseband gain. The designs are implemented in a 0.13 mum CMOS technology and achieve peak conversion gains of 50 dB and 56 dB, with single side-band noise figures of 12.7 dB and 9.4 dB, and OIP3 values of 8 and 11 , respectively. They operate at a nominal supply of 1.2 V with bias current of 2.9 mA and 2.1 mA, respectively. The active die area is less than 0.1 mm for each design. Noise and linearity performance of the down-converters is analyzed, and the potential for enhancement of IIP3 through cancellation of nonlinear products is discussed.     

微电容超声换能器的前端专用集成电路设计

针对微电容超声换能器(CMUT)微弱电流信号检测的要求,设计了一种用于CMUT的前端专用集成电路——运算放大器(OPA)电路。运算放大器电路采用两级放大结构,第一级采用全差分折叠-共源共栅结构,输出级采用AB类控制的轨到轨输出级,在运算放大器电路反相输入端和输出端通过一个反馈电阻实现CMUT电流信号到电压信号的转换。采用GlobalFoundries 0.18μm的标准CMOS工艺进行了仿真设计和流片,芯片尺寸为226μm×75μm。仿真结果表明,运算放大器的开环增益为62 dB,单位增益带宽为30 MHz,在3 MHz处的输入参考噪声电压为2.9μV/Hz^1/2,电路采用±3.3 V供电,静态功耗为11 mW。测试结果表明仿真与实测结果相符,该运算放大器电路能够实现CMUT微弱电流信号检测功能。     

6-k/spl Omega/ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range

A high-gain, 43-Gb/s InP HBT transimpedance-limiting amplifier (TIALA) with 100-/spl mu/A/sub pp/ sensitivity and 6 mA/sub pp/ input overload current is presented. The circuit also operates as a limiting amplifier with 40-dB differential gain, better than 15-dB input return loss, and a record-breaking sensitivity of 8 mV/sub pp/ at 43 Gb/s. It features a differential TIA stage with inductive noise suppression in the feedback network and consumes less than 450mW from a single 3.3-V supply. The TIALA has 6-k/spl Omega/ (76dB/spl Omega/) differential transimpedance gain and 35-GHz bandwidth and comprises the transimpedance and limiting gain functions, an auto-zero dc feedback circuit, signal level monitor, and slicing level adjust functions. Other important features include 45-dB isolation and 800-mV/sub pp/ differential output.     

K波段反馈式MMIC中功率放大器

给出了一种基于功率PHEMT工艺技术设计加工的K波段反馈式MMIC宽带功率放大器。在21～29GHz的工作频段内,当漏极电压为6V、栅电压为-0.25V、电流为111mA时,1dB压缩点输出功率大于21dBm,小信号增益在13±1.5dB,输入驻波比小于3,输出驻波比均小于1.7。芯片尺寸:1mm×2.5mm×0.1mm。同时给出了一种芯片级电磁场仿真验证方法,用该方法仿真的结果和测试结果非常一致,保证了电路设计的准确性。     

Large bandwidth BiCMOS operational amplifiers for SC videoapplications

A single-ended and a fully differential broadband BiCMOS operational amplifier for switched-capacitor video applications are presented. The amplifiers feature a folded cascode gain stage with a current source as output load. For the single-ended amplifier the current mirroring is accomplished with a modified bipolar Wilson current mirror at the output of the differential pair. Symbolic expressions for the transfer functions for both amplifiers are derived. The amplifiers are integrated in an analog 1 μm BiCMOS process with an active die area of 0.72 mm² and 0.96 mm² for the single-ended and the fully differential amplifier, respectively. For both amplifiers a DC-gain of 68 dB and a unity gain frequency greater than 250 MHz was measured for a power supply voltage of 5 V     

一种高速信号的可编程有源连续时间均衡器的设计

介绍了一种基于0.18μm标准CMOS工艺实现的,用于均衡1.25 Gb/s高速信号的可编程有源连续时间均衡器。通过外部可编程逻辑器件输出的控制信号,控制该均衡器的输入信号Ctrl,从而改变其高频增益提升系数,最大可以实现长达40英寸(1 000 mm)的FR-4背板传输线衰减后的接收信号的均衡。该均衡器的电路主要由R-C电阻电容衰减差分放大器和MCML输出缓冲级组成,其中R-C放大器完成输入信号的高频增益提升,MCML缓冲级完成输出信号的整形并提供一定的增益。该均衡器的工作电压为1.8 V,在输入信号速率为1.25 Gb/s时,总的工作电流为1.6 mA。     

紧凑型K波段单级反馈式MMIC中功率放大器

给出了一种基于功率PHEMT工艺技术设计加工完成的紧凑型K波段单级反馈式MMIC宽带功率放大器.在21～28GHz的工作频段内,当漏极电压为6V,栅电压为-0.25V,电流为82mA时,1dB压缩点输出功率大于21dBm,小信号增益为7dB左右,输入驻波比小于3,输出驻波比均小于2.芯片尺寸为1mm×1.2mm×0.1mm.同时,给出了一种芯片级电磁场仿真验证方法,用该方法仿真的结果和测试结果非常一致,保证了电路设计的准确性.     

A monolithic transformer coupled 5-W silicon power amplifier with59% PAE at 0.9 GHz

This paper presents the circuit design and application of a monolithically integrated silicon radio-frequency power amplifier for 0.8-1 GHz. The chip is fabricated in a 25-GHz-f_T silicon bipolar production technology (Siemens B6HF). A maximum output power of 5 W and maximum efficiency of 59% is achieved. The chip is operating from 2.5 to 4.5 V. The linear gain is 36 dB. The balanced two-stage circuit design is based fundamentally on three on-chip transformers. The driver stage and the output stage are connected in common-emitter configuration. The input signal can be applied balanced or single-ended if one input terminal is grounded. One transformer at the input acts as balun as well as input matching network. Two transformers acts as interstage matching network     

一种恒跨导轨对轨CMOS运算放大器的设计

设计了一种新颖的恒跨导轨对轨CMOS运算放大器结构。输入级采用轨对轨的结构,在输入级采用4个虚拟差分对管来对输入差分对的电流进行限制,使运放的输入级跨导在工作范围内保持恒定。输出级采用前馈式AB类输出结构,以使输出达到全摆幅。仿真结果显示,在5 V电源电压和带有10 pF电容与10 kΩ电阻并联的负载下,该运放在共模输入范围内实现了恒跨导,在整个共模输入范围内跨导变化率仅为3%,输出摆幅也达到了轨对轨全摆幅,运放的开环增益为108.5 dB,增益带宽积为26.7 MHz,相位裕度为76.3°。     

Seventh-order elliptic video filter with 0.1 dB pass band ripple employing CMOS CDTAs

In this paper, a CMOS realization of the current differencing transconductance amplifier (CDTA) is given, which is a newly reported active building block for current-mode signal processing. Current differencing stage of the CDTA element is realized using a differential current-controlled current source and in the output stage, floating current sources are used to convert intermediate voltage of z terminal to output currents. Due to the compactness of the circuit, it is capable of high-frequency operation and suitable for video signal-processing applications. The CDTA element is used in a current-mode anti-aliasing video filter, which is designed using operational simulation of a seventh-order passive elliptic filter, so the resulting active filter has the low sensitivity feature of its passive counterpart. The filter has 0.1 dB maximum pass band ripple as imposed by ITU video anti-aliasing filter standard. SPICE-simulation results of both the CDTA element and the seventh-order elliptic filter are given. Simulation results are found in close agreement with theoretical results.     

宽范围 CMOS差分式双端输入-输出电流传输器

基于宽线性跨导及共模检测电路,设计了一种改进型差分式双端输入-输出电流控制电流传输器电路(DIDOCC)。该全差分式电路具有电流控制功能,并能抑制偶次谐波和共模干扰。仿真结果表明,在-1.5～+1.5V供电电压下,总静态电流约为300μA,X1、X2端差分电压输入动态范围为-0.9～0.9V。基于DIDOCC电路,设计了一种全差分二阶滤波器,仿真结果与理论值较为吻合。文中所有电路均基于0.25μmCMOS工艺。