Ni纳米晶制备及其在MOS电容中存储特性研究

优化了Ni纳米晶的制备工艺参数,得到了分布均匀,形状为球形,平均尺寸5nm,密度2×1012/cm2的Ni纳米晶。在此基础上,制备了包含Ni纳米晶的MOS电容结构。利用高频电容-电压(C-V)和电导-电压(G-V)测试研究了其电学性能,证明该MOS电容结构的存储效应主要源于金属纳米晶的限制态。电容-时间(C-t)测试曲线呈指数衰减趋势,保留时间600s,具有较好的保留性能。     

纳米晶存储特性的研究

常温下硅纳米晶构成的MOSFET存储器具有低压、低功耗、体积小、高剂量和快速读写等优良特性,在ULSI中有重要的应用前景.它是当前ULSI研究中的一项热门专题,在国外一些著名刊物上屡见报道.本文介绍了这种器件的存储特性及其机理与最新研究进展.     

纳米晶非挥发性存储器研究进展

介绍了纳米晶非挥发性存储器的发展状况和基本工作原理,比较了纳米晶非挥发性存储器所涉及到的各种不同的电荷输运机制,系统介绍了纳米晶非挥发性存储器在纳米晶材料设计、纳米晶晶体生长控制方法、隧穿/控制介质层工程和新型存储器器件结构等方面的一些最新研究进展,对纳米晶非挥发性存储器的研究趋势进行了展望。     

基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

基于硅纳米晶的非挥发存储器制备与存储特性

硅纳米晶非挥发存储器由于其卓越的性能以及与传统工艺的高度兼容性,近来引起高度关注。采用两步低压化学气相淀积(LPCVD)生长方式制备硅纳米晶(Si-NC),该方法所制备的硅纳米晶具有密度高、可控性好的特点,且完全兼容于传统CMOS工艺。在此基础上制作四端硅纳米晶非挥发存储器,该器件展示出良好的存储特性,包括10 V操作电压下快速地擦写,数据保持特性的显著提高,以及在105次擦写周期以后阈值电压(Vt)飘移低于10%的良好耐受性。该器件在未来高性能非挥发存储器应用上极具潜质。     

N型6H-SiC MOS电容的电学特性

在可商业获得的N型6H-SiC晶片上,通过化学气相淀积,进行同质外延生长,在此结构材料上,制备MOS电容.详细测量并分析了6H-SiCMOS电容的电学特性,其有效电荷密度为4.3×1010cm-2;SiC与SiO2之间的势垒高度估算为2.67eV;SiC热生长SiO2的本征击穿场强(用累计失效率50%时的场强来计算)为12.4MV/cm,已达到了制作器件的要求.     

金属纳米晶快闪存储器研究进展

金属纳米晶具有态密度高、费米能级选择范围广以及无多维载流子限制效应等优越性,预示着金属纳米晶快闪存储器在下一代闪存器件中具有很好的应用前景。从金属纳米晶存储器的工作原理、纳米晶的制备方法、以及新型介质材料和电荷俘获层结构等方面,对金属纳米晶存储器近年来的研究进展进行了总结。     

半导体纳米粒子的电容

用简谐势描述量子点中电子所受的约束 ,通过简谐势模型利用自洽迭代的方法计算了Cd S、Pb S等半导体纳米粒子的充电电容 ,从而找到了其在室温下形成单电子器件的最大粒径 .     

Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO_2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time.     

使用化学方法常温合成金纳米晶并通过旋涂工艺将其组装的存储特性可调型非易失性存储器

3C行业的不断发展,催生了对高密度、持久保存、快速擦写、鲁棒可靠性的非易失性存储器(如flash)的持续需求,促使我们在科研上不断地深入研究新材料、新工艺。在本文中,我们首次采用了区别于传统CMOS工艺的两步工艺方法来制作金属纳米晶非易失性存储器。这种方法,由于将金纳米晶的化学合成和后续组装分离开来,所以能够独立地调节纳米晶的尺寸和组装密度,而且可以很好地避免一直困扰的金属扩散问题。最终的形貌表征和电学测量结果,证实存在一个最优化的纳米晶密度--在这个最优化条件下,我们的存储器件,既有持久的保存时间,又有较大的存储窗口。而组装密度的可调,同时可以满足我们对于大的存储窗口/较长保存时间某一方面的偏好。这些实验结果,都很好地证明了我们两步工艺方法的可行性。     

Density-controllable nonvolatile memory devices having metal nanocrystals through chemical synthesis and assembled by spin-coating technique

A novel two-step method is employed,for the first time,to fabricate nonvolatile memory devices that have metal nanocrystals.First,size-averaged Au nanocrystals are synthesized chemically;second,they are assembled into memory devices by a spin-coating technique at room temperature.This attractive approach makes it possible to tailor the diameter and control the density of nanocrystals individually.In addition,processes at room temperature prevent Au diffusion,which is a main concern for the application of...     

Capacitance-voltage characterization of fully silicided gated MOS capacitor

This paper investigates the capacitance-voltage (C-V) measurement on fully silicided (FUSI) gated metal-oxide-semiconductor (MOS) capacitors and the applicability of MOS capacitor models. When the oxide leak-age current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic, A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the three-element and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor's area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation fac-tor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this pa-per investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to evaluate whether the full silicidation has completed or not, and to extract the interface trap density of the SiO2/Si interface.     

Capacitance-voltage characterization of fully silicided gated MOS capacitor

This paper investigates the capacitance-voltage （C-V） measurement on fully silicided （FUSI） gated metal-oxide-semiconductor （MOS） capacitors and the applicability of MOS capacitor models. When the oxide leakage current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic. A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the threeelement and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor＇s area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation factor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this paper investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to evaluate whether the full silicidation ha     

面向非挥发存储器应用的叠层Ru纳米晶材料的制备与特性

Two methods are proposed to fabricate stacked ruthenium （Ru） nanocrystals （NCs）： rapid thermal annealing （RTA） for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density of Ru NCs are 2-4 nm and 3 × 10^12 cm^-2 for the former method, compared to 3-7 nm and 2 ×10^12 cm^-2 for the latter. Because of the higher surface trap density and more uniform electron tunneling path between upper and lower Ru NCs, a 5.2 V memory window and 1 V after a period of 10 years are observed in metal oxide semiconductor （MOS） capacitors fabricated by the former method, which are much better than 4.6 V and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.     

Formation of stacked ruthenium nanocrystals embedded in SiO2 for nonvolatile memory applications

n metal oxide semiconductor (MOS)capacitors fabricated by the former method, which are much better than 4.6 Ⅴ and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.     

Dielectric characteristics of gamma irradiated Au/SnO2/n-Si/Au (MOS) capacitor

The dielectric characteristics of gamma irradiated Au/SnO₂/n-Si/Au (MOS) capacitor were studied. The MOS capacitor was irradiated by a ⁶⁰Co gamma radiation source with a dose rate of 0.69 kGy/h. The dielectric parameters such as dielectric constant (ε′), dielectric loss (ε″), loss factor (tan δ) and ac electrical conductivity (σ_ac) were calculated from the capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. It is found that the C and G/ω values decrease with the increasing total dose due to the irradiation-induced defects at the interface. Also, the calculated values of ε′, ε″ and σ_ac are found to decrease with an increased radiation dose. This result indicates that the dielectric characteristics of the MOS capacitor are sensitive to gamma-ray dose.