A decentralized and fault tolerant convergence detection algorithm for asynchronous iterative algorithms

This article presents an algorithm that performs a decentralized detection of the global convergence of parallel asynchronous iterative applications. This algorithm is fault tolerant. It runs a decentralized saving procedure which enables this algorithm, after a node’s crash, to replace the dead node by a new one which will continue the computing task from the last check point. Combined with the advantages of the asynchronous iteration model, this method allows us to compute very large scale problems using highly volatile parallel architectures like Peer-to-Peer and distributed clusters architectures. We also present the implementation of this algorithm in the JaceP2P platform which is dedicated to designing and executing parallel asynchronous iterative applications in volatile environments. Numerous experiments show the robustness and the efficiency of our algorithm.     

A multi-agent architecture with cooperative fuzzy control for a mobile robot

The challenges of robotics have led the researchers to develop control architectures composed of distributed, independent and asynchronous behaviors. One way to approach decentralization is through cooperative control, since it allows the development of complex behavior based on several controllers combined to achieve the desired result. Robots, however, require high-level cognitive capacities, and multi-agent architectures provide the appropriate level of abstraction to define them. This article describes a multi-agent architecture combined with cooperative control developed within the agent. The experiments were carried out on an ActivMedia Pioneer 2DX mobile robot.     

Model-driven development of asynchronous message-driven architectures with AsyncAPI

In the Internet-of-Things (IoT) vision, everyday objects evolve into cyber-physical systems. The massive use and deployment of these systems has given place to the Industry 4.0 or Industrial IoT (IIoT). Due to its scalability requirements, IIoT architectures are typically distributed and asynchronous. In this scenario, one of the most widely used paradigms is publish/subscribe, where messages are sent and received based on a set of categories or topics. However, these architectures face interoperability challenges. Consistency in message categories and structure is the key to avoid potential losses of information. Ensuring this consistency requires complex data processing logic both on the publisher and the subscriber sides. In this paper, we present our proposal relying on AsyncAPI to automate the design and implementation of these asynchronous architectures using model-driven techniques for the generation of (part of) message-driven infrastructures. Our proposal offers two different ways of designing the architectures: either graphically, by modeling and annotating the messages that are sent among the different IoT devices, or textually, by implementing an editor compliant with the AsyncAPI specification. We have evaluated our proposal by conducting a set of experiments with 25 subjects with different expertise and background. The experiments show that one-third of the subjects were able to design and implement a working architecture in less than an hour without previous knowledge of our proposal, and an additional one-third estimated that they would only need less than two hours in total.

     

Implementation of a self-timed segmented bus

We propose an asynchronous structure for implementation on a SoC. An intersegment topological arrangement preserves parallelization and, through a so-called central arbiter, efficiently organizes communication with high signaling speed in the proposed structure. Researchers proposed the concept of segmenting buses primarily for multicomputer architectures. More recent approaches address on-chip implementation of segmented buses. We present an asynchronous segmented-bus architecture targeted for the modular design of high-performance SoC applications. The structure not only enables faster operation than a conventional bus system but also offers lower power consumption per transferred data item. This is possible because segmentation is realized in such a way that the majority of data transfers in the system are intrasegment transactions on relatively short wires with low or moderate capacitive loads.     

A block-asynchronous relaxation method for graphics processing units

In this paper, we analyze the potential of asynchronous relaxation methods on Graphics Processing Units (GPUs). We develop asynchronous iteration algorithms in CUDA and compare them with parallel implementations of synchronous relaxation methods on CPU- or GPU-based systems. For a set of test matrices from UFMC we investigate convergence behavior, performance and tolerance to hardware failure. We observe that even for our most basic asynchronous relaxation scheme, the method can efficiently leverage the GPUs computing power and is, despite its lower convergence rate compared to the Gauss–Seidel relaxation, still able to provide solution approximations of certain accuracy in considerably shorter time than Gauss–Seidel running on CPUs- or GPU-based Jacobi. Hence, it overcompensates for the slower convergence by exploiting the scalability and the good fit of the asynchronous schemes for the highly parallel GPU architectures. Further, enhancing the most basic asynchronous approach with hybrid schemes–using multiple iterations within the “subdomain” handled by a GPU thread block–we manage to not only recover the loss of global convergence but often accelerate convergence of up to two times, while keeping the execution time of a global iteration practically the same. The combination with the advantageous properties of asynchronous iteration methods with respect to hardware failure identifies the high potential of the asynchronous methods for Exascale computing.     

Shared-per-wavelength asynchronous optical packet switching: A comparative analysis

This paper compares four different architectures for sharing wavelength converters in asynchronous optical packet switches with variable-length packets. The first two architectures are the well-known shared-per-node (SPN) and shared-per-link (SPL) architectures, while the other two are the shared-per-input-wavelength (SPIW) architecture, recently proposed as an optical switch architecture in synchronous context only, which is extended here to the asynchronous scenario, and an original scheme called shared-per-output-wavelength (SPOW) architecture that we propose in the current article. We introduce novel analytical models to evaluate packet loss probabilities for SPIW and SPOW architectures in asynchronous context based on Markov chains and fixed-point iterations for the particular scenario of Poisson input traffic and exponentially distributed packet lengths. The models also account for unbalanced traffic whose impact is thoroughly studied. These models are validated by comparison with simulations which demonstrate that they are remarkably accurate. In terms of performance, the SPOW scheme provides blocking performance very close to the SPN scheme while maintaining almost the same complexity of the space switch, and employing less expensive wavelength converters. On the other hand, the SPIW scheme allows less complexity in terms of number of optical gates required, while it substantially outperforms the widely accepted SPL scheme. The authors therefore believe that the SPIW and SPOW schemes are promising alternatives to the conventional SPN and SPL schemes for the implementation of next-generation optical packet switching systems.     

VOVO: VCR-Oriented Video-on-Demand in Large-Scale Peer-to-Peer Networks

Most P2P Video-On-Demand (VOD) schemes mainly focus more on mending service architectures and optimizing overlays but do not carefully consider the user behavior and the benefit of prefetching strategies. As a result, they cannot better support VCR-oriented services in terms of substantive asynchronous clients, and free VCR controls for P2P VODs. In this paper, we propose VOVO, VCR-oriented VOD for large-scale P2P networks. By mining associations inside a video, the segments requested in VCR interactivities are accurately predicted based on the information collected through gossips. Together with a hybrid caching strategy, a collaborative prefetching scheme is proposed to optimize resource distribution among neighboring peers. We evaluate VOVO through extensive experiments. Results show that VOVO is scalable and effective, providing short startup latencies and good performance in VCR interactivities.     

网络瞄准环境下异步航迹融合策略及融合算法研究

多个网络节点的异步航迹融合是实现网络瞄准作战方式的关键技术之一．本文有效利用各网络节点的异步航迹信息, 提高瞄准的精度. 首先分析了网络瞄准环境下异步航迹融合的主要方式, 在此基础上结合工程实际, 提出了3种可适用于网络瞄准的异步航迹融合策略; 然后根据最优估计理论, 分别给出了不同策略下的异步融合算法与实现步骤; 最后通过仿真验证了所提出方法在解决异步航迹融合问题上的有效性, 并分析了不同航迹融合周期 对系统融合性能的影响.     

Challenges and Lessons in Developing Middleware on Smart Phones

Several research projects pursuing middleware architectures to support pervasive applications on smart phones reveal the importance of careful resource management, lightweight communication protocols, and asynchronous programming.     

UC: A Set-Based Language for Data-Parallel Programming

UC is a data-parallel extension of C designed for scientific computations on synchronous and asynchronous parallel architectures. The primary constructs of the language include sets, reductions, and parallel and asynchronous composition. Its communication model is that of a globally addressable memory, with no syntactic distinction between local and remote data references, Unlike most existing data-parallel languages, UC programs may be synchronized at multiple levels of granularity, from a strict expression-level synchronization to a coarser statement or function-level synchronization. This paper describes the language and its implementation on the Connection Machine CM-2. Experimental measurements that compare the performance of the UC compiler with that of programs written in commercial parallel languages such as CM Fortran, C*, and *Lisp are also presented.     

Tolerance evaluation of flexible manufacturing architectures

Within the framework of FMS dependability, this article aims to apply the concept of tolerance to flexible manufacturing architectures. This enables flexible architectures to be studied and the one that could best react if failure occurs to be chosen. The methods proposed here are based on a process representation. They could be used on a designed architecture in a feedback process: The analysis is performed off line in order to check whether the workshop is tolerant or the addition of some flexibilities can make the system more tolerant.     

多传感器噪声方差未知情况下的异步航迹融合

针对分布式多传感器数据融合系统,提出了一种多传感器异步航迹融合算法。现有的多传感器信息融合算法大都基于Kalman滤波器,要求噪声方差已知,并且假定各传感器同步采样,不考虑通信延迟。本文在分布式处理的模式下,基于各传感器在扩展记忆因子递推最小平方(EFRLS)估计形成本地航迹的基础上,提出了一种融合误差均方差矩阵的迹最小意义下的异步目标航迹融合算法。仿真实验结果表明,这种融合算法是有效的,算法接近集中式融合算法的精度。     

Formal modelling and verification of GALS systems using GRL and CADP

A GALS (Globally Asynchronous, Locally Synchronous) system consists of several synchronous components that evolve concurrently and interact with each other asynchronously. The design of GALS systems is tedious and error-prone due to the high degree of synchronous and asynchronous concurrency present in complex architectures. In this paper, we present GRL (GALS Representation Language), a formal language designed to model GALS systems, for the purpose of formal verification of the asynchronous aspects. GRL combines the synchronous reactive model underlying dataflow languages and the asynchronous concurrent model underlying process algebras. We propose a translation from GRL to LNT, a value-passing concurrent language with classical process algebra flavour. This makes possible the analysis of GRL specifications using all the state-of-the-art simulation and verification functionalities provided by the CADP toolbox.     

Is Asynchronous Logic More Robust Than Synchronous Logic?

With clock rates beyond 1 GHz, the model of a systemwide synchronous clock is becoming difficult to maintain; therefore, asynchronous design styles are increasingly receiving attention. While the traditional synchronous design style is well-proven and backed up by a rich field experience, comparatively little is known about the properties of asynchronous circuits in practical application. In the face of increased transient fault rates, robustness is a crucial property, and from a conceptual view, the so-called “delay-insensitive” asynchronous design approaches promise to be more robust than synchronous ones, since their operation does not depend on tight timing margins, and data are two-rail coded. A practical assessment of asynchronous designs in fault-injection (FI) studies, however, can rarely be found, and there is a lack of adequate methods and tools in this particular domain. Therefore, the objective of this work is 1) to provide a common approach for efficient and accurate FI in synchronous and in asynchronous designs, and 2) to experimentally compare the robustness of both synchronous and asynchronous designs. To this end, a synchronous 16-bit processor as well as its asynchronous (delay insensitive) equivalent are subjected to signal flips and delay faults. The results of over 489 million experiments are summarized and discussed, and a detailed discussion on the specific properties of the chosen asynchronous design style is given.     

Action-Level Real-Time Network-on-Chip Modeling

To simulate time-constrained operations and scheduling for Network-on-Chip (NoC) systems, we introduce a new set of component specifications at flit level grounded in Action-Level Real-Time DEVS formalism. These models capture the dynamics of NoC systems through action-based behavior under strict execution time intervals. These DEVS-based models are well-suited for development and simulation of asynchronous NoC architectures. This is achieved by extending the DEVS-Suite simulator to support real-time executions of ALRT-DEVS models. Representative simulation models capturing structure and behavior of prototypical Mesh NoC systems are developed. A set of experiments are designed, implemented, executed, and analyzed to show the kind of real-time simulation capabilities that can be achieved for Network-on-Chip systems.     

挖掘多数据流的异步偶合模式的抗噪声算法

挖掘多数据流的异步偶合模式是具有挑战性的工作.主要的研究工作包括:(1) 研究Haar小波滤波技术在挖掘流数据的异步偶合模式中的应用;(2) 引入小波系数序列来度量数据流的异步局域偶合度;证明了一系列定理,保证了度量方法的正确性;(3) 设计了环形滑动窗口和挖掘异步偶合模式的抗噪声增量算法,其时间复杂性小于O(n2);(4) 使用真实数据进行模拟实验,验证了算法的有效性.     

Optimized implementation of synchronous models on industrial LTTA systems

Synchronous models are used to specify embedded systems functions in a clear and unambiguous way and allow verification of properties using formal methods. The implementation of a synchronous specification on a distributed architecture must preserve the model semantics to retain the verification results. Globally synchronized time-triggered architectures offer the simplest implementation path, but can be inefficient or simply unavailable. In past work, we defined a mapping of synchronous models on a general class of distributed asynchronous architectures, for which the only requirement is a lower bound on the rate of activation of tasks. In this paper, we set tighter requirements on task execution rates, and we include a realistic modeling of communication delays, task scheduling delays and schedulability conditions, discussing the timing characteristics of an implementation on a system with a Controller Area Network (CAN). Next, the semantics preservation conditions are formulated as constraints in an architecture optimization problem that defines a feasible task model with respect to timing constraints. An automotive case study shows the applicability of the approach and provides insight on the software design elements that are critical for a feasible implementation.     

Three generations of asynchronous microprocessors

We trace the evolution of Caltech asynchronous processors from a simple proof of concept, to a high-performance MIPS-like processor using a different buffer circuit for better performance, to the latest 8051 clone targeting low-energy operation. We describe the control aspects of the evolving circuit styles. We describe these three generations of asynchronous microprocessors (Caltech asynchronous processors, MiniMIPS and Lutonium) and the corresponding circuit families and design methods. The asynchronous circuits we use are called quasidelay-insensitive (QDI) circuits. A QDI circuit involves no assumption about, or knowledge of, delays in operators and wires, except for isochronic forks, which the designer assumes have similar delays on the different branches. QDI circuits are the most conservative asynchronous circuits in terms of delays.