H.264/AVC中基于全零块检测的运动估计快速算法

全零块检测是面向低比特率的视频编码器常用优化方法之一.特别是与运动估计相结合,可以有效的减少编码器的计算复杂性.本文根据H.264/AVC中整数变换的特点,给出了相应的全零块检测门限,提出了一种基于全零块检测的运动搜索提前中止准则.针对H.264/AVC多编码模式的特点,进一步将全零块检测用于H.264/AVC中多种编码模式的选择,有效的提高了运动估计的效率.利用这种方法,在有效减少编码器的计算复杂性,提高H.264/AVC软件编码器编码效率的同时,可以保持比特率和图像质量基本不变.     

高清视频编解码芯片选型及压存系统的设计

介绍了H.264视频编解码芯片MB86H50,Hi3510和一款市场认知度较高的芯片PNX1500,在性能、结构等方面进行对比.以专用视频压缩芯片MB86H50为核心,以PNX1500 DSP为主控制器,设计出集多路高清数字视频压缩编码、存储于一体的专用图像系统,对于高清视频走向监控、信息存储等实际应用具有极大的研究价值.     

H.264中一种基于矩阵分解的变换算法及硬件实现

H.264是新一代的视频编码标准，具有优秀的压缩性能。其获得优越性能的代价是运算复杂度的大幅增加，因此在实际应用上存在困难。使用专门的硬件设备是解决这个问题的方法之一。H．264标准中的整数变换运算适合使用硬件实现。首先对H，264标准中的整数变换运算进行介绍，针对H．264中的变换运算提出一种基于矩阵分解的快速并行算法。分析了该算法的结构，表明是符合H.264标准的一种快速算法。并对变换算法的硬件寡现进行了分析，表明这种硬件算法结构适合在实时编解码中应用。     

基于PNX1700的嵌入式多媒体平台

文章介绍基于Philips NEXPERIA PNX1700 DSP的嵌入式音视频编解码多媒体平台,该平台支持音频,视频的实时采集压缩解压处理,支持H.323网络传输协议,音频编码采用G.711协议,视频编码采用H.264协议.文章主要介绍平台的硬件设计方案.     

适用于H.264的快速模式选择算法

多模式运动估计使H.264比其他视频编码算法具有更高的编码效率,但同时也使计算复杂度明显提升。提出了一种新的适用于H.264的快速模式选择算法。此算法提前对块的细节程度和纹理方向进行分析,根据块细节程度缩小模式选择的范围,并根据块纹理方向对模式进行进一步筛选,从而大大提高了模式搜索速度,将性能损失控制在可以忽略的范围内。仿真及实验的结果证明了本算法的有效性。     

一种H.264视频编码码率控制方法

根据视频编码线性率失真函数和对H．264整数变换量化方法分析，提出一种适合于H．264编码算法的码率控制算法。先验证线性率失真函数对H．264编码算法的适用性，再通过将H．264整数变换的量化分解为系数校正和统一量化两个步骤实现了线性率失真函数在H．264码率控制中的应用。实验证明，与JVT—G012码率控制算法相比，码率控制的准确性和信噪比均有所提高。     

DSP上视频编码器的计算效率优化技术研究

文章以Philips的PNX1500平台优化移植H.264为例,阐述了DSP平台上优化移植视频编码算法的通用设计原则和若干有效设计方法.通过结合目标处理器特定体系结构的算法优化,并行指令优化和存贮结构优化来提高视频编码器的运算效率.实验结果表明,笔者优化得到的H.264视频编码器可以按照不低于18FPS的速度近似实时地编码D1格式的视频.该技术目前已应用于实际视频通信产品中.     

H.264变换编码及量化策略分析

H.264采用4×4的整数变换替代通用的8×8DCT变换.并将其融合在量化过程中,有效降低了变换算法的复杂度和运算量.避免了逆变换的失配问题.对H.264变换编码及量化策略进行了详细的分析,给出了其具体的实现过程.     

基于视频序列特性的运动估计算法比较与改进

对比分析了主流H.264运动估计算法,并针对UMHexagonS算法提出了更为有效的改进意见.实验表明,在编码后的失真度损失较小的情况下,该算法比UMHexagonS算法减少了搜索运算量.     

一种基于H.264/AVC的高效块匹配搜索算法

本文针对H.264/AVC的编码特点,提出了一种利用时空域运动相关性的快速块匹配搜索算法.该算法充分利用了视频序列的运动程度与宏块编码模式间的关联特性以及运动矢量的统计特征,明显减少了运动估计的搜索复杂度.实验表明,本文方法的搜索速度分别比FS和DS算法平均提高了77.96%和32.19%;重建图像的PSNR比DS算法平均提高了0.06dB,更接近FS算法的编码质量.     

基于H.264的嵌入式视频解码研究

针对H.264格式视频编解码器在嵌入式平台上的应用需求,对H.264格式视频编解码器的优缺点进行了理论性介绍,在对H.264视频编解码器研究的基础上,实现了基于嵌入式S3C6410平台的H.264解码器和播放器的移植。对基于Linux的开源编解码库ffmpeg在嵌入式S3C6410平台上进行了移植,实现了嵌入式平台上对H.264码流的解码和播放。对视频流图像分别在PC机和目标板上的解码效果进行了详细比较,论证了研究的正确性,证明了此研究具有工程应用价值。     

G·729在PNX1500 DSP平台上的优化设计

文章简单介绍了PNX1500 DSP[1]的体系架构,阐述了基于此架构的语音压缩算法G.729[2]的优化方法。在分析了影响G.729音频编码效率的关键因素基础上,选择了有针对性的优化策略对G.729音频编解码器的Cache部分进行指令优化和算法优化,有效地克服了影响编码速度的瓶颈,改善了编码器效率。     

Fast Interframe mode decision algorithm based on mode mapping and MB activity for MPEG-2 to H.264/AVC transcoding

Recently the latest video coding standard H.264/AVC is widely used for the mobile and low bitrate video codec in the various multimedia terminals. On the other hand, the MPEG-2 MP@HL codec has become the center of digital video contents since it is the standard codec for the Digital TV (DTV). To provide the bridge between the contents in MPEG-2 and mobile terminals, the transcoding of MPEG-2 contents into H.264/AVC format is an inevitable technology in the digital video market. The main bottleneck in the process lies in the computational complexity. In H.264/AVC, the variable block size (VBS) mode decision (MD) is used in the Interframe for the improved performance in the motion compensated prediction. For the macroblock (MB) which cannot be accurately predicted with one motion vector (MV), it is partitioned into smaller blocks and predicted with different MVs. In addition, SKIP and Intra modes are also permitted in the Interframe MD of H.264/AVC to further ameliorate the encoding performance. With the VBS MD technology, the Inter prediction accuracy can be improved significantly. However, the incidental side-effect is the high computational complexity. In this paper, we propose a fast Interframe MD algorithm for MPEG-2 to H.264/AVC transcoding. The relationships between SKIP and Intra modes are detected at first to map these two kinds of modes directly from MPEG-2 to H.264/AVC. And then the MB activity will be scaled by the residual DCT energy obtained from the MPEG-2 decoding process to estimate the block sizes of the MB mode for H.264/AVC Interframe MD. In our proposed method, the original redundant candidate modes can be eliminated effectively, resulting in the reduction of the computational complexity. It can reduce about 85% Rate-to-Distortion Cost (RDCost) computing and 45% entire processing time compared with the well-known cascaded transcoder while maintaining the video quality.     

H.264帧内预测模式快速判定算法研究

帧内预测作为H.264中提高编码效率的重要部分,其采用了率失真优化技术（RDO）进行预测模式的选择,但同时编码复杂度和计算量也明显增加.为此,提出一种快速判定算法.该算法利用区域图像的质心坐标对区域图像的平坦性和方向性进行判断,算法通过判断宏块的平坦性提前选定块大小,根据4×4块的纹理方向,确定预测模式集,降低算法复杂度.实验结果表明,与H.264标准参考编解码器JM8.6相比,所提算法编码时间节省50％以上,峰值信噪比和码率变化不大.     

H．264的信道适应性分析与仿真

H.264通过编码端的差错弹性工具,解码端的误码掩盖措施来增强对误码信道的适应性。分析了H.264为增强抗误码性能而采取的主要措施和H.264的校验模型JM对信道误码的处理方法,提出了一种H.264的信道适应性仿真方法,并使用国际上推荐的测试环境进行了仿真,仿真结果表明H.264能够很好地适应有线和无线误码信道。     

低速率的无线视频监控系统设计与实现

随着低速率的视频编码技术与无线通信技术的迅速发展,使得为用户提供移动视频监控业务成为可能。这里,文章实现了一套在移动环境下的实时视频监控系统。该系统融合了H.264视频编码技术,并对H.264核心代码进行了优化,以确保其在处理能力较弱的移动终端上流畅解码。实验表明,即使在低速率的无线网络环境下,也可以获得较高质量的监控图像。     

基于PNX1500平台的H.264编码器优化与实现

针对Philips公司的多媒体处理芯片PNX1500硬件结构特点,设计了适应实时信号处理的高性能H.264编码器架构.采用了先进的快速变换和搜索算法,完成了对代码的逐步优化和调试.实验结果表明,该编码器能实现对各种运动幅度视频数据的快速编码,满足不同运动级别视频信号的实时处理.     

Fast block mode decision algorithm in H.264/AVC video coding

The recent video coding standard H.264/AVC show extremely higher coding efficiency compare to any other previous standards. H.264/AVC can achieve over 50% of bit rate saving with same quality using the rate–distortion process, but it brings high computational complexity. In this paper, we propose an algorithm that can reduce the complexity of the codec by reducing the block mode decision process adaptively. Block mode decision process in H.264/AVC consists of inter mode decision process and intra mode decision process. We deal with reduction method for inter and intra mode decision. In this paper an efficient method is proposed to reduce the inter mode decision complexity using the direct prediction methods based on block correlation and adaptive rate distortion cost threshold for early stopping. The fast intra mode reduction algorithm based on inter mode information is also proposed to reduce the computational complexity. The experimental results show that the proposed algorithm can achieve up to 63.34–77.39% speed up ratio with a little PSNR loss. Increment in bit requirement is also not much noticeable.     

Batch-pipelining for multicore H.264 decoding

Pipelining has been applied in many area to improve system performance by overlapping executions of hardware or software computing stages. However, direct pipelining for H.264 decoding is difficult because video bitstreams are encoded with lots of dependencies and little parallelism is left to be explored. Fortunately, pure software pipelining can still be applied to H.264 decoding at macroblock level with reasonable performance gain. However, the pipeline stages might need to synchronize with each other and incur lots of extra overhead. For optimized decoders, the overhead is relatively more significant and software pipelining might lead to negative performance gain. We first group multiple stages into larger batches and execute these batches concurrently, called batch-pipelining, to explore more parallelism on multicore systems. Experimental results show that it can speed the decoding up to 89% and achieve up to 259 and 69 frames per second for resolution 720P and 1080P, respectively, on a 4-core ×86 machine over an optimized H.264 decoder. Because of its flexibility, batch-pipelining can be applied to not only H.264 but also many similar applications, such as the next-generation video coding: high efficiency video coding. Therefore, we believe the batch-pipelining mechanism creates a new effective direction for software codec development.