Zero-temperature-coefficient biasing point of partially depletedSOI MOSFET's

Experimental and analytical results of the front gate bias (V_GS) and the drain current (I_DS) with the drain voltage (V_DS) of partially depleted (PD) SOI MOSFET at the Zero-Temperature-Coefficient (ZTC) point over a very wide temperature range (25-300°C) are presented. Two distinct ZTC points are identified, one in the linear region and the other is in the saturation region. Additionally, the analysis takes into consideration the body effects, and mobility degradation with applied front gate bias. The analysis results are in excellent agreement with the experimental results     

Measurement of substrate current in SOI MOSFETs

A new “Quasi-SOI” MOSFET structure is shown to allow direct measurement of substrate current in a fully-depleted SOI device. The holes generated by impact ionization near the drain are collected at the substrate terminal after they have traversed the source-body barrier and caused bipolar multiplication. By monitoring this hole current, direct characterization of the impact-ionization multiplication factor, M, and the parasitic bipolar gain, β, was performed. It was found that M-1 increases exponentially with V_DS and decreases with V_GS, exhibiting a drain field dependence. The bipolar gain β was found to be as high as 1000 for V_GS-V_T=0 V and V_DS=-2.5 V, but decreases exponentially as V_DS increases. Finally, it was found that β also decreases as V_GS increases     

Comparison of photoresponsive drain conduction and gate leakage inn-channel pseudomorphic HEMT and MESFET under electro-opticalstimulations

Photoresponsive drain conduction and gate leakage characteristics of n-channel PHEMT and MESFET are comparatively reported as a function of electro optical stimulation (V_GS, V_DS, P_opt; λ=830 nm). Both in PHEMT and MESFET, a strong nonlinearity of drain photoresponse (R) with P_opt was observed and can be modeled empirically as R=κP_opt^-β (κ_PHEMT≫κ_MESFET) where model parameters κ and β accommodate differences in device/epitaxial structures and electrical biases. Gate leakage current was linearly increasing with P_opt while it was independent of V_DS in both PHEMT and MESFET. However, I_G was a strong function of V_GS in PHEMT while it was almost independent in MESFET due to suppressed modulation of photoresponsive depletion width with heavy channel doping. Photonic gate response (R_pG), on the other hand, was observed to be constant in MESFET while it was a strong function of electrical bias in PHEMT     

Measurement of I-V curves of silicon-on-insulator (SOI) MOSFET'swithout self-heating

A new method for measuring the output (I_D-V_D) characteristics of SOI MOSFET's without self-heating is described. The method uses short pulses with a low repetition rate, and a reverse transient loadline construction. The technique is demonstrated by measuring 0.25 μm bulk and SOI MOSFET's with 5-nm gate oxide. Application of the method to the extraction of device temperature as a function of DC power is also illustrated     

Flicker noise in GaN/Al0.15Ga0.85N dopedchannel heterostructure field effect transistors

We have investigated noise characteristics of novel GaN/Al_0.15Ga_0.85N doped channel heterostructure field effect transistors designed for high-power density applications. The measurements were carried out for various gate bias voltages V_GS and with the drain voltage V_DS varying from the linear to the saturation regions of operation V_DS>5 V. Our results show that flicker, e.g., 1/f noise, is the dominant limiting noise of these devices; and the Hooge parameter is of the order of 10 ^-5-10^-4. The gate voltage dependence of 1/f noise was observed in the linear region for all examined V_GS and in the saturation region for V_GS>0. These results indicating low values of the Hooge parameter are important for microwave applications     

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E_m). Experimental results using SOI MOSFET's with body contacts indicate that E_m is just a weak function of thin-film SOI thickness (T_si and that E_m can be significantly lower than in a bulk device with drain junction depth (X _j) comparable to SOI's T_si. The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I_G) of studying E_m in SOI device without body contacts. Thin-film SOI MOSFET's have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought     

$hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE Regrowth

Abstract-We report Al₂O₃Zln_0.53Ga_0.47As MOSFETs having both self-aligned in situ Mo source/drain ohmic contacts and self-aligned InAs source/drain n⁺ regions formed by MBE regrowth. The device epitaxial dimensions are small, as is required for 22-nm gate length MOSFETs; a 5-nm In_0.53Ga_0.47As channel with an In_0.4sAl_0.52As back confinement layer and the n⁺⁺ source/drain junctions do not extend below the 5-nm channel. A device with 200-nm gate length showed I_D = 0.95 mA/mum current density at V_GS = 4.0 V and g_m = 0.45 mS/mum peak transconductance at V_DS = 2.0 V.     

Partially depleted SOI NMOSFET's with self-aligned polysilicon gateformed on the recessed channel region

A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with V_z of 0.773 V and T_ox=7.6 nm is 360 μA/μm at V_GS=3.5 V and V _DS=2.5 V. Improved breakdown characteristics were obtained and the BV_DSS (the drain voltage for 1 nA/μm of I_D at T_GS=0 V) of the device with L_eff=0.3 μm under the floating body condition was as high as 3.7 V     

Transient drain current and propagation delay in SOI CMOS

The transient overshoot in drain current that occurs in thin-film SOI (Si-on-SiO2) MOSFET's because of the floating body in analyzed, and the benefit it can provide to propagation delay (speed) in SOI CMOS digital circuits is assessed. The analysis accounts for the charge coupling between the front and back gates, and hence describes the dependence of the transient drain (saturation) current and propagation delay on the back-gate bias as well as on the switching frequency. Measurements of the transient current in recrystallized SOI MOSFET's and of propagation delay in SOI CMOS inverters and ring oscillators are described and shown to support the theoretical analysis. The current overshoot is especially beneficial in low-voltage circuits, although at high frequencies other floating-body effects can degrade the speed.     

Transient effects in accumulation mode p-channel SOI MOSFET'soperating at 77 K

This paper critically examines the conduction mechanisms in accumulation mode p-channel SOI MOSFET's operating at cryogenic temperatures. In particular, attention is given to the body current component, which in most cases is experimentally not observed at 77 K or 4.2 K. As will be demonstrated, both the body current and the back accumulation current show pronounced transient effects at low temperatures, which are related to the slow generation/recombination of minority carriers. This is caused by deep depletion from the front interface, which suppresses these current components. By the application of either a light pulse or a large drain voltage V_ds minority carriers are generated nearly instantaneously in the body region, rendering the body and the back accumulation components clearly visible     

Low-voltage hot electrons and soft-programming lifetime predictionin nonvolatile memory cells

This paper reports experiments and Monte Carlo (MC) simulations of flash memory cells at the typical bias conditions of read operations (high V_GS and low V_DS) leading to the soft-programming phenomenon. Comparing experiments with simulations we first show that, differently from the previously reported case of homogeneous injection experiments, efficient energy gain mechanisms must be invoked to explain the order of magnitude of gate (I_G) and substrate (I_B) currents at low voltage. Second, the voltage scaling behavior of the soft-programming lifetime is analyzed and the validity of usual extrapolation techniques to evaluate this parameter is addressed     

AC floating body effects and the resultant analog circuit issues insubmicron floating body and body-grounded SOI MOSFET's

We report the extensive study on ac floating body effects of different SOI MOSFET technologies. Besides the severe kink and resultant noise overshoot and degraded-distortion in partially depleted (PD) floating body SOI MOSFET's, we have investigated the residue ac floating body effects in fully depleted (FD) floating body SOI MOSFET's, and the different body contacts on PD SOI technologies. It is important to note that there is a universal correlation between ac kink effect and Lorentzian-like noise overshoot regardless of whether the body is floating or grounded. In addition, it was found that third-order harmonic distortion is very sensitive to floating body induced kink or deviation on output conductance due to the finite voltage drop of body resistance. These results provide device design guidelines for SOI MOSFET technologies to achieve comparable low-frequency noise and linearity with Bulk MOSFET's     

Direct tunneling-induced floating-body effect in 90-nm pseudo-kink-free PD SOI pMOSFETs with DTMOS-like behavior and low input power consumption

This paper reports the investigation of the direct tunneling-induced floating-body effect in 90-nm H-gate floating body partially depleted (PD) silicon-on-insulator (SOI) pMOSFETs with dynamic-threshold MOS (DTMOS)-like behavior and low input power consumption. Based on this paper, with the decrease of the gate-oxide thickness, the direct-tunneling current will dominate the floating body potential of H-gate PD SOI pMOSFETs, which makes the floating body potential highly gate voltage dependent like DTMOS behavior with a larger drain current. However, the input power consumption is still kept lower. Simultaneously, the highly gate voltage dependent direct-tunneling current will reduce the influence of the impact ionization current on the neutral region with a higher kink onset-voltage. It contributes to the pseudo-kink-free phenomenon in 90-nm H-gate floating body PD SOI pMOSFETs.     

A simple method to qualify the LDD structure against the early modeof hot-carrier degradation

A simple combination of the heating gate technique and measurements of the forward and reverse (source and drain interchanged) saturation I_DS versus V_GS characteristics for an LDD NMOSFET is shown to reveal more information on the nature of an early hot-carrier degradation. Any susceptibility of the LDD structure to this type of degradation leads to an early evolution of the floating gate drain current, and a corresponding evolution in the I_DS versus V_GS curves mentioned above, without affecting the threshold voltage. Our method reveals that the early mode affects both forward and reverse saturation I_DS versus V_GS characteristics. While the effect on the reverse characteristic can be attributed to an increase in the drain parasitic resistance, the effect on the forward characteristic, apparently indicating source side activity, may be actually due to an increase in the effective channel length, as suggested by simulations. An additional new observation of the decrease of the peak substrate current with the floating gate cycles, when coupled with simulations, allow us to locate and quantify the damage at the edge of the gate. We expect our observations to be useful in qualifying the LDD structure     

Adaptive-learning neuron integrated circuits usingmetal-ferroelectric(SrBi2Ta2O9)-semiconductor (MFS) FET's

An adaptive-learning neuron circuit was fabricated for the first time by integrating a metal-ferroelectric-semiconductor (MFS) FET and a complementary unijunction transistor (CUJT) on a silicon-on-insulator (SOI) structure. SrBi₂Ta₂O₉ (SBT) was selected as a ferroelectric gate material and it was deposited by liquid source misted chemical deposition (LSMCD) method. In fabrication of the circuit, a new selective etchant, NH₄F:HCl, was used to remove the unnecessary SBT film, since it was found from preliminary experiments that the parasitic ferroelectric capacitors prevented normal operation of the circuit. It was found that the drain current of the MFSFET was changed gradually by applying a number of input pulses with a sufficiently short duration time of 20 ns. The gradual change in the output pulse frequency of the neuron circuit was also demonstrated as the number of input pulses was increased     

Experimental characterization of the continuous switching regime in floating-body PD SOI MOSFETs

The floating body configuration in partially depleted (PD) SOI MOSFETs gives rise to the switch-on and switch-off transients of the drain current, that can strongly affect the performance of PD SOI circuits. In this work we present an experimental characterization of the impact of those transients on the current delivered under continuous switching operation. The on state current shows a frequency dependent behavior that changes with the bias region. For voltages below the kink where impact ionization is negligible, the current decreases increasing frequency, while for voltages above the kink, the current increases increasing frequency. Thus, circuit instabilities arise at low frequencies. At high frequencies, the transients vanish and the current capability of these devices, particularly in the kink region, can be fully exploited. However, the off state leakage current must also be taken into account.     

Epitaxially-grown GaN junction field effect transistors

Junction field effect transistors (JFETs) are fabricated on a GaN epitaxial structure grown by metal organic chemical vapor deposition (MOCVD). The dc and microwave characteristics of the device are presented. A junction breakdown voltage of 56 V is obtained corresponding to the theoretical limit of the breakdown field in GaN for the doping levels used. A maximum extrinsic transconductance (g_m ) of 48 mS/mm and a maximum source-drain current of 270 mA/mm are achieved on a 0.8 μm gate JFET device at V_GS=1 V and V_DS=15 V. The intrinsic transconductance, calculated from the measured g_m and the source series resistance, is 81 mS/mm. The f_T and f_max for these devices are 6 GHz and 12 GHz, respectively. These JFET's exhibit a significant current reduction after a high drain bias is applied, which is attributed to a partially depleted channel caused by trapped hot-electrons in the semi-insulating GaN buffer layer. A theoretical model describing the current collapse is presented, and an estimate for the length of the trapped electron region is given     

Improved subthreshold characteristics of n-channel SOI transistors

It has been found that certain n-channel MOSFET's fabricated on silicon-on-insulator (SOI) substrates formed by oxygen implantation can havelog (I_{d}): V_{gs}, characteristics with very steep slopes in the subthreshold region. In contradiction to normal models for short-channel transistors on bulk silicon, the slope becomes steeper for shorter gate lengths or higher drain voltages. This effect is shown to be related to the kink in the output characteristics of transistors with floating islands.     

Ferroelectric neuron integrated circuits using SrBi2Ta2O9-gate FET's and CMOS Schmitt-triggeroscillators

A pulse frequency modulation (PFM) type ferroelectric neuron circuit composed of a metal-ferroelectric-semiconductor field effect transistor (MFSFET) and a CMOS Schmitt-trigger oscillator was fabricated on an SOI structure, in which SrBi₂Ta₂O₉ (SBT) was used as a ferroelectric gate material of the FET. It was found that the fabricated MFSFET showed a relatively good I_D-V_G (drain current versus gate voltage) characteristic with a hysteresis loop due to the ferroelectricity of the SBT film and that it acted as a synapse device with adaptive-learning function. It was also found that the output pulse height of the circuit was as high as the power supply voltage and that output pulse frequency was changed as the number of applied input pulses increased     

Analytical models for n+-p+ double-gate SOIMOSFET's

Previously, we proposed n⁺-p⁺ double-gate SOI MOSFET's, which have n⁺ polysilicon for the back gate and p⁺ polysilicon for the front gate to enable adjustment of the threshold voltage, and demonstrated high speed operation. In this paper, we establish analytical models for this device, This transistor has two threshold voltages related to n⁺ and p⁺ polysilicon gates: V_th1 and V_th2, respectively. V _th1 is a function of the gate oxide thickness t_Ox and SOI thickness t_Si and is about 0.25 V when t_Ox/t_Si=5, while V_th2 is insensitive to t_Ox and t_Si and is about 1 V. We also derive models for conduction charge and drain current and verified their validity by numerical analysis. Furthermore, we establish a scaling theory unique to the device, and show how to design the device parameters with decreasing gate length. We show numerically that we can design sub 0.1 μm gate length devices with an an appropriate threshold voltage and an ideal subthreshold swing