The impact of light on current DLTS and gate-lag transients of AlGaAs-GaAs HFETs

Gate-lag transients and "hole-like" deep level transient spectroscopy signals from AlGaAs-GaAs heterostructure field-effect transistors are shown to be suppressed by illumination with photons with energy larger than the AlGaAs bandgap. The observed pulse-response dependence on light intensity is reproduced and explained by two-dimensional numerical device simulations based on hole-trap behavior of surface deep levels.     

Fabrication and characterization of field-plated buried-gate SiC MESFETs

Silicon carbide (SiC) MESFETs were fabricated using a standard SiC MESFET structure with the application of the "buried-channel" and field-plate (FP) techniques in the process. FPs combined with a buried-gate are shown to be favorable concerning output power density and power-added efficiency (PAE), due to higher breakdown voltage and decreased output conductance. A very high power density of 7.8 W/mm was measured on-wafer at 3 GHz for a two-finger 400-/spl mu/m gate periphery SiC MESFET. The PAE for this device was 70% at class AB bias. Two-tone measurements at 3 GHz /spl plusmn/ 100 kHz indicate an optimum FP length for high linearity operation.     

Light sensitivity of current DLTS and its implications on the physics of DC-to-RF-dispersion in AlGaAs-GaAs HFETs

The light sensitivity of current deep-level transient spectroscopy (I-DLTS) is analyzed with the aim of gaining insight about the physics of surface-trap related dc-to-RF dispersion effects in AlGaAs-GaAs heterostructure field-effect transistors. I-DLTS experiments under dark reveals three surface-trap levels with activation energies 0.44 eV (h1), 0.59 eV (h2), and 0.85 eV (h3), as well as a bulk trap with activation energy 0.45 eV (e1). While the I-DLTS signal peaks associated with the two shallower surface traps h1 and h2 are suppressed by optical illumination with energy larger than the AlGaAs bandgap, that which is associated with the deepest surface trap h3 is nearly unaffected by light up to the highest intensity adopted. Two-dimensional device simulations assuming that surface traps behave as hole traps provide an interpretation for the observed different light sensitivity of surface traps, explaining it as the result of the temperature dependence of surface hole concentration and negative trap-charge density, making trap-charge modulation at increasing temperature less and less sensitive to excess carriers generated by light.     

Self-heating in high-power AlGaN-GaN HFETs

We compare self-heating effects in AlGaN-GaN heterostructure field effect transistors (HFETs) grown on sapphire and SiC substrates. Heat dissipation strongly affects the device characteristics soon after the application of the source-drain voltage (in less than 10^-7 s). Our results show that in HFET's with the total epilayer thickness less than 1.5 μm, the thermal impedance, Θ is primarily determined by the substrate material and not by the material of the active layer. For our devices grown on 6H-SiC substrates, we measured Θ of approximately 2°C·mm/W, which was more than an order of magnitude smaller than Θ=25°C mm/W measured for similar AlGaN/GaN HFET's grown on sapphire. Our results demonstrate that AlGaN-GaN HFET's grown on SiC substrates combine advantages of superior electron transport properties in AlGaN/GaN heterostructures with excellent thermal properties of SiC, which should make these devices suitable for high-power electronic applications     

GaN HFET研究的最新进展

综述了GaNHFET研究中材料生长和工艺研究的新进展,介绍了器件向高频、大功率方向发展的现状及其应用前景,总结了优化器件性能和商品化问题中的二维场结构和电子态、纳米金属介质层、应变能带工程及介质势垒等重要课题。     

Power and linearity characteristics of field-plated recessed-gate AlGaN-GaN HEMTs

Record power density and high-efficiency operation with AlGaN-GaN high-electron mobility transistor (HEMT) devices have been achieved by adopting a field-plated gate-recessed structure. Devices grown on SiC substrate yielded very high power density (18.8 W/mm with 43% power-added efficiency (PAE) as well as high efficiency (74% with 6 W/mm) under single-tone continuous-wave testing at 4 GHz. Devices also showed excellent linearity characteristics when measured under two-tone continuous-wave signals at 4 GHz. When biased in deep-class AB (33 mA/mm, 3% I/sub max/) device maintained a carrier to third-order intermodulation ratio of 30 dBc up to a power level of 2.4 W/mm with 53% PAE; increasing bias current to 66 mA/mm (6% I/sub max/) allowed high linear operation (45 dBc) up to a power level of 1.4 W/mm with 38% PAE.     

Experimental determination of the ratio of injected hole current and total current in silicon nitride

In a metal-Si3N4-nSi structure, the net minority-carrier generation rate is equal to the hole injection rate into the insulator under balanced conditions. The generation rate has been determined experimentally, giving the ratio of the injected hole current and the total current in the Si3N4 film.     

Thermal analysis of AlGaN-GaN power HFETs

In this paper, we present a thermal analysis of AlGaN-GaN power heterojunction field-effect transistors (HFETs). We report the dc, small-signal, large-signal, and noise performances of AlGaN-GaN HFETs at high temperatures. The temperature coefficients measured for GaN HFETs are lower than that of GaAs pseudomorphic high electron-mobility transistors, confirming the potential of GaN for high-temperature applications. In addition, the impact of thermal effects on the device dc, small-signal, and large-signal characteristics is quantified using a set of pulsed and continuous wave measurement setups. Finally, a thermal model of a GaN field-effect transistor is implemented to determine design rules to optimize the heat flow and overcome self-heating. Arguments from a device, circuit, and packaging perspective are presented.     

Transient charge and current distributions in the nitride of MNOS devices

Transient charge distributions in the nitride of MNOS devices at constant-current pulses have been computed using the pronounced detrapping model of Arnett. The results are compared with available analytical expressions for the limiting cases of small injected-charge levels and the steady state. Centroid versus charge content is computed and fitted by an analytical expression containing three parameters which are related to the electron range before trapping, the steady-state occupied-trap concentration at the oxide boundary, and the Frenkel-Poole coefficient. Charge outflow into the gate electrode is computed and used to obtain the apparent centroid as derived from the shift of flat-band voltage with injected charge.     

High-frequency noise in AlGaN/GaN HFETs

We present in this letter the benefits of GaN-based electronic devices for low-noise MMICs. A temperature-dependent two-temperature noise model for AlGaN/GaN HFETs is implemented on a wide range of bias conditions. This study enables to access the device high-frequency noise parameters, and allow a comparison of the noise performances with SiC and GaAs technologies.     

GaN基HFET的新进展

回顾了氮化镓 ( Ga N)基异质结场效应晶体管 ( HFET)的发展 ,概述了它的直流和微波特性。制作氮化镓基 HFET可以采用不同的器件结构 ,不同的结构有各自的优点 ,对器件性能有很大影响。多数器件采用了其中两种比较成熟的结构 ,文中对这两种结构进行了讨论     

Dynamic current-voltage characteristics of III-N HFETs

A comparative study of the dynamic current-voltage (DI-V) characteristics of III-N heterojunction and double heterojunction field-effect transistors (HFETs and DHFETs) reveals that the current and RF power collapse in HFETs arise from modulation of device series resistances under large input signal. A model based on space-charge limited current through the depletion regions formed at the gate edges due to the charge trapping explains the DI-V behavior and other observations related to the RF current collapse in III-N HFETs.     

Reliability of large periphery GaN-on-Si HFETs

GaN devices exhibit excellent potential for use in many RF applications. However, commercial acceptance of the technology has been hindered by the scarcity and non-statistical nature of reliability results. In this work we present a full device level reliability study of GaN-on-Si HFETs. Reliability results on this technology include three-temperature DC data that show an activation energy of 1.7 eV and an average failure time >10⁷ h at 150 °C. Additionally, long duration DC lifetest (30 000 device hours) and RF lifetest (4000 device hours) results demonstrate a repeatable low drift process. Environmental tests such as autoclave and ESD demonstrate the ruggedness of the material system and technology. Finally, initial failure analysis is discussed.     

Direct tunneling gate leakage current in transistors with ultrathinsilicon nitride gate dielectric

We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si₃N₄) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms mere extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si ₃N₄ gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications     

High temperature performance and operation of HFETs

The high temperature performance of Al_0.75Ga_0.25 As/In_0.25Ga_0.75As/GaAs Complementary Heterojunction FETs (CHFETs) is reported between 25 and 500°C. Both experimental and modeled devices have shown acceptable digital characteristics to 400°C. Digital logic circuits have also been shown to operate at temperatures of over 400°C. This strongly suggests that GaAs based devices are capable of satisfying high temperature electronics requirements in the 125-400°C range. Two dimensional physically based modeling has been used to understand the high temperature operation of the HFETs. This work has shown that the devices suffer from gate limited drain leakage currents at elevated ambient temperatures. This off-state leakage current is higher than anticipated. Simulation has shown that, although forward gate leakage currents are reduced with the heterostructure device design, the reverse current is not     

Mechanism of dislocation-governed charge transport in schottky diodes based on gallium nitride

A mechanism of charge transport in Au-TiB _x -n-GaN Schottky diodes with a space charge region considerably exceeding the de Broglie wavelength in GaN is studied. Analysis of temperature dependences of current-voltage (I–V) characteristics of forward-biased Schottky barriers showed that, in the temperature range 80–380 K, the charge transport is performed by tunneling along dislocations intersecting the space charge region. Estimation of dislocation density ρ by the I–V characteristics, in accordance with a model of tunneling along the dislocation line, gives the value ρ ≈ 1.7 × 10⁷ cm^?2, which is close in magnitude to the dislocation density measured by X-ray diffractometry.     

Breakdown voltage and current collapse of F-plasma treated AIGaN/GaN HEMTs

The breakdown and the current collapse characteristics of high electron mobility transistors （HEMTs） with a low power F-plasma treatment process are investigated. With the increase of F-plasma treatment time, the saturation current decreases, and the threshold voltage shifts to the positive slightly. Through analysis of the Schottky characteristics of the devices with different F-plasma treatment times, it was found that an optimal F-plasma treatment time of 120 s obviously reduced the gate reverse leakage current and improved the breakdown voltage of the devices, but longer F-plasma treatment time than 120 s did not reduce gate reverse leakage current due to plasma damage. The current collapse characteristics of the HEMTs with F-plasma treatment were evaluated by dual pulse measurement at different bias voltages and no obvious deterioration of current collapse were found after low power F-plasma treatment.     

F等离子体处理 AlGaN/GaN HEMT击穿电压和电流崩塌研究

F等离子体处理工艺被广泛的应用于 AlGaN/GaN HEMT增强型器件的研制和栅前处理工艺。本文研究了低功率F处理 AlGaN/GaN HEMT的击穿特性和电流崩塌特性。随着F处理时间的增加,饱和电流下降,阈值电压正向移动。对不同F处理时间的器件肖特基特性分析后发现,120s的F处理后器件栅泄漏电流明显减小,器件击穿电压提高,当F处理时间大于120s后,由于长时间F处理带来的损伤器件栅泄漏电流没有继续减小。采用不同偏置下的双脉冲测试对不同F处理时间的电流崩塌特性进行了研究,低功率F处理后没有发现明显的电流崩塌现象。     

Control of parallel conduction in MOVPE grown InP based HFETs

Several methods for controlling the parallel conduction path at the substrate interface in InP-based HFETs have been investigated. A novel combination of substrate annealing, gas phase etching and semi-insulating buffer layer is shown to provide the most reliable solution to this problem     

Microwave noise performance and modeling of SiGe-based HFETs

Microwave noise performance of SiGe-based heterostructure field effect transistors (HFETs) is presented. Noise parameters for devices with buried channel fabricated on several virtual substrates are discussed. The impact of such strain relieved buffers on device noise performance is estimated by a proper noise de-embedding technique. Then, the noise properties measured in the 2.5-18-GHz frequency range are compared with those of other technologies. Noise parameters of SiGe HFETs are simulated using Pospieszalski's and Van Der Ziel's noise models. Some detrimental effects like access resistances and self-heating effects that negatively impact the microwave noise behavior are discussed and some alternatives to overwhelm them are proposed.