New four-quadrant CMOS analogue multiplier

The letter describes a new four-quadrant CMOS analogue multiplier with a simple circuit configuration. This multiplier is based on the current/voltage characteristics of MOS transistors operating in the triode region. The simulation result shows less than 1% distortion for both input signals of 4Vpp when supply voltages of ± 5V are used.     

Compact low-voltage CMOS four-quadrant analogue multiplier

A compact architecture for a four-quadrant analogue multiplier circuit is presented. The circuit is formed by connecting common source amplifiers with a pair of differential flipped voltage followers. This results in a novel cancellation of the nonlinear terms in the sub-currents, leading to the desired four-quadrant analogue multiplier. The circuit combines low complexity with low-voltage operation and low static power consumption. Simulated results using a 0.35 mum CMOS process are provided     

Low-voltage, four-quadrant, analogue CMOS multiplier

A CMOS four quadrant analogue multiplier that can operate from a supply voltage of 1.5 V is described. The multiplier requires two linear transconductors whose input transistors are operated in their linear region. Simulation results indicate that the nonlinearity can be kept below 0.8%, across the entire differential input voltage range of ±400 mV     

A low-voltage,versatile CMOS four-quadrant analogue multiplier

This paper describes a four-quadrant analogue multiplier circuit using a low-voltage power supply. It comprises two voltage/current adders and a basic multiplier. Its major advantages over other low-voltage multipliers are that it can operate on either a single power supply or two power supplies, and that its output can be the product of two signal currents, the product of two signal voltages, or the product of a signal current and a signal voltage. Second-order effects were analysed and the simulated results revealed that: (1) for a two-power supply voltage of 2?V, the total harmonic distortion is about 1%, whereas the input voltage is 0.4?V_P–P, the power dissipation is about 0.4?mW and the ?3?dB bandwidth is more than 55?MHz; (2) for a single-power supply voltage of 2?V, the total harmonic distortion is about 1%, whereas the input voltage is 0.4?V_P–P, the power dissipation is about 0.2?mW and the ?3?dB bandwidth is more than 55?MHz. Experimental results are provided to confirm the operation of the circuit.     

A new four-quadrant analogue multiplier

A new four quadrant analogue multiplier employing a 555 timer is proposed. Compared to multipliers that use triangular waves, it is simpler and more accurate. Unlike multipliers baaed on charge equilization principles, it requires no time to settle down to new steady state when one of the signals changes.     

Analogue four-quadrant CMOS multiplier with resistors

The letter will present an integrated analogue four-quadrant multiplier with resistors in CMOS technology. This circuit has a large dynamic range over supply voltages and good linearity, with nonlinearity error less than 2% even when the input voltages are greater than half of the supply voltages.     

A simple CMOS analog four-quadrant multiplier

A simple CMOS circuit which performs analog four-quadrant multiplication is described. Transconductance as well as voltage-mode operation is practicable. The basic circuit consists of only two transistors, at least one of which is depletion-mode. We analyze sources of error in the multiplier, and suggest additional circuitry to improve performance. The circuit has been fabricated in thin-film silicon-on-sapphire and test results are reported. Error relative to full-scale output, and total harmonic distortion with individual multiplicands varied sinusoidally, were both observed to be on the order of 1% to 3% with full-scale inputs.     

High frequency gallium arsenide four-quadrant analogue multiplier

A general principle and some basic circuit techniques suitable for the implementation of the four-quadrant analogue multiplier using gallium arsenide depletion-mode MESFET technology are presented. A version of the circuit achieves a simulated accuracy of the order of 2% and a 3 dB bandwidth of 6.5 GHz using level 1 MESFET models in HSPICE.<>     

CMOS four-quadrant multiplier using bias feedback techniques

A new wide-range CMOS four-quadrant multiplier using the bias feedback techniques is presented. Simulation results show that for a power supply of ±5 V, the linear range is over 14 V and the linearity error is less than 1% over a 13 V input range. Experimental results show that the linear range is over ±1 V. The results will be useful in analog signal processing applications     

A 20-V four-quadrant CMOS analog multiplier

A novel technique is presented for performing the analog multiplication in CMOS technology. The circuit handles a wide range of input voltages. The MSO version of Gilbert's six-transistor cell (GSTC) is the basis for this multiplier. A simple source-coupled pair is used to study the MOS GSTC. Then, a technique is introduced for linearizing the source-coupled circuit. This scheme is extended to the MOS GSTC. The voltage ranges are further increased by introducing the folded CMOS GSTC.     

New CMOS four-quadrant multiplier and squarer circuits

A CMOS four-quadrant multiplier and a squarer using the positive feedback loops consisting of the current mirrors are presented. Simulation results are given to verify the theoretical analysis. The input range of this multiplier is over ±2.5V with the linearity error less than 1% and its-3dB bandwidth is about 20MHz. The total harmonic distortion is less than 1% with the input range up to ±2V. The squarer has a ±1.6V input range. Second order effects such as mobility reduction and transistor mismatch have been discussed. Experimental results by using discrete components are also given. The proposed circuits are expected to be useful in analog signal-processing applications.     

CMOS analogue current-steering multiplier

A four-quadrant multiplier circuit for realisation in CMOS is proposed and compromises between characteristics of the design are discussed. The design is optimised for use in the analogue VLSI implementation of neutral networks and the results presented demonstrate that the circuit complies with the requirements of this application.<>     

Four-quadrant CMOS analogue multiplier

A novel two-signal four-quadrant analogue voltage multiplier has been built in CMOS technology. This multiplier relies on the quadratic current/voltage characteristics of MOS transistors in saturation and combines them with switched-capacitor-type voltage dividers and charge transfer circuits to achieve accurate voltage multiplications with low offsets and large dynamic ranges up to several volts throughout the audio frequency range.     

A four-quadrant CMOS analog multiplier for analog neural networks

A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 μm CMOS process. Experimental results obtained from it are presented     

Integrated MOS four-quadrant analogue multiplier using switched-capacitor technique

A fully integrated four-quadrant analogue multiplier based on switched-capacitor technique for realisation of high-speed and high-density analogue LSIs was developed using a MOS VLSI process. Excellent characteristics such as low total harmonic distortion of ?50 dB for two input signals of 1 Vp-p, large dynamic range of 80 dB and fast operation speed of 2 MHz clock rate were obtained. Application to convolvers and correlators is also demonstrated.     

CMOS analog divider and four-quadrant multiplier using poolcircuits

CMOS divider and four-quadrant multiplier circuits using the pool circuits are presented. Using CMOS differential amplifiers and MOS transistors biased in the saturation region, the new analog divider and multiplier are presented. Experimental and simulation results are given-to verify the theoretical analyses. The proposed circuits are expected to be useful in analog signal processing applications     

1.5 V four-quadrant CMOS current multiplier/divider

A low voltage CMOS four-quadrant current multiplier/divider circuit is presented. It is based on a compact V-I converter cell able to operate at very low supply voltages. Measurement results for an experimental prototype in a 0.8 /spl mu/m CMOS technology show good linearity for a /spl plusmn/15 /spl mu/A input current range and a 1.5 V supply voltage.     

Ultra-low-power, class-AB, CMOS four-quadrant current multiplier

A class-AB four-quadrant current multiplier constituted by a class-AB current amplifier and a current splitter which can handle input signals in excess of ten times the bias current is presented. The proposed circuit operation is based on the exponential characteristic of BJTs or subthreshold MOSFETs. The multiplier is designed using the latter devices and achieves very low power consumption. Simulation results show that from a 0.65 V supply, the proposed circuit consumes 12.4 nW static power while less than 230 dB total harmonic distortion is achieved for an input modulation index up to 10.     

CMOS four-quadrant multiplier using bias offset crosscoupled pairs

A CMOS four-quadrant multiplier using bias offset crosscoupled pairs is presented. Simulation results show that a for a power supply of +or-5 V, the linearity error is less than 1% over a +or-2.5 V input range. The effect of mobility reduction is also analysed. The results will be useful in analogue signal processing applications.<>     

CMOS four-quadrant current multiplier using switched current techniques

A new CMOS four-quadrant switched current multiplier, operating from a single 3V power supply and employing two-phase clocking scheme, is proposed. The circuit is designed to perform one multiplication per clock cycle. SPICE simulations using 0.5 /spl mu/m CMOS process parameters have been carried out to verify the multiplier performance.