A Control Circuit With Load-Current Injection for Single-Phase Power-Factor-Correction Rectifiers

A load-current-injection control technique for boost-derived power-factor-correction (PFC) rectifiers with average current-mode control is proposed in this paper. By adding a load-current loop to the conventional inductor current loop, the output voltage response to load steps is speeded up, almost eliminating the typical voltage overshoots of this kind of converters. Although the techniques based on the load-current injection are traditionally called "load feedforward," this paper shows that an additional feedback loop, which modifies the linear small-signal model of the converter, is also introduced. In order to validate the concept, a converter prototype working from a universal input line has been designed and tested, showing that a very fast dynamic response of PFC rectifiers may be achieved in a cost-effective way     

A general technique for derivation of average current mode controllaws for single-phase power-factor-correction circuits without inputvoltage sensing

This paper presents a general technique to derive average current mode control (CMC) laws without input voltage sensing to achieve high power factor for single-phase topologies operating in continuous conduction mode (CCM). The control laws are derived based on the steady-state input-output voltage relationships and the CCM large-signal averaged pulsewidth modulation (PWM)-switch model. Using this methodology, average CMC laws with linear PWM waveforms are discovered for commonly used single-phase power stage topologies such as boost, flyback, SEPIC, and buck/boost. Conventional three-loop-controlled average CMC converters can now be controlled with a two-loop architecture. Hardware results for a boost power factor correction (PFC) and simulation results for flyback, SEPIC, and buck/boost topologies verify operation. The small-signal models of the current loop and voltage loop are derived for the boost topology and are used for control loop design. Input current harmonic distortion measurements demonstrate improved performance compared to the conventional three-loop control technique     

A general three-phase PFC controller for rectifiers with a parallel-connected dual boost topology

A general constant-frequency power-factor-correction (PFC) controller is proposed for three-phase rectifiers with parallel-connected dual-boost topologies. This paper shows that unity power factor and low current distortion in all three phases can be realized by one-cycle control using one integrator with reset along with a few near and logic components. This new extension of one-cycle control provides the core PFC function to the dual-boost topologies. It does not require multipliers, as used in most other control approaches to scale the current reference according to the output power level. In each 60/spl deg/ of AC line cycle, only two switches are switched at high frequency; therefore the switching losses are significantly reduced. All switches are switched at low current, which results in reduced current ratings. This control method is simple and general. It is applicable to three-phase rectifiers that can be decoupled into parallel-connected dual-boost topologies by slight modification of the logic circuit. This control method is verified by experimental results. The proposed controller is suitable to be integrated into a three-phase PFC control chip.     

Current-Mode Linear Transformation Filters Using Current Mirrors

Novel building blocks for designing high-order current-mode filters by employing current mirrors as the elementary active elements are introduced in this paper. As a design example, a fifth-order elliptic current-mode filter is designed using only grounded capacitors. Simulation results using transistor parameters of a typical CMOS 0.35- technology are in a good agreement with the theoretically expected. A comparison with the corresponding current mirror based filter topologies realized using the leapfrog and the wave techniques has been also performed. For this purpose, new leapfrog and wave filter topologies are introduced. Comparison results confirm the benefits offered by the proposed filter configurations.     

Nonlinear Current Control of Single-Phase PFC Converters

A set of new nonlinear current control methods are presented for single-phase power factor corrected ac-dc converters. These control methods combine input current feedforward with partial feedback based on the switch current to achieve sinusoidal input current and unity input power factor. They overcome the limitations of conventional linear (average) current control in terms of control bandwidth and sensitivity to noise, resulting in high-performance input current control which can meet the most stringent harmonic current limits required by variable-frequency airborne power systems. The control methods are also ideally suited for integrated mixed-signal implementation, requiring an analog current controller which is very simple, much less sensitive to noise than conventional linear feedback control, and independent of converter and control design parameters; and a digital controller which operates with a sampling frequency much lower than the switching frequency. Detailed development of the control methods is presented along with their stability analysis and circuit implementation. A prototype converter and its operation are also presented to validate the analysis and to demonstrate the performance of the control methods.     

Stabilizing Technique for AC–DC Boost PFC Converter Based on Time Delay Feedback

It is well known that the ac–dc power factor correction (PFC) boost preregulator can present instability at the line frequency. This nonlinear phenomenon can jeopardize the system performances by increasing the total harmonic distortion and decreasing the power factor. In this brief, a new stabilizing technique is applied using time delay feedback when the system exhibits slow-scale instability under a traditional controller. First, the technique is applied to the averaged model. The results are then validated by numerical simulations using power simulator package. An analytical expression for the stability domain is also provided. It is proven that the proposed technique introduces many advantages to the most and widely used average current mode control through widening the stability region of the PFC converter. Moreover, this technique can also bring the same advantages to other existing commercial control methods for boost and other PFC topologies.      

PWM zero-voltage switching boost-derived converters with outputisolation

In this paper, the basic operations and steady-state analysis for three modified boost-derived power converter topologies are presented. Unlike the conventional boost topology, these power converters provide electrical isolation and zero-voltage switching, while having identical component stresses as those in the conventional boost power converters. Zero-voltage switching and proper transformer-core resetting are achieved from the resonance that occurs between the parasitic capacitance of the power switch and the transformer magnetizing inductance. By introducing a lossless clamping circuit, the voltage stresses across the switching devices are limited to the reflected output voltage to the primary side     

An Efficient Current Distortion Suppression Method for Six-Pulse Bridge Rectifiers

In this paper, an efficient current distortion suppression method for six-pulse bridge rectifiers is presented, whereby high-quality waveforms at both ends of the rectifier are possible. The methodology involves accurate shaping of the dc current by using two forced commutated switches. It is demonstrated, theoretically and experimentally, that this action on the dc side is reflected back on the ac side, and as a result, perfect sinusoidal input currents are achieved. In addition, ripple-free voltages and currents are obtained on the dc side by using electrolytic capacitors and smoothing reactors. Rectifying and inverting operations are possible with a simple control circuit, which is also able to both track rapid load variations and overcome failures more efficiently than other modern alternatives. Selected theoretical results are presented, which are fully validated in a laboratory prototype.     

一种滞环恒流LED驱动电路的电流采样电路

针对滞环恒流大功率LED驱动芯片,提出一款高性能电流采样电路。该电路采用高压工艺,可承受最高达40 V的输入电压。通过分析滞环控制的特点,采用串联电阻采样技术,结合匹配电流源结构,在保证响应速度和采样精度的同时,降低了电路的复杂度。电路中加入输入电压补偿电路,进一步提高了恒流控制的精度。在Cadence下的仿真结果表明,电路可在800 kHz的频率下正常工作,采样精度达99.78%;当电压从15 V变化至35 V时平均负载电流误差为0.81%;输出电压范围为0~5 V。     

Interaction between EMI filter and power factor preregulators withaverage current control: analysis and design considerations

The effects of a nonnegligible source impedance, due to the presence of an input EMI filter, on the stability of power factor preregulators (PFPs) with average current control are analyzed by using a state-space averaged model. Different from previous approaches, it allows us to derive a simple expression for the loop gain in terms of the converter current loop gain. The overall system stability was studied for boost, Cuk, and SEPIC PPP topologies. Based on this model, a simple modification of the standard current control loop is proposed which increases the converter robustness against instabilities. Comparison between model forecasts and experimental measurements was carried out using two prototypes, one based on the boost topology and the other based on the SEPIC topology, both rated at 600 W. Finally, the model accuracy was investigated with measurements at different current loop bandwidths     

Low-Voltage Current Feedback Operational Amplifiers

A number of current feedback operational amplifier topologies suitable for operation in a low-voltage environment are introduced in this paper. Their realization is based on the corresponding low-voltage second generation current conveyor topologies. Important performance factors such as accuracy, bandwidth, and linearity have been considered, and the obtained simulation results have been compared in order to evaluate the behavior of the proposed topologies.     

Current phase control methods for permanent magnet synchronousmotors

Three types of current phase control methods are examined for the interior magnet motor and the surface magnet motor: (1) the i _d=0 control method, (2) the cos φ=1 control method, and (3) the constant-flux-linkage control method. The control circuits for realizing these control methods were investigated and a drive test carried out. The most suitable current phase control method for the rotor geometry was examined by computer simulation and experimentation. It was found that in the i_d=0 control method, high-performance torque control can be obtained as the torque is proportional to the armature current. In the cos φ=1 control method, the torque per armature current is small and the torque characteristic is nonlinear. Therefore, high-performance torque control cannot be expected. The constant-flux-linkage control method is desirable for interior magnet motors as the torque characteristic is almost linear and the required inverter capacity is comparatively small     

Lossless average inductor current sensor for CMOS integrated DC–DC converters operating at high frequencies

A novel average inductor current sensing circuit integrable in CMOS technologies is presented. It is designed for DC–DC converters using buck, boost, or buck-boost topologies and operating in continuous conduction mode at high switching frequencies. The average inductor current value is used by the DC–DC controllers to increase the light load power conversion efficiency (e.g., selection of the modulation mode, selection of the dynamic width of the transistors). It can also be used to perform the constant current charging phase when charging lithium-ion batteries, or to simply detect overcurrent faults. The proposed average inductor current sensing method is based on the lossless sensing MOSFET principle widely used in monolithic CMOS integrated DC–DC converters for measuring the current flowing through the power switches. It consists of taking a sample of the current flowing through the power switches at a specific point in time during each energizing and de-energizing cycle of the inductor. By controlling precisely the point in time at which this sample is taken, the average inductor current value can be sensed directly. The circuit simulations were done with the Cadence Spectre simulator. The improvements compared to the basic sensing MOSFET principle are a lower power consumption because no high bandwidth amplifier is required, and less noise emission because the sensing MOSFET is no more switched. Additionally, the novel average inductor current sensing circuit overcomes the low bandwidth limitation previously associated with the sensing MOSFET principle, thus enabling it to be used in DC–DC converters operating at switching frequencies up to 10 MHz and above.     

Bipolar Current Feedback Amplifier: Compensation Guidelines

The aim of the paper is to discuss in detail the compensation of the current feedback amplifier (CFOA). The approach is suitable for a pencil-and-paper compensation and takes into account both resistive and capacitive feedback. The frequency limitation inside the CFOA and due to a load capacitor are also considered. The feature of the CFOA which can be simply compensated for when it is configured as a differentiator is also exploited. To validate the proposed strategies, Spice simulations were performed on the fundamental CFOA topologies, and some of them are included and discussed in the paper.     

A new approach for the realization of voltage-mode second-order universal filters using current conveyors

In this work two different types of topologies are derived for realization any second-order filter characteristic by choosing properly, the admittances of passive elements. These topologies use two second-generation current conveyors (CCIIs). One of the topologies involves different types of CCIIs whereas the other uses the same type of CCIIs together with a unity gain voltage buffer. The buffer used provides not only low output impedance but also facilitates cascading of the filter circuits thus obtained. It is possible to derive many different filters realizing any second-order transfer function by the use of the proposed topologies. Moreover, the produced filters have low-sensitivity performance and permit orthogonal controlling of both the quality factor and the natural angular frequency.     

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low-power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. STSCL circuits exhibit a better power–delay performance compared with their static CMOS counterparts in situations where the leakage current constitutes a significant part of the power dissipation of static CMOS gates. The superior control on power consumption, in addition to the lower sensitivity to the process and supply voltage variations, makes the STSCL topology very suitable for implementing ultra-low-power low-frequency digital systems in modern nanometer-scale technologies. An analytical approach for comparing the power–delay performance of these two topologies is proposed.      

Dynamic Current Requirements in Single-Ended Log-Domain Filters

Single-ended log-domain filters must operate Class A: the amplitude of any symmetric signal must be less than the bias current. Even so, peak internal dynamic current requirements can be much greater than the bias currents. Worst-case peak current demands in a second-order log-domain filter are related to modulation index by simple expressions that allow transistor geometries to be optimized for specified signal levels. Several circuit topologies are considered, and some circuit topologies are shown to be better able to supply larger internal currents than others.     

DC characteristics and stability of push-pull and bridge-typezero-current-switched quasi-resonant converter

In the buck-derived, push-pull, and bridge-type topologies the output inductor current during the switched-off interval can free-wheel either through the shorted secondaries of the transformer or through a separate free-wheeling diode (FWD). It is shown that the former method results in highly nonlinear DC voltage-conversion-ratio characteristics for zero-current-switched quasi-resonant converters operating in the half-wave mode. As a result the incremental gain of the power stage of these converters varies with input voltage and load over an extremely wide range, so that it is not possible to achieve stable feedback control with high loop gains using conventional compensation techniques. It is shown that the addition of a FWD not only linearizes the DC characteristics but also reduces current and voltage stresses on semiconductor devices and improves efficiency     

Gate oxide leakage current analysis and reduction for VLSI circuits

In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of I/sub gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I/sub gate/. We find that for technologies with appreciable I/sub gate/, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for I/sub sub/ reduction.     

Performance Analysis of SDN/OpenFlow Controllers: POX Versus Floodlight

Software-Defined Networking (SDN) is an emerging network architecture that is adaptable, dynamic, cost-effective, and manageable. The SDN architecture is a form of network virtualization where the network controlling functions and forwarding functions are decoupled. A setup and configuration task of a control plane to work as an SDN controller is explained in this paper. This paper includes a brief survey of different SDN based OpenFlow-enabled controllers available in various programmable languages. This paper mainly focuses on two OpenFlow-enabled controllers, namely, POX—a Python-based controller and Floodlight—a Java-based controller. A performance comparison of both controllers is tested over different network topologies by analyzing network throughput and round-trip delay using an efficient network simulator called Mininet. A single, linear, tree and custom (user-defined) topologies are designed in Mininet by enabling external controllers. It is obtained that, a percentage improvement in round-trip time for Floodlight over POX is 11.5, 13.9, 19.6 and 14.4% for single, linear, tree and custom topology respectively. Similarly, a percentage improvement in throughput for Floodlight over POX is 5.4, 8.9, 3.8 and 4.9% for single, linear, tree and custom topology respectively.