Two-layer resist structure for electron-beam fabrication of a submicrometer gate length GaAs device

A two-layer resist structure using EBR-9 and PMMA for fabricating a fine metal line with a mushroom-like cross-sectional profile is reported. The structure provides T-shaped resist cavities with undercut profiles using electron-beam exposure. With the optimum developing condition, the bottom opening is as small as 0.1 µm, and the top opening is wide enough not to require an additional exposure in order to obtain a mushroom-like metal lift-off pattern. A Monte Carlo calculation is carried out in order to analyze the profile of the two-layer resist structure, and it is shown that an undercut T-shaped resist profile with a 0.1-µm bottom opening can be obtained using a high-sensitivity resist on a low-sensitivity resist structure. A 0.15-µn mushroom-like lift-off metal profile has been fabricated on a 0.1-µm recessed GaAs substrate by the use of this resist structure.     

Boundary conditions in regional Monte Carlo device analysis

A new set of boundary conditions is proposed which allows Monte Carlo (MC) calculations to be carried out accurately in preselected regions of a device structure, thus avoiding impractically long computation time. This technique has been applied to three different silicon device structures: an n-p junction, a 0.3-µm basewidth n⁺-n-n⁺diode, and an n⁺-p-n-n⁺bipolar-transistor structure with a 0.1-µm basewidth. The results indicate difficulties with the MC method when applied to regions where a large retarding field exists. A comparison of the results where both the entire device structure can be analyzed and the "regional" MC calculation can be performed, using the proposed boundary conditions, shows good agreement. The computation time using the regional approach, however, is substantially less.     

Modeling for an AlGaAs/GaAs heterostructure device using Monte Carlo simulation

Two-dimensional electron gas behavior in an AlGaAs/GaAs heterostructure FET has been analyzed using the Monte Carlo method. In the channel region, it is assumed that the electrons are subjected to a two-dimensional scattering process. In the other regions, three-dimensional scattering rates are assumed. It is predicted that, in an actual device with 1.20-µm gate length, the transconductance of 250 and 450 mS/mm can be attained at 300 and 77 K, respectively. More efficient performance is possible with improvements in the device structure.     

Mark detection technology in electron-beam direct writing

Monte Carlo (MC) simulation and experimental results are used to investigate mark detection technology in electron-beam (e-beam) direct writing for a 10-kV acceleration voltage. The simulation is based on a single scattering and a continuously slowing down approximation model, and also takes into account the Gaussian profile of the e-beam in order to calculate the backscattered electrons from the mark edges in detail. The simulation results for the alignment signals from a 66° tapered pedestal mark with a 1.1-µm-thickness resist are in good agreement with the experimental results. For the 10-keV e-beam, a location accuracy of about 0.15 µm (3 σ) is obtained by an alignment mark 2.3 µm high and 3.8 µm wide under the same conditions as the simulation. In this study, it is revealed that the simulation for the mark signal makes it possible to evaluate the accuracy of mark detection.     

Variable-shaped electron-beam direct writing technology for 1-µm VLSI fabrication

A 1-µm 256K MOS RAM has been fabricated using a variable-shaped electron-beam (EB) direct writing technology. EB drawing data are prepared using a new program, PEBL, which includes a new algorithm for shot division. PEBL plays an important role in obtaining high EB system throughput and high quality patterns. A new proximity correction technique, DCA, has also been proposed. This technique is simple and very effective in fabricating 1-µm VLSI patterns. Negative resist CMS or positive resist FPM are used appropriately, according to process levels. In fabrication of a 1-µm 256K MOS RAM, ±0.2-µm overlay accuracy and ±0.1-µm linewidth accuracy were achieved.     

Monte Carlo surface scattering simulation in MOSFET structures

The Monte Carlo method has been applied to MOSFET devices with the gate lengths less than 1 µm. The electric field in the channel was obtained by an analytical approach. Since the classical situation is approached in the submicrometer gate device, the partial diffusive model is employed for surface scattering process. Transient phenomena such as velocity overshoot have been predicted with drain biases causing a large field gradient in the channel. Comparison of the results of the Monte Carlo simulation with those obtained by an analytical approach based on static mobility shows that the carrier transit time in the channel is shorter (as much as two times) than that predicted by the analytical approach for a 0.3 µm gate device.     

Monte Carlo modeling of the photo and Auger electron production in X-ray lithography with synchrotron radiation

A Monte Carlo model has been constructed for the photo and Auger electron production in X-ray lithography with synchrotron radiation. First, the accuracy of electron simulation at low energies of 0.1-2.5 keV was checked in comparison with published experimental results of developed depths of polymethyl methacrylate (PMMA) films under electron exposure. The agreement was within about 20 percent. Next, Monte Carlo calculations of X-ray exposure on a 1.0-µm PMMA film were performed for three cases with and without Si and Au Substrates. Etching simulation of pattern profiles for an infinitely fine-line exposure was conducted combining both the solubility rate for a developer of methyl isobutyl ketone and the calculated spatial distribution of absorbed energy in the resist film. Electron orbital energies investigated were 0.7, 1.0, and 1.3 GeV in a synchrotron with a radius of 4 m. The calculated ultimate resolution was found to be about 100 nm. There was no significant difference between the ultimate resolutions at both energies. The exposure time required for the pattern fabrication was less at 1.3 GeV by a factor of 2.8 than at 1.0 GeV. With the Si substrate a favorable compensation was seen for the energy loss near the boundary due to escaped electrons, while with the Au substrate the effect was excessive, suggesting a preference of a lower energy of 1.0 GeV.     

Formation of shallow p+-n junctions using boron-nitride solid diffusion source

Shallow p⁺-n junctions on the order of 0.1-µm deep have been fabricated using boron-nitride (BN) solid diffusion sources. The process combines the hydrogen-injection method and rapid thermal processing (RTP). Sheet resistivities, in ranges from 50 to 130 Ω/sq with junction depths from 0.1 to 0.19 µm, are possible in this technique. Diode characteristics of 0.11-µm junctions show low reverse leakage current, of the order of 10 nA/cm², indicating the possibility of this method to form PMOS source-drain contacts.     

Quantitative evaluation of proximity effect in raster-scan exposure system for electron-beam lithography

The proximity effect in a raster-scan for electron-beam lithography system was evaluated by Monte Carlo calculation and verified by experiments. It was revealed that the reduction in the beam diameter below the scanning pitch, which links into the shortening of drawing time, is more effective in decreasing the proximity effect than the reduction in the resist thickness. From the calculated results, it was found that the error in linewidth definition due to the proximity effect was less than 10 percent at a linewidth of 1.5 µm with scanning pitch of 0.5 µm, beam diameter of 0.2 µm, and PMMA resist of 1.0-µm thickness.     

Biomimetic Polymer Film with Brilliant Brightness Using a One‐Step Water Vapor–Induced Phase Separation Method

The scales of the white Cyphochilus beetles are endowed with unusual whiteness arising from the exceptional scattering efficiency of their disordered ultrastructure optimized through millions of years of evolution. Here, a simple, one‐step method based on water vapor–induced phase separation is developed to prepare thin polystyrene films with similar microstructure and comparable optical performance. A typical biomimetic 3.5 µm PS film exhibits a diffuse reflectance of 61% at 500 nm wavelength, which translates into a transport mean free path below 1 µm. A complete optical characterization through Monte Carlo simulations reveals how such a scattering performance arises from the scattering coefficient and scattering anisotropy, whose interplay provides insight into the morphological properties of the material. The potential of bright‐white coatings as smart sensors or wearable devices is highlighted using a treated 3.5 µm film as a real‐time sensor for human exhalation.     

Dry etching technology for 1-µm VLSI fabrication

A dry etching technology for 1-µm VLSI has been developed. This technology led to successful fabrication of a 1-µm 256-kbit MOS RAM using electon-beam direct writing and molybdenum-polysilicon double-gate structure. Silicon nitride, silicon dioxide, phosphosilicate glass, polysilicon, single-crystal silicon, molybdenum, and aluminum are etched by parallel-plate RF diode reactors. Resist patterns are used as etching masks. The negative resist is CMS and the positive resist is FPM. Plasma polymerization is found to have significant effect on etching selectivity, undercutting, and residue. Directional etching profiles are realized and 1-µm patterns with less than 0.05-µm undercutting are obtained. High etching selectivities are achieved. Methods for preventing and removing contamination as well as damage are established. With these, dry etching proves to bring no adverse effects on device characteristics. Pattern-width fluctuations caused by negative-resist pattern foot are decreased to below 0.1 µm by a new foot trimming technique. Resist step coverage is also clarified.     

Titanium nitride local interconnect technology for VLSI

This paper reports on how the self-aligned titanium disilicide process, normally used to simultaneously reduce MOS gate and junction sheet resistances to less than 1 Ω/square, has been extended to provide a layer of local interconnect for VLSI CMOS applications. The local interconnect level has been realized by utilization of the titanium nitride (TIN) layer that forms during the gate and junction silicidation process. Normally the TiN layer is discarded, but in this process the 0.1-µm-thick TiN layer is patterned and etched to provide local connections between polysilicon gates and n⁺and p⁺junctions, with a sheet resistance of less than 10 Ω/ square. This is accomplished without area consuming contacts or metal straps, and without any extra deposition steps. In addition to providing a VLSI version of the buried-contact process, the technology permits the widespread use of self-aligned contacts and minimum geometry junctions. These features significantly reduce parasitic capacitance with the result that the signal propagation delay through a 1-µm CMOS inverter is decreased by 20- 25 percent. The TiN local interconnect process has been successfully demonstrated by the fabrication of a pseudo-static CMOS VLSI memory with nearly half a million 1-µm transistors. A full CMOS 16K SRAM has also been fabricated in which the TiN layer performs the gate to n⁺and p⁺junction cross-coupling function. Application of the technology to achieve a high-density full CMOS SRAM cell, that makes a 256K SRAM chip size of less than 80K mils²feasible with 1-µm design rules, is also discussed.     

0.4-µm gate-length devices fabricated by contrast-enhanced lithography

This letter describes the fabrication of submicrometer polysilicon-gate MOS devices by an advanced optical process called contrast enhancement. Functional devices having gate lengths as small as 0.4 µm were fabricated with this process. Contrast-enhanced lithography (CEL) allows usable photoresist patterns to be fabricated at smaller dimensions than is possible with conventional resist. The simultaneous replication of mask dimensions for isolated lines at 0.35 µm and above was achieved in this work using a single exposure on an Optimetrix 10:1 DSW system. Contrast enhancement has been applied to the fabrication of n-channel MOS devices having gate lengths from 0.4 to 1.5 µm in steps of 0.1 µm. Long-channel devices were also fabricated. The transconductance of the 0.4-µm devices is 40 mS/mm at Vds= 5 V. Threshold voltages (Vds= 0) are nearly independent of gate length, ranging from 1.21 to 1.31 V over the 7.5- to 0.4-µm range in gate length. The effective mobility for long-channel devices is 430 cm²/V.s.     

Mo- and Ti-silicided low-resistance shallow junctions formed using the ion implantation through metal technique

Mo-and Ti-silicided junctions were formed using the ITM technique, which consists of ion implantation through metal (ITM) to induce metal-Si interface mixing and subsequent thermal annealing. Double ion implantation, using nondopant ions (Si or Ar) implantation for the metal-Si interface mixing and dopant ion (As or B) implantation for doping, has resulted in ultrashallow ( ≤ 0.1-µm) p⁺-n or n⁺-p junctions with ∼30-Ω sheet resistance for Mo-silicided junctions and ∼5.5-Ω sheet resistance for Ti-silicided junctions. The leakage current levels for the Mo-silicided n⁺-p junctions (0.1-µm junction depth) and the Mo-silicided p⁺-n junction (0.16-µm junction depth) are comparable to that for unsilicided n⁺-p junction with greater junction depth ( ∼0.25 µm).     

基于蒙特卡罗方法的烟幕透过率计算与分析

烟幕透过率是表征烟幕干扰性能的重要参数。以等效粒径为0.1μm的石墨为例,就不同形状的石墨粒子组成的烟幕,基于蒙特卡罗方法对烟幕透过率进行了数值计算。利用Mie散射理论和离散偶极子近似(DDA)方法分别计算了球形粒子、椭球形粒子和圆柱形粒子对1.06μm波长的入射光单次散射的消光参量。对于入射光在烟幕中的传输,建立了蒙特卡罗模拟计算模型,利用MATLAB语言编制了相应的计算程序,给出了不同纵横比的椭球形粒子和圆柱形粒子相应的烟幕透过率计算结果,并和等体积球粒子相应的烟幕透过率进行了比较分析。结果表明:透过率与烟幕中粒子形状、粒子数密度、入射光的入射角度及烟幕厚度有关,粒子形状越偏离球形,对应透过率越小。     

Performance of a quarter-micrometer-gate ballistic electron HEMT

The electrical properties of a quarter-micrometer-gate HEMT have been studied by simulation and experiment. An IDSof 11 mA/50 µm, a gmof 500 mS/mm, and an fTof 110 GHz have been predicted by two-dimensional Monte Carlo simulation for certain conditions. The reasons underlying the high performance are discussed in terms of the electron dynamics in the device. A record room-temperature propagation delay time of 9.2 ps/gate at a power dissipation of 4.2 mW/ gate with the maximum transconductance of 400 mS/mm was obtained experimentally for a 0.28-µm-gate HEMT. Only a negligible short-channel effect was observed for reducing the gate length from 1.4 to 0.28 µm.     

Ballistic transport and properties of submicrometer Silicon MOSFET's from 300 to 4.2 K

The characteristics of submicrometer silicon MOSFET's have been measured from 300 to 4.2 K, and the mobility versus temperature and carrier velocity versus longitudinal field as a function of temperature have been plotted. Effective mobilities in 500-µm-square devices as high as 25 000 cm²/V . s at 4.2 K have been observed. Mobilities of this magnitude represent mean free path lengths that could lead to ballistic transport in submicrometer devices. Effective mobilities in 0.2-µm devices were only 800 cm²/V . s at 4.2 K due to high-field effects. The mobility versus effective channel length for 0.2-, 0.7-, and 1.7-µm devices operating at drain voltages of 0.1 V has been plotted, and it has been observed that the mobility is greatly reduced in short-channel devices. The mobility versus longitudinal field was studied, resulting in the observation that ballistic transport is inhibited by the high fields in devices operating at 0.1 V. Similar high-field effects should limit the effects of ballistic transport in high-mobility semiconductors such as submicrometer GaAs FET's Operating at nominal supply voltages.     

Alignment signals from resist-coated marks for direct wafer writing

Monte Carlo (MC) calculations based on a continuous-slowing-down approximation and experimental techniques are used to characterize the backscattered alignment signals from resist-covered Si tapered step marks. Effects of the coated thickness and the resist profile slope are separated by using MC simulation. A 1-µm resist coating on a 2-µm Si step reduces the maximum differenceDeltaSin the back-scattered signal for 20-keV electrons by a factor of 2 and about ⅓ of this reduction is due to the fact that the resist does not conformally follow the step. The rate of reduction inDeltaSwith resist coating was found to be faster for signals collected from low takeoff angles, however, the low takeoff angle signals are still preferred. For a 1-µm resist coating and 20-keV electrons, backscattered electrons with less than half the incident energy contain more information about the substrate but the use of energy analysis techniques would only improve the contrast slightly with a tradeoff in reduced signal-to-noise ratio. For best results alignment marks should a) be covered by a resist thickness less than 0.4 RB(RB= Bethe range) so that electrons will "see" the underlying material, and b) have a depth larger than ⅓ the resist thickness, so that the resist profiles will adequately reflect the underlying mark topography.     

长波长红外光大气信道传输

采用光子追踪法,模拟光子在大气信道中的随机迁移路径及散射后随机迁移方向。引入光束发散角和接收视场角等参数,建立了包含散射作用的长波长红外大气信道传输模型。运用蒙特卡洛方法进行仿真,分析了雾环境下长波长红外光的大气传输特性。与朗伯-比尔定律进行对比,发现在能见度较低、通信距离较近时接收机接收的散射能量不能被忽略。分析了通信距离、能见度、光束发散角、接收视场角对链路损耗的影响,分析了不同阶次散射对接收机接收能量的影响。发现在给定参数条件下,四阶及以上高阶次散射对接收机接收能量几乎可以忽略。     

Study of a 50 nm nMOSFET by ensemble Monte Carlo simulationincluding a new approach to surface roughness and impurity scattering inthe Si inversion layer

A 50 nm nMOSFET has been studied by Ensemble Monte Carlo (EMC) simulation including a novel physical model for the treatment of surface roughness and impurity scattering in the Si inversion layer. In this model, we use a bulk-like phonon and impurity scattering model and surface-roughness scattering in the silicon inversion layer, coupled with the effective/smoothed potential approach to account for space quantization effects. This approach does not require a self-consistent solution of the Schrodinger equation. A thorough account of how these scattering mechanisms affect the transport transient response and steady-state regime in a 50 nm gate-length nMOSFET is given in this paper. A set of I_ds-V_ds curves for the transistor is shown. We find that the smoothing of the potential to account for quantum effects has a strong impact on the electron transport properties, both in transient and steady-state regimes. We also show results for the impact that impurity and surface-roughness scattering mechanisms have on the average velocity of the carriers in the channel and the current flowing through the device. It was found that time-scales as short as 0.1-0.2 ps are enough to reach a steady-state channel electron average velocity