Predicting the process induced warpage of electronic packages using the P–V–T–C equation and the Taguchi method

A critical issue in the manufacturing of electronic packages is the warpage induced during the molding process as a result of differences in the shrinkage of the constituent materials. Package warpage causes serious problems such as the quality degradation of devices and yield loss in manufacturing processes. Loss of lead coplanarity happens due to package warpage and causes difficulty in device testing and surface mount assembly. Internal stresses associated with package warpage can also cause device failures such as die cracking, broken circuits and package cracking.Warpage in IC package has drawn intensive attention in the past. Although the effects of thermal shrinkage were extensively investigated in the literatures, the influence of the cure shrinkage on package warpage had received less attention. Accordingly, this study develops a numerical approach for generating more accurate predictions of the package warpage by taking the effects of both thermal shrinkage and cure shrinkage into account. A three-dimensional finite element model of the small outline package (TSOP) DBS-27P is constructed and the proposed numerical approach, which is based on the P–V–T–C (pressure–volume–temperature–conversion) equation and the CTEs (coefficients of thermal expansion) of the package materials, is employed to predict the warpage at each of its corners under various packaging processing conditions. Using the Taguchi method, the relative influences of the transfer pressure, the packing pressure, the mold temperature and the curing time on the degree of package warpage are identified and the optimal processing conditions are established. A series of experimental packaging trials are performed using the optimal processing conditions. It is found that the warpage of the actual package is in good agreement with that predicted numerically. Therefore, the accuracy of the proposed numerical approach is confirmed. Moreover, the results also demonstrate the capability of the Taguchi method to identify the optimal packaging processing parameters on the basis of a limited number of simulation runs.     

Warpage simulation and experimental verification for 320 mm × 320 mm panel level fan-out packaging based on die-first process

Warpage for 320 mm × 320 mm panel level fan-out packaging based on die-first process was investigated by both simulation and experimental approaches. In the present paper, a simple and efficient FEA (Finite Element Analysis) method based on shell element was introduced. Finite element models were built by using the software of Ansys products to predict and analysis the warpage for feasibility of large panel fan-out packaging technology in aspect of material, package geometries, package size, process conditions and metal density. In order to verify the accuracy and the precision of the simulation method, test vehicle with dies was fabricated by using low cost ‘die first (face down)’ fan-out technology. Warpage of the test vehicle was measured by using Shadow Moiré method. The simulated warpage result and the experimental one exhibit good consistency.     

Deformation Behavior of MEMS Gyroscope Sensor Package Subjected to Temperature Change

In microelectromechanical system (MEMS) devices, the deformation of MEMS structure caused by packaging induced stress is of great concern since it directly affects the performance of the device. In this paper, deformation behavior of the MEMS gyroscope package subjected to temperature change is investigated using a high-sensitivity moire interferometry. Temperature dependent analyses of warpage and extension/contraction of the package are presented. Analysis of the package reveals that global bending deformation occurs due to the mismatch of the coefficient of thermal expansion between the chip, the molding compound, and the printed circuit board. Detailed global and local deformations of the package by temperature change are investigated, and their effect on the frequency shift of the MEMS gyroscope is studied. It is found that package deformation or package induced stress results in the frequency shift of the MEMS gyroscope structure. In order to increase robustness of the structure against deformation, a "crab-leg" type spring is replaced with a semi-folded spring. The results show that the frequency shift is greatly reduced after applying the semi-folded spring. This frequency shift is within the tolerance limit of the gyroscope sensor in this work     

一种用于MEMS超低值封装残余应力的测量方法

微机电系统(MEMS)封装残余应力是在封装工艺过程中芯片上产生的残余应力,它对于MEMS器件的热稳定性和长期贮存稳定性有着十分重大的影响,故而对MEMS封装残余应力的高精确度测量有利于封装应力的研究。由于封装残余应力十分微小,因此无法利用目前的测量手段直接测量封装应力,本文针对这个问题提出了一种基于应力放大结构和拉曼光谱法的封装应力测量方法,可以测量出MEMS器件中封装应力的平均水平。基于理论分析建立了原始封装模型与应力放大结构之间的放大关系,并提出应力放大结构的设计原则。接着采用3D有限元(FEM)仿真对一款高精确度MEMS微加速度计的封装应力测量进行了分析,其结果与理论分析具有很高吻合度。最后,针对该微加速度计的封装应力测量,成功制作了应力放大结构的芯片样片,并进行封装,随后拉曼光谱法被用于测量样片中的最大应力,进而计算出待测微加速度计中平均封装应力大小。实验结果与仿真分析具有很好的吻合度,证明本文所提出的测量方法具有相当的可靠性。     

Numerical modeling of warpage induced in QFN array molding process

Warpage is a critical issue for QFN array molding process. In this paper, a cure-dependent viscoelastic constitutive model is established to model the cure-induced warpage in array molding process. For the relaxation modulus functions of the packaging polymer, the equilibrium moduli are modeled with a model based on scaling analysis and the relaxation behavior of the transient part is described by the cure-dependent relaxation amplitude and reduced relaxation times which are based on the time-conversion superposition principle. The cure-dependent parameters are characterized by using an integrated approach of dynamical mechanical analysis (DMA) and differential scanning calorimetry (DSC) measurements. Finite element modeling is carried out for three configurations of a carrier package map mould and the warpage induced during the curing process and cooling down is predicted. The results show that warpage induced during the curing process has significant contribution on the total warpage of the map.     

MEMS器件WLP封装温度特性的有限元模拟分析与实验

圆片级封装(WLP)技术是一种常用于微电子机械系统(MEMS)器件封装的有效方法。对于具有可动结构的MEMS器件来说,WLP的温度特性会对其性能和可靠性产生重要影响。通过对具有不同面阵列凸点分布形式的WLP封装结构进行有限元模拟,分析了封装过程中芯片有源面在温度载荷影响下的应力分布和变形情况,并通过实验对有限元模拟结果进行了修正。结果表明:对于具有3×3,6×6,9×9面阵列凸点分布形式的WLP封装结构来说,其芯片有源面变形的实际测试结果与修正后的模拟结果非常吻合,误差量分别为5.4%,4.1%和0.3%。     

Coupled package-device modeling for microelectromechanical systems

Microelectromechanical systems (MEMS), by their nature as sensors and actuators, require application specific packaging. The package is the near environment of the MEMS device and hence has a direct effect on its thermal behavior, mechanical effects, environmental compatibility and contamination. Therefore, understanding the influence of the packaging on MEMS device performance is critical to a successfully coupled package-device co-design. Here, an automated package-device interaction simulator has been developed. The simulator uses separate finite element method models for both the package and the device analysis and ties the simulations together through parametric behavioral package models. This technique allows the generation of package model libraries and supports the co-design of application specific packaging and MEMS devices. In the current implementation, thermomechanical package models have been implemented. Experimental verification of the technique is demonstrated by the comparison of simulation results to the measured package strain data. Although MEMS device-package interactions are not the only systems that could benefit from this method, they are a significant application area, focused on here.     

Evaluation of Die Stress in MEMS Packaging: Experimental and Theoretical Approaches

The device performance of microelectromechanical system (MEMS) inertial sensors such as accelerometers and gyroscopes is strongly influenced by the stress developed in the silicon die during packaging processes. This is due to the die warpage in the presence of the stress. It has previously been shown that most of the stress is generated during a die-attach process. In this study, we employ both experimental and theoretical approaches to gain a better understanding in a stress development induced during the packaging processes of a small silicon die (3.5times3.5 mm²). The former approach is accompanied with an optical profilometer while the latter part by a finite element analysis and an analytical model. A specific emphasis is given to the effects of structural parameters such as the die-attach adhesive thickness and material properties on the stress development. The results from all three approaches show good agreement, in that more compliant and thicker adhesives offer great relief in the stress development, as well as bend the die convex downward from its central location. A stress model proposed from this study not only provides a diagnostic tool for very small stress-sensitive devices, but it will also present a design tool for low-stress MEMS packaging systems     

热致封装效应对MEMS固支梁谐振频率的影响

MEMS器件的封装效应显著而复杂,其中由贴片封装引起的结构热失配是封装效应的主要成因.论文在前期封装-器件耦合行为模型的基础上,利用激光多普勒测振仪实验验证了贴片工艺的热致封装效应对固支梁器件性能的影响.结果表明,贴片前后固支梁的谐振频率发生显著变化,并沿芯片表面表现出明显的分布特征.考虑封装效应的理论模型可以较好地预测该结果,为MEMS系统的器件-封装协同设计提供理论指导.     

埋置型叠层微系统封装技术

包含微机电系统(MEMS)混合元器件的埋置型叠层封装,此封装工艺为目前用于微电子封装的挠曲基板上芯片(COF)工艺的衍生物.COF是一种高性能、多芯片封装工艺技术,在此封装中把芯片包入模塑塑料基板中,通过在元器件上形成的薄膜结构构成互连.研究的激光融除工艺能够使所选择的COF叠层区域有效融除,而对封装的MEMS器件影响...     

An embedded overlay concept for microsystems packaging

An embedded overlay concept for packaging hybrid components containing microelectromechanical systems (MEMS) is described. This packaging process is a derivative of the chip-on-flex (COF) process currently used for microelectronics packaging. COF is a high performance, multichip packaging technology in which die are encased in a molded plastic substrate and interconnects are made via a thin-film structure formed over the components. A laser ablation process has been developed which enables selected areas of the COF overlay to be efficiently ablated with minimal impact to the packaged MEMS devices. Analysis and characterization of the ablation procedures used in the standard COF process was performed to design a new procedure which minimized the potential for heat damage to exposed MEMS devices. The COF/MEMS packaging technology is well-suited for many microsystem packaging applications such as micro-optics and radio frequency (RF) devices.     

A Novel Wafer-Level Hermetic Packaging for MEMS Devices

Some emerging microelectromechanical systems (MEMS) devices such as high-performance inertial sensors and high-speed actuators must be operated in a high vacuum and in order to create this vacuum environment, specific packaging is required. To satisfy this demand, this paper presents a novel method for hermetic and near-vacuum packaging of MEMS devices. We use wafer-level bonding technology to combine with vacuum packaging, simultaneously. For this packaging solution, the wafers with air-guided micro-through-holes were placed on a custom-built design housed in a vacuum chamber maintained at a low-pressure environment of sub-10 mtorr. Packaging structure is then sealed by solder ball reflow process with the lower heating temperature of 300degC to fill up micro-through-hole. Experimental results shown the hermetical packaging technique using solder sealing is adapted to the wafer-level microfabrication process for MEMS devices and can achieve better yield and performance. Thus, this technique is very useful for many applications with high performance and low packaging cost can be obtained due to wafer-level processing.     

Analysis of RF MEMS switch packaging Process for yield improvement

Radio frequency microelectro-mechanical systems (RF MEMS) switches offer significant performance advantages in high-frequency RF applications. The switches are actuated by electrostatic force when voltage was applied to the electrodes. Such devices provide high isolation when open and low contact resistance when closed. However, during the packaging process, there are various possible failure modes that may affect the switch yield and performance. The RF MEMS switches were first placed in a package and went through lid seal at 320degC. The assembled packages were then attached to a printed circuit board at 220degC. During the process, some switches failed due to electrical shorting. Interestingly, more failures were observed at the lower temperature of 220degC rather than 320degC. The failure mode was associated with the shorting bar and the cantilever design. Finite element simulations and simplified analytical solutions were used to understand the mechanics driving the behaviors. Simulation results have shown excellent agreement with experimental observations and measurements. Various solutions in package configurations were explored to overcome the hurdles in MEMS packaging and achieve better yield and performance     

Simultaneous Measurement of PWB and Chip Package Warpage Using Automatic Image Segmentation

The shadow moire and projection moire techniques are widely used methods for measuring printed wiring board (PWB) and PWB assembly (PWBA) warpage. Both methods have high resolution, high accuracy and are suitable for use in an online environment. When measuring the warpage of a bare PWB, maximum warpage across the PWB is calculated by subtracting the minimum out-of-plane displacement on the PWB from the maximum out-of-plane displacement on the PWB. However, when the PWB is populated with electronic components (chip packages); the difference between the maximum and minimum out-of-plane displacements on the PWBA is not the warpage of the PWB or the warpage of the chip packages. In order to use warpage measurement methods such as the shadow and projection moire techniques to accurately and separately determine the warpage of a PWB and chip packages in a PWBA, an automated chip package segmentation algorithm is developed and will be presented in this paper. The automated algorithm is based on active contour models (snakes) and can be used to detect chip package locations on an out-of-plane displacement image of a PWBA. This paper will discuss the characteristics of the automated algorithm, which is applicable to all warpage measurement methods, not just the out-of-plane moire methods. Warpage case studies of PWBs populated with plastic ball grid array chip packages measured using the projection moire technique will also be presented and will show that the developed algorithm along with a warpage measurement method is a powerful tool for measuring the warpage of populated PWBs.     

埋置型叠层微系统封装技术

包含微机电系统(MEMS)混合元器件的埋置型叠层封装,此封装工艺为目前用于微电子封装的挠曲基板上芯片(COF)工艺的衍生物。COF是一种高性能、多芯片封装工艺技术,在此封装中把芯片包入模塑塑料基板中,通过在元器件上形成的薄膜结构构成互连。研究的激光融除工艺能够使所选择的COF叠层区域有效融除,而对封装的MEMS器件影响最小。对用于标准的COF工艺的融除程序进行分析和特征描述,以便设计一种新的对裸露的MEMS器件热损坏的潜在性最小的程序。COF/MEMS封装技术非常适合于诸如微光学及无线射频器件等很多微系统封装的应用。     

MEMS中的封装技术研究

MEMS中的封装工艺与半导体工艺中的封装具有一定的相似性 ,因此 ,早期MEMS的封装大多借用半导体中现成的工艺。本文首先介绍了封装的主要形式 ,然后着重阐述了晶圆级封装与芯片级封装[1] 。最后给出了一些商业化的实例     

层叠微芯片封装翘曲行为优化分析

本文以某汽车用芯片为研究对象,研究芯片封装过程结构翘曲优化问题。首先采用Taguchi正交实验设计,结合M oldflow 2016微芯片封装模拟软件,分析各因素对芯片封装过程结构翘曲影响程度及影响规律。选择对芯片翘曲影响较大的因素为响应试验因素,芯片翘曲值为响应目标,进行Box-Behnken试验设计,建立响应面试验因素与目标的数学模型。利用Box-Behnken试验设计构建的数学模型,定义遗传算法优化适应度函数,基于Matlab 2016软件遗传算法工具箱(GUI),通过迭代寻优,获得芯片封装结构翘曲的最小值及最小值时的参数组合。按照芯片翘曲最小值,对芯片原始模型进行反变形补偿,通过实际生产验证,该优化方法具有较高的精度。     

焊料键合实现MEMS真空封装的模拟

结合典型的焊料键合MEMS真空封装工艺,应用真空物理的相关理论,建立了封装腔体的真空度与气体吸附和解吸、气体的渗透、材料的蒸气压、气体通过小孔的流动等的数学模型,确定了其数值模拟的算法．通过实验初步验证了模拟结果的准确性,分析了毛细孔尺寸对腔体和烘箱真空度的影响,实现了MEMS器件真空封装工艺的参数化建模与模拟和仿真优化设计．     

Application of Au-Sn eutectic bonding in hermetic radio-frequency microelectromechanical system wafer level packaging

Development of packaging is one of the critical issues toward realizing commercialization of radio-frequency-microelectromechanical system (RF-MEMS) devices. The RF-MEMS package should be designed to have small size, hermetic protection, good RF performance, and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low-temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at temperatures below 300°C is used. Au-Sn multilayer metallization with a square loop of 70 μm in width is performed. The electrical feed-through is achieved by the vertical through-hole via filling with electroplated Cu. The size of the MEMS package is 1 mm × 1 mm × 700 μm. The shear strength and hermeticity of the package satisfies the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.     

Low stress packaging of a micromachined accelerometer

A packaging study of an acceleration microelectromechanical systems (MEMS) sensor is presented. The sensor consists of two silicon chips: a surface micromachined capacitive transducer (g-cell), which converts acceleration into signals of capacitance variation, and a microprocessor control unit (MCU) for signal conditioning. The two chips are die-bonded into a single piece of leadframe, connected via wire bonding, and finally molded with an epoxy compound. The primary goals of this paper are to provide insight and guidance for designing a package with low stress and low deformation. In particular, two die-bonding schemes: full die attach and four-dot die attach are presented in detail and their impact on performance of the transducer is discussed. Both the numerical simulation and testing data indicated that the four-dot-die-attach process results in a significantly lower packaging stress to the transducer, and is appropriate for stress-sensitive MEMS devices