Investigation of false triggering mechanism

This paper discusses a problem that a half‐bridge circuit can generate, namely a false trigger by high‐speed switching transition. In general, a false trigger occurs by charging a gate–source capacitance because of high‐speed voltage transition and influx of current via a reverse transfer capacitance. Therefore, it is thought that the ratio of the input capacitance and the reverse transfer capacitance is important to check whether a false trigger occurs. However, we find another reason and propose a novel assumption. A novel false triggering mechanism appears by considering the source‐side parasitic inductance. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano‐circuit simulation. The FinFET used in this work is designed using careful engineering of source–drain extension, which simultaneously improves maximum frequency of oscillation ƒ_max because of lower gate to drain capacitance, and intrinsic gain A_V0 = g_m/g_ds, due to lower output conductance g_ds. The framework for the ANN‐based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I_d on drain–source V_ds and gate–source V_gs is derived by a simple two‐layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low‐noise amplifier. At low power (J_ds∼10 µA/µm) improvement was observed in both third‐order‐intercept IIP₃ (∼10 dBm) and intrinsic gain A_V0 (∼20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first‐order to third‐order derivative of I_d with respect to gate voltage and lower g_ds in FinFET compared to bulk MOSFET. Copyright © 2009 John Wiley & Sons, Ltd.     

A three‐phase constant‐current source using an immittance converter

The term immittance converter refers to an impedance–admittance converter. The immittance converter has an input impedance that is proportional to the admittance of the load connected across output terminals. In this converter, the output current is proportional to the input voltage and the input current is proportional to the output voltage. Consequently, it converts a constant‐voltage source into a constant‐current source and a constant‐current source into a constant‐voltage source. It is well known that the quarter wavelength transmission line shows immittance conversion characteristics. However, it has a very long line length for the switching frequency, and is not suitable for power electronics applications. We thus proposed immittance converters that consist of lumped elements L, C and show improved immittance conversion characteristics at a resonant frequency. A three‐phase constant‐current source is proposed in this paper. It is possible to realize this by a simple circuit using an immittance converter. In this paper, circuit operation, characteristic equations, and results of simulation are described. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 151(4): 47–54, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20078     

Impact of stray inductances of the power loop on false trigger‐on in the zero‐voltage‐switching full‐bridge converter

Here, we propose an exhaustive theoretical investigation and experimental verification of the false trigger‐on phenomenon, which would lead to the interaction between the upper and lower devices during the switching transient, in the zero‐voltage‐switching (ZVS) full‐bridge converter. An equivalent model of the converter, which takes not only the parasitic capacitors of the metal–oxide–semiconductor field‐effect transistors into account but also the stray inductances of the main circuit, is presented. Based on the model, a comprehensive study of the false trigger‐on phenomenon is carried out. According to the analysis results, the stray inductances of the metal–oxide–semiconductor field‐effect transistors have negligible influence on the false trigger‐on phenomena since the soft‐switching is realized. The false trigger‐on phenomenon is induced by the stray inductances of the main circuit. Moreover, the arrangement of the switching sequence would cause significant discriminations in the false trigger‐on phenomena because of the specific working mode of the ZVS full‐bridge converter. According to the investigation results, optimization methods are presented to suppress the induced voltage. At last, the theoretical investigations are verified by tests of a ZVS full‐bridge converter. Copyright © 2016 John Wiley & Sons, Ltd.     

Modeling and comparative analysis of DC characteristics of AlGaN/GaN HEMT and MOSHEMT devices

In this paper, a charge control model is developed for AlGaN/GaN High Electron Mobility Transistor (HEMT) and Metal Oxide Semiconductor High Electron Mobility Transistor (MOSHEMT) by considering the triangular potential well in the two‐dimensional electron gas (2DEG) and simulated with matlab . The obtained results from the developed model are compared with the experimental data for drain current, transconductance, gate capacitance and threshold voltage of both devices. The physics‐based models for 2DEG charge density, threshold voltage and gate capacitance have been developed. By using these developed models, the drain current for both linear and saturation modes is derived. The predicted threshold voltage with the variation of barrier thickness has been plotted. A positive threshold voltage can be obtained by decreasing the barrier thickness that builds up the foundation for enhancement mode MOSHEMTs. The predicted C‐V, I_d‐V_gs, I_d‐V_ds and transconductance characteristics show an excellent agreement with the experimental results from the literature and hence validate the developed model. The results clearly establish the potential of using AlGaN/GaN MOSHEMT approach for high power microwave and switching applications. Copyright © 2015 John Wiley & Sons, Ltd.     

Switched‐capacitor‐voltage‐multiplier boost DC–AC inverter with adaptive stages

A multistage switched‐capacitor‐voltage‐multiplier inverter (SCVMI) is proposed with a variable‐conversion‐ratio phase generator and a sinusoidal pulse‐width‐modulation controller for boost DC–AC conversion and high‐efficiency regulation. Its power unit contains: SCVM booster and H‐bridge. The SCVM booster includes two m_c‐stage switched‐capacitor cells and two n_c‐stage switched‐capacitor cells in the interleaving operation to realize DC–DC boost gain of m_c × n_c at most. Here, the variable‐conversion‐ratio phase generator is suggested and adopted to change the running stage number and topological path for a suitable gain level of m × n (m = 1, 2, ?,m_c, n = 1, 2, ?,n_c) to improve efficiency, especially for the lower AC output. The H‐bridge is employed for DC–AC conversion, where four switches are controlled by sinusoidal pulse‐width‐modulation not only for full‐wave output but also for output regulation as well as robustness to source/loading variation. Some theoretical analysis and design include: SCVMI model, steady‐state/dynamic analysis, conversion ratio, power efficiency, stability, capacitance selection, output filter, and control design. Finally, the closed‐loop SCVMI is simulated, and the hardware circuit is implemented and tested. All the results are illustrated to show the efficacy of this scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

Development of gate drive circuit for next‐generation ultrahigh‐speed switching devices

This paper describes a gate drive circuit which is capable of driving an ultrahigh‐speed switching device and of suppressing high‐frequency noise caused by its high dV/dt ratio of 104 V/μs order. SiC (silicon carbide)‐based power semiconductor devices are very promising as next‐generation ultrahigh‐speed switching devices. However, one of their application problems is how to drive them with less high‐frequency noise without sacrificing their ultrahigh‐speed operation capability. The paper proposes a new gate drive circuit specialized for such devices, which charges and discharges the input capacitance of the device by using an impulse voltage generated by inductors. This ultrahigh‐speed switching operation causes a high‐frequency common‐mode noise current in the gate drive circuit, which penetrates an isolated power‐supply transformer due to the parasitic capacitance between the primary and the secondary windings. In order to overcome this secondary problem, a toroidal multicore transformer is also proposed in the paper in order to reduce the parasitic capacitance drastically. By applying the former technique, the turn‐on time and turn‐off time of the power device were shortened by 50% and by 20%, compared with a conventional push‐pull gate drive circuit, respectively. In addition, the latter technique allows reduction of the peak common‐mode noise current to 25%, compared with the use of a conventional standard utility power‐supply transformer. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 176(4): 52–60, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21124     

Impact of high‐κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor

High‐κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III–V GAAFET based on self‐consistent solution of Schrodinger–Poisson equation is proposed. Using this simulator, capacitance–voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant (κ) and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of In_xGa_1‐xAs, channel doping, and cross‐sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005 V/nm for above 10 nm fin width and 0.064 V/nm for sub‐10 nm fin width). Simulation suggests that for lower channel doping below 10²³ m⁻³, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 10²³ m⁻³, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05 V/nm oxide thickness and 0.01 V/per unit change in κ). Copyright © 2014 John Wiley & Sons, Ltd.     

Universal basis for ranking small‐signal aspects of compensation techniques for operational amplifiers

A multi‐pole gain‐bandwidth theorem sets an upper bound to the bandwidth that can be achieved with specified DC gain and external load capacitance, for a given selection of transistors and operating points. A product of the poles and zeros is constrained by ∏(g_m/C) evaluated over the forward‐path active devices. Most practical compensation techniques degrade the actual bandwidth, by factors which the paper explores in detail; depending on the circuit topology, some compensating capacitors can add to the intrinsic device capacitances. A few techniques achieve the ideal. Copyright © 2010 John Wiley & Sons, Ltd.     

Mapping of circuit variables into two‐port network variables in basic amplifier structures: identifying new topologies

In this paper, we report on a unique observation which enables the unification of the analysis for different amplifier structures. In particular, we report that the change from one type of amplifier to the other can be understood via a mapping of source‐load circuit variables (V_s, R_s, I_i, I_o, I_L, V_o) into two‐port network variables (V₁, V₂, I₁, I₂). As such, unified expressions for (A_v,Z_i,A_i,Z_o) are derived. Further, a Matlab code is written to search for all valid mappings out of 3⁸ different possibilities. Copyright © 2013 John Wiley & Sons, Ltd.     

Constructive approximation of non‐linear discrete‐time systems

It is known that large classes of approximately‐finite‐memory maps can be uniformly approximated arbitrarily well by the maps of certain non‐linear structures. As an application, it was proved that time‐delay networks can be used to uniformly approximate arbitrarily well the members of a large class of causal nonlinear dynamic discrete‐time input–output maps. However, the proof is non‐constructive and provides no information concerning the determination of a structure that corresponds to a prescribed bound on the approximation error. Here we give some general results concerning the problem of finding the structure. Our setting is as follows. There is a large family 𝒢 of causal time‐invariant approximately‐finite‐memory input‐output maps G from a set S of real d‐vector‐valued discrete‐time inputs (with d⩾1) to the set of ℝ‐valued discrete‐time outputs, with both the inputs and outputs defined on the non‐negative integers 𝒵₊. We show that for each ϵ>0, any Gϵ𝒢 can be uniformly approximated by a structure map H(G, ·) to within tolerance ϵ, and we give analytical results and an example to illustrate how such a H(G, ·) can be determined in principle. Copyright © 2000 John Wiley & Sons, Ltd.     

Competitive evolutionary algorithms for building performance database of a microwave transistor

In this work, the simultaneous trade‐off relations among the noise figure F, gain G_T, input V_in, and output V_out VSWRs of a microwave transistor operated at a certain (V_DS, I_DS, f) condition are obtained fast and as accurate as the corresponding analytical results using multiobjective optimization process without any need for expertise on the microwave device, circuit, and noise. Three powerful evolutionary algorithms, cuckoo search, firefly, and differential evolution, are implemented comparatively as a study case to obtain the trade‐off relations of a typical low‐noise amplifier transistor NE3511S02 for its operation between 9 and 17 GHz at V_DS = 2 V and I_DS = 10 mA. Finally, differential evolution is found as the most successful algorithm to demonstrate the typical trade‐off relations of NE3511S02. It can be concluded that these trade‐off relations being obtained by using a signal and noise model of the transistor enable performance database covering all the (F ≥ F_min, G_T, V_in ≥ 1, V_out ≥ 1) quadruples with their (Z_S, Z_L) termination pairs using solely an evolutionary optimization process. Thus, a small signal transistor can be identified by its performance database to be used in the design optimization of high‐performance low‐noise amplifiers with the full device capacity.     

A new modeling approach for circuit‐field‐coupled time‐stepping electromagnetic analysis of saturated interior permanent magnet synchronous motors

This paper proposes a new modeling approach for circuit‐field‐coupled time‐stepping electromagnetic analysis of a saturated interior permanent magnet synchronous motor (IPMSM). To predict the drive performance quickly, the proposed approach consists of a dynamic simulator based on a new analytical model of the d‐ and q‐axis magnetization characteristics (λ‐i_d‐i_q‐θ). The model can take into account not only cross‐saturation but also the harmonics of the inductance distributions and EMF waveforms. The validity of the model is verified from suitable simulation results for the instantaneous current and torque waveforms of the IPMSM. The proposed analysis leads to a dramatic reduction in the computation time compared to circuit‐field‐coupled time‐stepping FEA, while maintaining analytical accuracy. The effectiveness of the proposed method is experimentally verified using a 10‐kW, 15,000‐rpm concentrated‐winding IPM motor. © 2010 Wiley Periodicals, Inc. Electr Eng Jpn, 174(1): 49–58, 2011; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.21024     

Delay‐dependent robust L2–L∞ filtering of T‐S fuzzy systems with time‐varying delays

This paper considers the problem of robust delay‐dependent L₂–L_∞ filtering for a class of Takagi–Sugeno fuzzy systems with time‐varying delays. The purpose is to design a fuzzy filter such that both the robust stability and a prescribed L₂–L_∞ performance level of the filtering error system are guaranteed. A delay‐dependent sufficient condition for the solvability of the problem is obtained and a linear matrix inequality (LMI) approach is developed. A desired filter can be constructed by solving a set of LMIs. Copyright © 2009 John Wiley & Sons, Ltd.     

A switch‐utilization‐improved switched‐inductor switched‐capacitor converter with adapting stage number

A novel closed‐loop switched‐inductor switched‐capacitor converter (SISCC) is proposed by using the pulse‐width‐modulation (PWM) compensation for the step‐up DC–DC conversion/regulation, and together by combining the adaptive‐stage‐number (ASN), control for the higher switch utilization and wider supply voltage range. The power part of SISCC is composed of two cascaded sub‐circuits, including (i) a serial‐parallel switched‐capacitor circuit with n_c pumping capacitors and (ii) a switched‐inductor booster with m_c resonant capacitors, so as to obtain the high step‐up gain of (n_c + 1) × m_c /(1 ? D) at most, where D is the duty cycle of PWM adopted to enhance output regulation as well as robustness to source/loading variation. Besides, the ASN control is presented with adapting the stage number n (n = 0, 1, 2, …, n_c) of pumping capacitors to obtain a flexible gain of (n + 1) × m_c /(1 ? D), and further in order to make the SISCC operating at a properly small duty cycle for improving switch utilization and/or supply voltage range. Some theoretical analysis and control design include formulation, steady‐state analysis, ASN‐based conversion ratio, efficiency, output ripple, stability, inductance and capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on an ASN‐based SISCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2015 John Wiley & Sons, Ltd.     

A gain/efficiency‐enhanced bidirectional switched‐capacitor DC‐DC converter

A closed‐loop gain/efficiency‐enhanced bidirectional switched‐capacitor converter (BSCC) is proposed by combining an adaptive‐conversion‐ratio (ACR) phase generator and pulse‐width‐modulation (PWM) controller for bidirectional step‐up/down DC‐DC conversion and regulation. For realizing gain‐enhanced, the power part consists of one m_c‐stage cell and one n_c‐stage cell in cascade between low‐voltage (LV) and high‐voltage (HV) sides to boost HV voltage into m_c × n_c times voltage of LV source at most, or convert LV voltage into 1/(m_c × n_c) times voltage of HV source at most. For realizing efficiency‐enhanced, the ACR idea with adapting stage number m, n is built in the phase generator to obtain a suitable step‐up/down gain: m × n or 1/(m × n) (m = 1, 2, …, m_c, n = 1, 2, …, n_c). Further, the output regulation and robustness to source/loading variation can be enhanced by PWM on the LV/HV sides. Some theoretical analysis and control design are included as: modeling, steady‐state analysis, conversion ratio, efficiency, capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on a BSCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2012 John Wiley & Sons, Ltd.     

Inner Intrinsically Safe Criterion and Design Considerations of Buck Converter Based on Equivalent Inductance

To obtain the intrinsic safety criterion of the Inner-intrinsic-Safety-Buck-Converter (ISBC) based on equivalent-inductance to guide its optimal design, the Inductor Disconnected Discharge (IDD) behavior of ISBC is researched, and the Equivalent-Simple-Inductive-Circuit (ESIC) based on the equivalent inductance is defined. According to ESIC based on the equivalent-current and the energy equivalence, the expression of the equivalent inductance L_ei is derived. The effect of the inductance L, the capacitance C, the input voltage V_i and the load resistance R_L on L_ei is deeply studied, and it’s pointed out that L_ei increases with the increase of V_i, L, C, and R_L, respectively. According to the minimal ignition current curve of the Simple-Inductive-Circuit (SIC), the nonexplosive intrinsically safe criterion based on L_ei is proposed. Combining the proposed criterion, the output ripple voltage and the expression of L_ei, the design region of the capacitance and inductance of the Buck converter meeting the demands of both inner intrinsic safety and electric performance is obtained. The feasibility of the design method and the proposed criterion is proved by the simulation and experimental results.     

移相控制的LLC变换器轻载增益研究

传统的LLC谐振变换器为适应负载宽范围变化常采用变频控制策略,但存在调频范围过宽、限制感性元件设计、造成了额外的损耗等问题.因此采用变频移相控制方法以缩小调频范围,能够较好地实现原边开关管零电压开关ZVS(zero-voltage switching)及副边整流二极管零电流开关ZCS(zero-current swit...     

Harmonic fold back reduction at the N‐path filters

In this paper, a method is proposed to reduce harmonic fold back (HFB) problem of N‐path filters, without increasing the input reference clock (f_CLK ) frequency. The HFB at the N‐path filter is analyzed, and simple expressions are extracted to model this problem. Using the results of the analysis, an M‐of‐N‐path filter has been proposed that behaves like an M × N‐path filter in terms of HFB problem; however, the f_CLK frequency of this structure is the same as an N‐path filter. To demonstrate the feasibility of the proposed idea, a 3‐of‐4‐path filter is designed, and its characteristics are compared with 4‐path and 12‐path filters by simulation. Impacts of different non‐idealities like clock‐phase error, mismatch, and parasitic capacitance are investigated. The transistor‐level implementation of this filter is performed in 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology. The simulation results show that the filter has the pass‐band gain of 17 dB, tuning range of 0.2–1.2 GHz, −3 dB bandwidth of 25 MHz, quality factor of 8–48, 18 dB out‐of‐band rejection, 16 dB rejection of the third harmonic of switching frequency (f_s ), and the noise figure of 4.35 dB (using ideal G_m cells) and 6.95 dB (for practical G_m cells). The strongest harmonic folding to the filter pass‐band occurs around 11f_s with the attenuation of 23.8 dB. Each G_m cell draws about 12.4 mA from 1.8 V supply, and the out‐of‐band IIP3 and P _{1 dB,CP} are 17 and 4 dBm, respectively. Copyright © 2016 John Wiley & Sons, Ltd.