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1.
    
This paper describes circuit design considerations for realization of low power dissipation successive approximation register (SAR) analog‐to‐digital converter (ADC) with a time‐mode comparator. A number of design issues related to time‐mode SAR ADC are discussed. Also, noise and offset models describing the impact of the noise and offset on the timing error of time‐domain comparator are presented. The results are verified by comparison to simulations. The design considerations mentioned in this paper are useful for the initial design and the improvements of time‐mode SAR ADC. Then, a number of practical design aspects are illustrated with discussion of an experimental 12‐bit SAR ADC that incorporates a highly dynamic voltage‐to‐time converter and a symmetrical input time‐to‐digital converter. Prototyped in a 0.18‐µm six‐metal one‐polysilicon Complementary Metal‐Oxide‐Semiconductor (CMOS) process, the ADC, at 12 bit, 500 kS/s, achieves a Nyquist signal‐to‐noise‐and‐distortion ratio of 53.24 dB (8.55 effective number of bits) and a spurious‐free dynamic range of 70.73 dB, while dissipating 27.17 μW from a 1.3‐V supply, giving a figure of merit of 145 fJ/conversion‐step. Copyright © 2013 John Wiley & Sons, Ltd.  相似文献   

2.
    
Successive approximation register (SAR) analog‐to‐digital converters (ADCs) are widely used due to their low power consumption and area cost. However, testing SAR ADCs on an embedded chip is costly. This paper proposes a capacitance‐ratio quantification design for the linearity test of differential top‐plate sampling SAR ADCs. First, the pattern generator controls the switches connected to the bottom plate of capacitors to create a voltage difference proportional to a certain capacitance ratio on the top plates to be quantified. Then, the proposed mechanism quantifies the capacitance ratio via the auxiliary transistors connected to the input pair of the comparator in the SAR ADC. The capacitance ratios are recorded to construct the differential nonlinearity (DNL) and integral nonlinearity (INL) using the derived construction principles, which simplifies the implementation of the output response analyzer. Thus, the test time and area cost can be reduced with these two proposed mechanisms. For characterizing the DNL, the error between the results obtained using the proposed method and those obtained using conventional linear ramp histogram method is from ?0.10 to 0.11 least significant bits (LSBs). For the INL, the estimation error is from ?0.19 to 0.11 LSBs. Moreover, a test time reduction of about 76% is achieved at the expense of an 18.54% area overhead for the capacitance‐ratio quantification mechanism. Copyright © 2014 John Wiley & Sons, Ltd.  相似文献   

3.
    
Recent progress in CMOS integrated successive approximation (SAR) analog‐to‐digital converters (ADCs) is remarkable in terms of architecture and performance. Because of the inherent non‐necessity of active circuit elements such as operational amplifiers, the SAR architecture is suitable for fine CMOS processes. By using a time‐interleaved architecture, it achieves a very high speed conversion rate of 90 G‐sample/s with an 8‐bit resolution. Also, for applications with very low power consumption, such as wireless sensor nodes, it achieves 84 nW at 10‐bit, 200 k‐sample/s. A high signal to noise and distortion ratio (SNDR) can also be achieved by using several techniques such as an SAR architecture that combines oversampling and noise shaping. This survey paper explains the progress made recently in SAR‐ADC circuit techniques and the achieved performances. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.  相似文献   

4.
    
Four calibration algorithms based on the order statistics about capacitive mismatch are proposed for successive approximation register (SAR) analog-to-digital converter (ADC). An 18-bit split capacitive SAR ADC architecture with redundant bits was used to verify the four calibration algorithms proposed. The main dynamic parameters of the SAR ADC were simulated in MATLAB by 500 Monte-Carlo runs with a standard deviation of 0.1% (σ0/C0 = 0.001 ). And the simulation results of sorting and regrouping method II (SRGII) show that a 21.64-dB enhancement of spurious-free dynamic range (SFDR) and a 3.33-bit improvement of effective number of bits (ENOB) have achieved respectively, whereas the simulation results of sorting and re-exchanging method I (SREI) show that a 21.64-dB enhancement of SFDR and a 3.34-bit improvement of ENOB have achieved, respectively  相似文献   

5.
    
Industrial electronics are in great demand for oil and gas exploration, well drilling, and automotive applications where the operating temperature goes beyond 200 °C. Circuit designs using conventional complementary metal–oxide semiconductor (CMOS) technology are mostly rated at maximum of 125 °C, which is not suitable for harsh environment. In this paper, a high‐temperature (HT) 9‐bit successive approximation register analog‐to‐digital converter (SAR ADC) designed in silicon‐on‐insolation CMOS technology with a sampling rate of 50 kS/s is presented. The design considerations of the HT SAR ADC are discussed from process selection, temperature‐aware circuit design, and measurement perspectives. The ADC achieves an effective number of bit (ENOB) of 8.35 bits and a figure of merit of 93 pJ/step at room temperature. Under HT test, ENOBs of 7.3 bits at 225 °C and 6.9 bits at 300 °C are obtained. The power consumption is 1.52 mW from a 5‐V supply at room temperature and only 2.17 mW at 300 °C. Copyright © 2015 John Wiley & Sons, Ltd.  相似文献   

6.
    
This paper presents an energy‐efficient 12‐bit successive approximation‐register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary‐window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spurious‐free dynamic range and signal‐to‐noise‐and‐distortion ratio. The ADC prototype occupies an active area of 0.12 mm2 in the 0.18‐μm CMOS process and consumes a total power of 0.6 mW from a 1.5‐V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7‐dB signal‐to‐noise‐and‐distortion ratio and 83‐dB spurious‐free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure‐of‐merit of 43 fJ/conversion‐step.  相似文献   

7.
    
A successive approximation register analog‐to‐digital converter (SAR ADC) based on a split‐capacitor digital‐to‐analog converter (CDAC) with a split binary weighted capacitor array and C‐2C ladder is proposed. In present design, a unit split capacitor is used in the CDAC instead of the fractional‐value capacitor in the conventional configuration. The preset error induced by the unit split capacitor and the mismatch error of the upper bit CDAC are self‐calibrated. The calibration range and the impact of calibration DAC resolution on circuit linearity are studied to provide an optimum design guideline. Behavior simulation and post‐layout simulation are performed to verify the proposed calibration method. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.  相似文献   

8.
    
A method for estimating integral nonlinearity (INL) in pipeline analog‐to‐digital converters is presented. In this method, errors in each stage are modeled by an equivalent input‐referred gain error and an input‐referred nonlinearity. For a switched capacitor implementation, the proposed model predicts the maximum statistical INL in terms of capacitor mismatch and also provides an exact formula for INL in terms of finite gain of operational amplifiers. Using this model, it is proved that a high per‐stage resolution reduces the power consumption in low‐speed converters, whereas in high‐speed circuits 1.5‐bit or 2.5‐bit stage is more advantageous. It is also shown that when voltage swing is below 1 V, the lower limit for the size of the capacitors is mainly determined by thermal noise rather than by INL. Copyright © 2008 John Wiley & Sons, Ltd.  相似文献   

9.
    
This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm2 in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.  相似文献   

10.
一种新的基于旋转变压器的测速方法   总被引：1，自引：0，他引：1  
李绍文  吴双 《电气传动》2011,41(8):61-64
提出一种旋转变压器输出信号的软件解调方法,即不使用RDC(resolve to digital converter)芯片转换,而是直接将旋转变压器输出的模拟信号连接到DSP (TMS320F2812)的模拟一数字转换(ADC,analog to digital converter)模块上,通过软件算法对旋转变压器的输出...  相似文献   

11.
    
This paper describes a fully differential, cyclic, analogue‐to‐digital converter (ADC). It utilizes a 4‐bit binary weighted capacitor array to obtain 9‐bit resolution. The ADC uses an operational amplifier to suppress supply voltage variations. The operational amplifier with the slew‐rate detection is used to increase the speed of the ADC. The ADC is fabricated in IBM 0.13 μm CMOS process and occupies 650 × 850μm2 active area. At 10 kS/s sampling rate, the ADC consumes 11 μW. In order to test immunity of the ADC on the supply voltage variations, static and dynamic performance of the ADC is measured with triangular supply voltage (V D C  = 1.5 V, V A C  = 200mV pp, f  = 1 kHz). The measured peak of differential nonlinearity and integral nonlinearity is  + 0.26/ − 0.67 and  + 0.65/ − 0.59, respectively. At 250 Hz, effective number of bit is 8.4 bits, S F D R  = 66.7 dB and S N D R  = 52.6 dB. Copyright © 2016 John Wiley & Sons, Ltd.  相似文献   

12.
    
A low‐power technique for high‐resolution comparators is introduced. In this technique, p‐type metal‐oxide‐semiconductor field‐effect transistors are employed as the input of the latch of the comparator just like the input of the preamplifier. The latch and preamplifier stages are activated in a special pattern using an inverter‐based controller. Unlike the conventional comparator, the preamplification delay can be set to an optimum low value even if after the preamplification, the output voltages is less than n‐channel metal‐oxide semiconductor voltage threshold. As a result, the proposed comparator reduces the power consumption significantly and enhances the speed. The speed and power benefits of the proposed comparator were verified using analytical derivations, PVT corners, and post layout simulations. The results confirm that the introduced technique reduces the power consumption by 60%, also, provides 57% better comparison speed for an input common mode voltage (Vcm) range of 0‐Vdd/2.  相似文献   

13.
    
This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (TS) and the difference between fall/rise times in the DAC current pulse is 4%TS. Simulated at 600‐MHz sampling frequency (fS) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOMSNDR) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.  相似文献   

14.
    
In this paper, a two‐dimensional dynamic element matching digital to analog converter (2D DEM DAC) is proposed having less design complexity compared to the conventional 2D DEM DAC. A novel unit element selection algorithm is presented in order to alleviate the need for consecutive elements selection that is mandatory in the conventional 2D DEM DAC. The flexibility of this algorithm leads to the introduction of a generalized multidimensional DEM DAC applicable to any resolutions. The multidimensional structure mitigates intersegment mismatch error and improves the spurious‐free dynamic range (SFDR) and intermodulation distortion (IMD). A 12‐bit 2D DEM DAC is simulated in 65‐nm CMOS process using the digital return‐to‐zero (DRZ) technique with 1.2 V of supply voltage and power dissipation of 26 mW. The simulation results show 63.4‐ and 60.71‐dB SFDR at near DC and Nyquist frequency, respectively, and <?61‐dB IMD with 1.25‐GHz sampling frequency.  相似文献   

15.
艾红卫  苏义滨  方刚  周革 《黑龙江电力》2006,28(2):112-114,118
电力控制器以87C196CB单片机为控制核心,数字信号处理芯片ADSP-2185执行数据采集和处理功能.作为主控制器的单片机具有内置的CAN总线接口,使远程通信更容易实现.数据采集采用AD73360模/数转换器芯片,它是一个6通道16位同步模拟输入转换器,与DSP结合实现了对多路电压、电流信号的实时采集与数据处理.  相似文献   

16.
    
In this paper, a switching scheme is presented to reduce the capacitive digital-to-analog converter (DAC) switching energy, area, and the number of switches in successive approximation register (SAR) analog-to-digital converters (ADCs). In the proposed DAC switching method, after a few most significant bits (MSBs) decision, the sampled differential input signal is shifted into two special regions where the required DAC switching energy and area is less than the other regions. This technique can be utilized in most of the previously reported DAC switching schemes to further reduce the capacitive DAC switching energy and area. The conventional and two recently presented DAC switching techniques are utilized in the proposed SAR ADC to evaluate its usefulness.  相似文献   

17.
    
This paper presents a methodology to design reconfigurable switched‐capacitor delta‐sigma modulators (ΔΣMs) capable of keeping their corresponding power efficiency figures constant and optimal for a set of resolutions and signal bandwidths. This method is especially suitable for low‐bandwidth, medium‐to‐high‐resolution specifications, which are common in biomedical application range. The presented methodology is based on an analytic model of all different contributions to the power dissipation of the ΔΣM. In particular, a novel way to predict the static power dissipated by integrators based on class A and class AB operational transconductance amplifier is presented. The power‐optimal solution is found in terms of filter order, quantizer resolution, oversampling ratio, and capacitor dimensions for a targeted resolution and bandwidth. As the size of the sampling capacitors is crucial to determine power consumption, three approaches to achieve reconfigurability are compared: sizing the sampling capacitors to achieve the highest resolution and keep them constant, change only the first sampling capacitor according to the targeted resolution, or program all sampling capacitors to the required resolution. The second approach results in the best trade‐off between power efficiency and simplicity. A reconfigurable ΔΣM for biomedical applications is designed at transistor level in a 0.18‐µm complementary metal–oxide–semiconductor process following the methodology discussed. A comparison between the power estimated by the proposed analytic model and the transistor implementation shows a maximum difference of 17%, validating thus the proposed approach. Copyright © 2014 John Wiley & Sons, Ltd.  相似文献   

18.
借助计算机仿真系统,将实际工业锅炉的一些传感器信号模拟在工控机屏幕上,并将这些信号通过数字量模拟量转换(D/A)接口板输出,供控制系统进行控制。为受训者提供了方便、安全、高效、经济、直观的实训。缩短了在实际操作中熟练的时间,从而提高生产的效率。  相似文献   

19.
    
This paper presents redundancy‐bandwidth scalable techniques to deal with the intersymbol interference distortions for current‐steering digital‐to‐analog converters in high‐speed applications. A switching strategy that explores the use of redundant current sources is proposed to realize a signal‐independent element transition rate, ie, the number of switching activities during the transition of successive sampling clock cycles. With a certain number of redundant current sources, this strategy significantly reduces the intersymbol interference distortions without oversampling operation or causing signal attenuation, which makes it appealing for high‐speed applications. As analyzed in this paper, the number of required redundant current sources is scalable for different bandwidth requirement in specific applications, leading to 3 redundancy‐bandwidth scalable trade‐offs between the cost from redundant current sources and the high‐dynamic‐range bandwidth. In implementation, we propose a custom‐designed decoder, named as the overlap‐controlled data‐weighted averaging (OC‐DWA). Compared with the existing similar‐purpose designs, the proposed OC‐DWA decoder realizes the current sources selection with a simple barrel rotator, which is of much lower hardware complexity and energy consumption. Simulations of a digital‐to‐analog converter with this decoder exhibit an enhanced dynamic range over the entire Nyquist band, which verifies the redundancy‐bandwidth scalability of the proposed techniques.  相似文献   

20.
    
A microelectromechanical digital‐to‐analog converter (MEMDAC) converts digital motion of shuttle actuators operated by the corresponding bits of a binary code into an output displacement proportional to the analog value represented by the input code. In this paper a MEMDAC with improved kinematic design is devised that allows large travel range and high positioning resolution while making the microfabrication process less critical. A lumped‐parameter model of the compliant mechanism of an N‐bit MEMDAC is derived and used to determine the stiffness ratio of flexible members needed for proper mechanical digital‐to‐analog conversion. Furthermore, we analytically investigated the effect of nonuniformity in the device geometry due to the limitations of the microfabrication processes on the linearity of the output displacement. Successful fabrication and release of a 12‐bit MEMDAC demonstrated the manufacturability of the new mechanism, revealing opportunities for MEMS applications in which micropositioners with open‐loop operation, relatively large output range, fine positioning resolution and high repeatability are required. Copyright © 2007 Institute of Electrical Engineers of Japan© 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.  相似文献   

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