Excitation and steam‐valving coordinated robust controller design for multi‐machine power systems based on the multi‐index nonlinear robust control approach

This paper proposes a novel multi‐index nonlinear robust control (MNRC) approach for multi‐machine power systems. The MNRC approach combines multi‐index nonlinear control with the control theory. With the multi‐index nonlinear control, which selects the output functions as arithmetic combination of state variables, multiple performance indices of the controlled system can be achieved simultaneously in the nonlinear control framework. The control is able to ensure that the system possess the desired robust performance during disturbance. Then, excitation and steam‐valving coordinated robust controllers are developed based on the MNRC approach for multi‐machine power systems. The effectiveness of the proposed robust controller is evaluated by a six‐machine power system simulation. Simulation results show that the expected dynamic and steady‐state performances of power system can be achieved with the MNRC approach. Meanwhile, it is able to achieve the prescribed system performance despite the presence of disturbances. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Design of a low‐power high open‐loop gain operational amplifier for capacitively‐coupled instrumentation amplifiers

We present the design of a low‐power high open‐loop gain opamp for use in chopper‐stabilized capacitively coupled instrumentation amplifiers (CCIAs). The opamp utilizes the current‐reuse folded‐cascode topology and a low‐power gain‐boosting technique to maximize its power efficiency and open‐loop gain. The proposed technique is applied to the designs of two CCIAs: the conservative CCIA with a moderate current scaling ratio and the stringent CCIA with a very high current scaling ratio. Utilizing the current scaling ratio of 4:1, the conservative CCIA, designed and fabricated in a 0.18 μ m CMOS process, consumes a total current of 1.69 μ A from a 0.8‐V supply voltage and achieves a thermal noise floor of 56.5 nV/ . Utilizing the current scaling ratio of 38:1, the stringent CCIA, designed and simulated in a 0.13 μ m CMOS process, consumes a total current of 1.4 μ A and achieves a thermal noise floor of 48 nV/ . The proposed design technique should benefit the designs of low‐power instrumentation amplifiers in advanced processes in which channel‐length modulation and the limited current consumption and supply voltage make the designs of high open‐loop gain opamps difficult. Copyright © 2017 John Wiley & Sons, Ltd.     

Averaging effect on stochastic response prediction in FastADR aggregation for building air‐conditioning facilities

This letter reports on the averaging effect on prediction errors of the fast automated demand response (FastADR) power limitation amount calculated by our autoregressive and neural net models for a large number of multi‐type building air‐conditioning facilities. The standard deviation of prediction error variation decreases with the number of FastADR trials according to the rule. This result will be useful for estimating the averaging effect in the prediction of FastADR for a large number of target facilities. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

2‐matrix‐based finite element linear solver for fast transient thermal analysis of high‐performance ICs

In this article, we propose ²‐based finite element (FE) solver for transient thermal analysis of high‐performance integrated circuits (ICs). ²‐matrix is a special subclass of hierarchical matrix or ‐matrix, which was shown to provide a data‐sparse way to approximate the matrices and their inverses with almost linear space and time complexities. In this work, we show that ²‐based mathematical framework can also be applied to FE‐based transient analysis of thermal parabolic partial differential equations. We show how the thermal matrix can be approximated by ²‐representations with controlled error. Then, we demonstrate that both storage and time complexities of the new solver are bounded by , where N is the matrix size. The method can be applied to any thermal structures for both steady and transient analysis. The numerical results from 3D ICs demonstrate the linear scalability of the proposed method in terms of both memory footprint and CPU time. The comparison with existing product‐quality LU solvers, CSPARSE and UMFPACK, on a number of 3D IC thermal matrices, shows that the new method is much more memory efficient than these methods, which however prevents the demonstration of the potential speedup of the proposed method over those methods. Copyright © 2014 John Wiley & Sons, Ltd.     

Improved Modified Switching Transient Pulse Width Modulation (MT‐PWM) Method Applied to H‐Bridge Type Step‐Down Converter

The authors have devised a new method to decrease high‐frequency harmonics in a specific frequency band by modifying the switching transient slope. In previous studies, there were several problems in applying modified transient pulse width modulation (MT‐PWM) to actual converters. In this paper, three problems are solved using an improved MT‐PWM method. First, the MT‐PWM signal was obtained using a trial‐and‐error approach that involved complex computation procedures in the previous studies. In this paper, a new calculation procedure for obtaining the MT‐PWM waveform using a simple calculation is proposed. Second, a new controller (drain‐source voltage controller) based on voltage feedback is proposed in order to realize a modified switching transient to increase the stability of the switching operation. Third, the dependency of MT‐PWM on source voltage variation is investigated in order to implement MT‐PWM in an actual step‐down converter. From this result, the concept of a new type of controller with the source voltage variation taken into consideration is proposed. Finally, the authors attempted to apply MT‐PWM to an H‐bridge converter to expand the application of MT‐PWM. An H‐bridge converter with MT‐PWM for a dc motor drive is successfully operated in an experiment.     

Swarm intelligence based robust active queue management design for congestion control in TCP network

Active queue management (AQM) is an effective solution for the congestion control problem. It can achieve high quality of service (QoS) by reducing the packet dropping probability and network utilization. Three robust control algorithms are proposed in this paper in order to design robust AQM schemes: conventional controller, robust particle swarm optimization (PSO)‐based PID (proportional–integral–derivative) (PSOPID) controller, and robust ant‐colony optimization (ACO)‐based PID (ACOPID) controller. PSO and ACO methods are used to tune the PID controller parameters subject to constraints to achieve the required robustness of the network. Robust PSOPID and ACOPID controllers can achieve desirable time‐response specifications with a simple design procedure and low‐order controller in comparison to the conventional controller. Wide ranges of system parameters change are used to show the robustness of the designed controllers. The ability of the designed controllers to meet the specified performance is demonstrated using MATLAB 7. 11, (R2010b): The MathWorks, Inc.3 Apple Hill Drive Natick, MA USA. On the other hand, to verify the effectiveness of the designed controller, nonlinear simulation is performed using the NS2 package. Finally, it is shown by comparison that the proposed robust ACOPID can achieve more desirable performance than the PSOPID controller and the controllers that have been proposed in previous works. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

filtering for switched discrete‐time systems under asynchronous switching: A dwell‐time dependent Lyapunov functional method

In this article, the filtering problem for switched discrete‐time linear systems under asynchronous switching is addressed in the framework of dwell time, where ‘asynchronous switching’ covers more general and practical cases, for example, the switching lags caused by mode identification process are taken into consideration. Firstly, a novel dwell‐time dependent Lyapunov function (DTDLF) is introduced to solve stability and ?₂ gain analysis problems. The main advantage of DTDLF approach is that the derived conditions are all convex in system matrices, so it is convenient to be applied into filter design with performance instead of weighted performance as many other previous results. Thus, on the basis of DTLDF, a dwell‐time dependent filter with time‐varying structure is proposed to achieve the desirable non‐weighted filtering performance. It is notable that the proposed approach can also easily characterize the relationships among filtering performance, dwell time, and asynchronous time. Two examples are provided to validate the theoretical findings in this paper. Copyright © 2014 John Wiley & Sons, Ltd.     

Investigating the frequency for load‐independent output voltage in three‐coil inductive power transfer system

Using circuit theory, this letter investigates the output voltage characteristics of three‐coil inductive power transfer (IPT) system against load variations and determines the operating frequency to achieve a constant output voltage. First, a three‐coil IPT system is modeled, and the analytical expression of the root‐mean‐square of the output voltage is derived. By substituting the coupling coefficient, the quality factor, and the resonant frequency, we propose an intuitive method of calculating the frequency for load‐independent output voltage for the first time. When the coupling coefficient is relatively small, there are three frequencies that achieve load‐independent output voltage. If the coupling coefficient increases and is greater than , only two frequencies can achieve load‐independent output voltage. Experiments are conducted to confirm these conclusions. Copyright © 2015 John Wiley & Sons, Ltd.     

Low‐power,low‐area preamplifier for ultra high‐speed multi‐channel optical communication system

A novel circuit technique was applied to the design of a preamplifier for ultra high‐speed short‐distance parallel optical communication system in standard 180‐nm CMOS technology. This circuit is featured by low power, low area as well as high gain bandwidth product, and suited for applications in low‐cost process. The restraint on voltage headroom as bottleneck in traditionally adopted regulated cascode configuration has been fundamentally analyzed and lifted by feed‐forward common gate stage to achieve high gain bandwidth product under limited f_T and strict power restriction. Complex poles were carefully assigned to further attain bandwidth extension without sacrifice on power, noise, and chip area. No additional peaking techniques and subsequent gain‐boosting stages are adopted, which makes the design simple and favorable in low‐cost high‐density multi‐channel optical communication system. The preamplifier provides a trans‐impedance gain of up to 52 dBΩ and a 3‐dB bandwidth of 8.4 GHz. Operating under a 1.8‐V supply, the power dissipation is 8 mW, and the chip area is only 0.075×0.08 mm. The measured average input‐referred noise–current spectral density is . Copyright © 2011 John Wiley & Sons, Ltd.     

A robust output error identifier for continuous‐time systems

This paper shows that the adaptive output error identifier for linear time‐invariant continuous‐time systems proposed by Bestser and Zeheb is robust vis‐à‐vis finite energy measurement noise. More precisely, it is proven that the map from the noise to the estimation error is –stable—provided a tuning parameter is chosen sufficiently large. A procedure to determine the required minimal value of this parameter is also given. If the noise is exponentially vanishing, asymptotic convergence to zero of the prediction error is achieved. Instrumental for the establishment of the results is a suitable decomposition of the error system equations that allows us to strengthen—to strict—the well‐known passivity property of the identifier. The estimator neither requires fast adaptation, a dead‐zone, nor the knowledge of an upperbound on the noise magnitude, which is an essential requirement to prove stability of standard output error identifiers. To robustify the estimator with respect to non‐square integrable (but bounded) noises, a prediction error‐dependent leakage term is added in the integral adaptation. –stability of the modified scheme is established under a technical assumption. A simulated example, which is unstable for the equation error identifier and the output error identifier of Bestser and Zeheb, is used to illustrate the noise insensitivity property of the new scheme. Copyright © 2014 John Wiley & Sons, Ltd.     

Robust adaptive dynamic surface control for linear time‐varying systems

In this paper, robust output‐feedback tracking control is considered for a class of linear time‐varying plants whose time‐varying parameters are unknown bounded with bounded derivatives and output is affected by unknown bounded additive disturbances. Using adaptive dynamic surface control technique, the proposed scheme possesses the following advantages: (1) the design procedure is simple and the control law is easy to be implemented, and (2) by introducing an initialization technique, together with adjusting some design parameters, the performance of system tracking error can be guaranteed regardless of the time variation. It is proved that with the proposed scheme, all the closed‐loop signals are semi‐globally uniformly ultimately bounded. Simulation results are presented to demonstrate the effectiveness of the proposed scheme. Copyright © 2013 John Wiley & Sons, Ltd.     

Proposal of shoplifting prevention service using image analysis and ERP check

In this paper, we propose a software‐as‐a‐service application that prevents shoplifting using image analysis and enterprise resource planning (ERP). In Japan, the total damage due to shoplifting has reached 450 billion per year, and each year more than 1000 small book stores give up their business because of shoplifting damage. Based on the recent advancement in cloud technology and data analysis technology, we propose a shoplifting prevention service with the image analysis of security camera movie and ERP data check for small shops. We also confirm the precision ratio of security camera stream movie analysis using the online machine learning framework Jubatus. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Modular‐based adaptive control of uncertain nonlinear time‐varying systems with piecewise jumping parameters

Nonlinear time‐varying systems exist widely in practice. Therefore, it is of great theoretical importance and practical value to investigate the problem of controlling such systems. However, the results available in developing adaptive control to address such a problem are still limited. Especially a majority of them are restricted to be slowly time‐varying linear systems. This paper presents a modular‐based adaptive control scheme for parametric strict feedback nonlinear time‐varying systems. The parameters considered include both continuous and piecewise time‐varying parameters, and they are not necessarily restricted to be slowly time‐varying or infrequent jumping. The technique of adaptive backstepping with nonlinear damping is employed in the control design module, while the parameter projection algorithm is performed on the parameter estimation module. It is proved that the uniform boundedness of all closed‐loop system signals can be guaranteed with the proposed control scheme. The performance of the tracking error in the mean square sense with respect to the parameter variation rate is also established. Furthermore, perfect asymptotically tracking can be achieved when the varying rates of unknown parameters are in the space. Copyright © 2013 John Wiley & Sons, Ltd.     

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

Over the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage‐controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high‐performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap‐gate transistors, this work aims to propose a carbon nanotube field‐effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10‐nm gate‐all‐around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA‐CNTFET‐based ring VCO consumes 85.176 μW at with a 6.12‐ to 10.42‐GHz frequency tuning range. At the worst‐case noise conditions, the proposed design presents ‐90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm² physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA‐CNTFET‐based VCO can be considered as a potential candidate for X‐band satellite communication applications.     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

Ultra‐low‐noise large‐bandwidth transimpedance amplifier

Equivalent input current noise and bandwidth are the most relevant parameters qualifying a low‐noise transimpedance amplifier. In the conventional topology consisting of an operational amplifier in a shunt‐shunt configuration, the equivalent input noise decreases as the feedback resistor (R_F), which also sets the gain, increases. Unfortunately, as R_F increases above a few MΩ, as it is required for obtaining high sensitivity, the bandwidth of the system is set by the parasitic capacitance of R_F and reduces as R_F increases. In this paper, we propose a new topology that allows overcoming this limitation by employing a large‐bandwidth voltage amplifier together with a proper modified feedback network for compensating the effect of the parasitic capacitance of the feedback resistance. We experimentally demonstrate, on a prototype circuit, that the proposed approach allows to obtain a bandwidth in excess of 100 kHz and an equivalent input noise of about 4 fA/ , corresponding to the current noise of the 1 GΩ resistor that is part of the feedback network. The new approach allows obtaining larger bandwidth with respect to those obtained in previously proposed configurations with comparable background noise. Copyright © 2014 John Wiley & Sons, Ltd.     

A robust adaptive control architecture for disturbance rejection and uncertainty suppression with L ∞ transient and steady‐state performance guarantees

In this paper, a new adaptive control architecture for linear and nonlinear uncertain dynamical systems is developed to address the problem of high‐gain adaptive control. Specifically, the proposed framework involves a new and novel controller architecture involving a modification term in the update law that minimizes an error criterion involving the distance between the weighted regressor vector and the weighted system error states. This modification term allows for fast adaptation without hindering system robustness. In particular, we show that the governing tracking closed‐loop system error equation approximates a Hurwitz linear time‐invariant dynamical system with input–output signals. This key feature of our framework allows for robust stability analysis of the proposed adaptive control law using system theory. We further show that by properly choosing the design parameters in the modification term, we can guarantee a desired bandwidth of the adaptive controller, guaranteed transient closed‐loop performance, and an a priori characterization of the size of the ultimate bound of the closed‐loop system trajectories. Several illustrative numerical examples are provided to demonstrate the efficacy of the proposed approach. Copyright © 2012 John Wiley & Sons, Ltd.     

Robust neuro‐adaptive cooperative control of multi‐agent port‐controlled Hamiltonian systems

This paper presents the distributed cooperative tracking control of the multi‐agent port‐controlled Hamiltonian (PCH) systems that are networked through a directed graph. Controller is made robust against the parametric uncertainties using neural networks. Dynamics of the the proposed novel neural network tuning law is driven by both the position and the velocity errors owing to the information preserving filtering of the Hamiltonian gradient. In addition, the PCH structure of the closed‐loop system is preserved and the controller achieves the disturbance attenuation objective. Simulations are performed on a group of robotic manipulators to demonstrate the efficacy of the proposed controller. Copyright © 2015 John Wiley & Sons, Ltd.     

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

This paper presents an energy‐efficient 12‐bit successive approximation‐register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary‐window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spurious‐free dynamic range and signal‐to‐noise‐and‐distortion ratio. The ADC prototype occupies an active area of 0.12 mm² in the 0.18‐μm CMOS process and consumes a total power of 0.6 mW from a 1.5‐V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7‐dB signal‐to‐noise‐and‐distortion ratio and 83‐dB spurious‐free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure‐of‐merit of 43 fJ/conversion‐step.     

A Two‐Stage Inductive Voltage Divider Using a Special Winding Method

Inductive voltage dividers (IVDs) are widely used in the field of ac measurements, such as impedance measurements at audio frequencies. The two‐stage guarded IVD was developed by D.N. Homan and T.L. Zapf about 40 years ago. However, it is not easy to construct a two‐stage guarded IVD. Therefore, we have developed a two‐stage IVD using a special winding method without guarding by magnetic and electrical shields. To reduce the admittances of the winding wires, corrugated polypropylene board is used for the new two‐stage IVD. In addition, the ratio winding and excitation winding are wound toroidally around two FINEMET ring cores using PEW flat cable 0.7 mm in diameter. As a result, the in‐phase ratio errors are within 10^?8 of the input at frequencies of 1 kHz or below. In this report, the winding methods and measurement results of the new two‐stage IVD are described.