Adaptive Multimodule Routers for Multiprocessor Architectures

Recent multiprocessors such as Cray T3D support interprocessor communication using partitioned dimension-order routers (PDRs). In a PDR implementation, the routing logic and switching hardware is partitioned into multiple modules, with each module suitable for implementation as a chip. This paper proposes a method to incorporate adaptivity into such routers with simple changes to the router structure and logic. We show that with as few as two virtual channels per physical channel, adaptivity can be provided to handle nonuniform traffic in multidimensional meshes.     

基于GMPLS的T比特路由器结构研究

GMPLS是一种将电层包交换技术与光层大颗粒度交换技术有机融合在一起的新技术,其统一的控制管理层面简化了网络的结构;在研究了多种T比特路由器结构的基础上,该文提出了一种将电处理技术优势和光技术优势有机结合的光电混合、多种交换颗粒度的大容量交换路由结构。     

Coverage Optimization for Defect-Tolerance Logic Mapping on Nanoelectronic Crossbar Architectures

Emerging nano-devices with the corresponding nano-architectures are expected to supplement or even replace conventional lithography-based CMOS integrated circuits, while, they are also facing the serious challenge of high defect rates. In this paper, a new weighted coverage is defined as one of the most important evaluation criteria of various defect- tolerance logic mapping algorithms for nanoelectronic crossbar architectures functional design. This new criterion is proved by experiments that it can calculate the number of crossbar modules required by the given logic function more accurately than the previous one presented by Yellambalase et al. Based on the new criterion, a new effective mapping algorithm based on genetic algorithm (GA) is proposed. Compared with the state-of-the-art greedy mapping algorithm, the proposed algorithm shows pretty good effectiveness and robustness in experiments on testing problems of various scales and defect rates, and superior performances are observed on problems of large scales and high defect rates.     

Cisco常见路由器密码的恢复

为了安全起见,网络管理员配置网络设备时都会使用密码保护功能,这在一定程度上增加了网络系统的安全性,可是如果忘记了设定的密码,网络管理员则无法登录网络设备,这将会影响到对网络设备的控制与使用.阐述了如何在不丢失路由器原有配置的情况下恢复遗忘的路由器密码.     

Evaluation of Architectures for Mobile Robotics

In this paper we make a comparative study of some successful software architectures for mobile robot systems. The objective is to gather experience for the future design of a new robot architecture. Three architectures are studied more closely, Saphira, TeamBots and BERRA. Qualities such as portability, ease of use, software characteristics, programming and run-time efficiency are evaluated. In order to get a true hands-on evaluation, all the architectures are implemented on a common hardware robot platform. A simple reference application is made with each of these systems. All the steps necessary to achieve this are discussed and compared. Run-time data are also gathered. Conclusions regarding the results are made, and a sketch for a new architecture is made based on these results.     

主动规则的并发控制与死锁处理

在基于规则的主动数据库系统中 ,被触发规则通常以事务模式运行 ,这些并行事务由规则耦合方式确定其开始处理时刻和可串行化提交次序 .本文根据并行事务对于共享数据对象的锁继承和锁剥夺关系 ,提出了一个并发控制算法 ,并基于事务树 (森林 )给出一个有效的死锁检测算法和具有最小代价的死锁恢复算法 .     

Application of Deadlock Risk Evaluation of Architectural Models

Software architectural evaluation is a key discipline used to identify, at early stages of a real‐time system (RTS) development, the problems that may arise during its operation. Typical mechanisms supporting concurrency, such as semaphores, mutexes or monitors, usually lead to concurrency problems in execution time that are difficult to be identified, reproduced and solved. For this reason, it is crucial to understand the root causes of these problems and to provide support to identify and mitigate them at early stages of the system lifecycle. This paper aims to present the results of a research work oriented to the development of the tool called ‘Deadlock Risk Evaluation of Architectural Models’ (DREAM) to assess deadlock risk in architectural models of an RTS. A particular architectural style, Pipelines of Processes in Object‐Oriented Architectures–UML (PPOOA) was used to represent platform‐independent models of an RTS architecture supported by the PPOOA –Visio tool. We validated the technique presented here by using several case studies related to RTS development and comparing our results with those from other deadlock detection approaches, supported by different tools. Here we present two of these case studies, one related to avionics and the other to planetary exploration robotics. Copyright © 2011 John Wiley & Sons, Ltd.     

Deadlock Models and a General Algorithm for Distributed Deadlock Detection

This paper deals with the problem of deadlock detection in asynchronous message passing systems in a system model that covers unspecified receptions and non-FIFO channels. It presents a hierarchy of deadlock models and deadlock detection problems. It abstracts deadlocks by a general deadlock model that has the same modeling power as the OR-AND model; however, it has much concise expressive power. An abstract general definition of deadlocks in distributed systems is presented that defines deadlocks independently of the underlying deadlock model. This formulation can be used to design a single distributed deadlock detection algorithm which uniformly addresses all deadlocks in the context of various request models such as AND, OR, AND-OR, and k-out-of-n requests. A simple generalized deadlock detection algorithm that uses a circulating token is presented to illustrate the concept. The algorithm is formally described and proven correct. Moreover, possible refinements of the basic solution concerning improvements of token routing and parallel implementation are outlined and evaluated. Extensions to individual and global termination issues are also addressed. Since the proposed deadlock detection algorithm is designed around the abstract definition of deadlocks, it has some very favorable features.     

一种无缓存片上网络交叉开关调度机制

提出一种无缓存片上网络的交叉开关调度机制.无缓存是指将路由节点输入端口缓存以及相应的控制逻辑移除,以降低实现开销.该调度机制在每个输入端口设置一条自回环通道,并在“偏转”路由基础上采用一种基于“偏转”和自回环次数的优先级策略,以通过减小“偏转”次数提高无缓存片上网络的网络性能.实验表明,此调度机制相对于基本的无缓存机制,可保证在硬件开销与能耗不增的前提下,提高网络性能;相对于典型的有缓存机制,在负载较低时其网络性能更优,负载较高时性能略低,但可使硬件开销与能耗分别下降58.9％与40.2％,并使频率提高74.6％.     

Measurement and Evaluation of Alternative Computer Architectures

The Army/Navy Computer Family Architecture Committee has developed an approach for quantifying the relative performance of alternative computer architectures.     

软件体系结构的性能评价研究

介绍了软件体系结构的形式化描述方法-化学抽象机(ChemicalAbstractMachine,CHAM),总结了队列网络模型(QueueingNetworkModel,QNM)及其产生过程的特点。基于队列网络模型,由化学抽象机中形式化描述的软件体系结构规约,导出了一种性能评价模型。其目的是提供一个测量集,在高抽象层次上比较两个或更多候选软件体系结构的性能。最后,以多相编译器为例,具体阐述了这种性能评价。     

Efficient Implementations of Software Architectures via Partial Evaluation

The notion of flexibility (that is, the ability to adapt to changing requirements or execution contexts) is recognized as a key concern in structuring software, and many architectures have been designed to that effect. However, the corresponding implementations often come with performance and code size overheads. The source of inefficiency can be identified to be in the loose integration of components, because flexibility is often present not only at the design level but also in the implementation. To solve this flexibility vs. efficiency dilemma, we advocate the use of partial evaluation, which is an automated technique to produce efficient, specialized instances of generic programs. As supporting case studies, we consider several flexible mechanisms commonly found in software architectures: selective broadcast, pattern matching, interpreters, software layers, and generic libraries. Using Tempo, our specializer for C, we show how partial evaluation can safely optimize implementations of those mechanisms. Because this optimization is automatic, it preserves the original genericity and extensibility of the implementation.     

各种服务质量体系的机理及性能评价

进入90年代后,互联网以超摩尔规律的速度增长,Internet上的应用也逐步由单一的数据传送向数据、语音、图像等多媒体信息的综合传输演化。由于Inter-net采用IP协议只能提供简单的点到点“尽力而为”(best-effort)服务,无法提供服务质量(QoS)保证,为适应新的业务,提供对多种QoS业务的支持,必须改进当前的Internet网络。可以说,Internet的迅猛发展使得如何在Internet中支持具有不同QoS要求的应     

Designing a Crossbar Scheduler for HPC Applications

A crucial part of any high-performance computing (HPC) system is its interconnection network. Corning and IBM are jointly developing a demonstration interconnect based on optical cell swtiching with electronic control. Key innovations in the scheduler architecture directly address the main HPC requirements: low latency, high throughput, efficient multicast suppot, and high reliability.     

一种新的路由器多址综合方法

网络中路由器拓扑发现是研究网络结构和行为的重要基础。路由器多址综合问题是拓扑发现中的一个难题。在总结现有的路由器多址综合解决方法后提出一种新的方法——邻居-子网综合法。与以往方法相比,该方法可信度提高、效率变快,效果更加明显,较好地解决了路由器多址综合问题。     

核心路由器中缓存容量问题的研究

目前核心路由器在网络拥塞时用以存储数据的缓存容量巨大,这虽然保持了极高的链路利用率,但使核心路由器的结构更为复杂。斯坦福法则认为路由器中缓存容量可减少为拇指法则的1%。该文指出斯坦福法则会引起较高的丢包率,提出在降低一定链路利用率的情况下,较小的缓存容量也可以获得较低的丢包率和较高的吞吐率。     

一种新的匿名路由器问题解决方案

路由器网络拓扑发现在网络拓扑发现中占有非常重要的作用,也是进行网络分析、建模的基础,与网络安全息息相关。本文针对路由器网络拓扑发现中出现的匿名路由器问题,提出了一种新的解决方案——带条件的最大匿名综合。该方法具有不增加网络负担、适用范围广、高效等优点,使得路由器网络拓扑数据更加准确和完整,是一种较好的匿名路由器解决方案。     

A Comparative Study and Evaluation of Parallel Programming Models for Shared-Memory Parallel Architectures

Nowadays, shared-memory parallel architectures have evolved and new programming frameworks have appeared that exploit these architectures: OpenMP, TBB, Cilk Plus, ArBB and OpenCL. This article focuses on the most extended of these frameworks in commercial and scientific areas. This paper shows a comparative study of these frameworks and an evaluation. The study covers several capacities, such as task deployment, scheduling techniques, or programming language abstractions. The evaluation measures three dimensions: code development complexity, performance and efficiency, measure as speedup per watt. For this evaluation, several parallel benchmarks have been implemented with each framework. These benchmarks are created to cover certain scenarios, like regular memory access or irregular computation. The conclusions show some highlights, like the fact that some frameworks (OpenMP, Cilk Plus) are better for transforming quickly a sequential code, others (TBB) have a small footprint which is ideal for small problems, and others (OpenCL) are suited for heterogeneous architectures but they require a very complex development process. The conclusions also show that the vectorization support is more critical than multitasking to achieve efficiency for those problems where this approach fits.     

Performance Analysis of Integrative QoS Scheme for Routers

This paper proposes an integrative scheme of DiffServ （differentiated service） for the IP-based network. In the scheme, QoS （Quality of Service） is ranked according to the level of both the queuing delay and the drop precedence that base on the relative differentiated service; it does not take the resource reservation problem into consideration for making its implementation more simple and flexible. We will propose an implemented architecture including edge routers and core routers, and the PHB （per-hop-behavior） architecture of the routers is generalized. We adopt ERED （extended random early discard） mechanism for drop precedence and use proportional delay differentiation for queuing delay. In the proportional delay differentiation topic, we propose a new WTP （waiting time priority）-like algorithm. Besides, a new stochastic petri net model of the PHB model is given, and the performance of whole implemented PHB architecture is analyzed, too.