Dry etching technology for 1-µm VLSI fabrication

A dry etching technology for 1-µm VLSI has been developed. This technology led to successful fabrication of a 1-µm 256-kbit MOS RAM using electon-beam direct writing and molybdenum-polysilicon double-gate structure. Silicon nitride, silicon dioxide, phosphosilicate glass, polysilicon, single-crystal silicon, molybdenum, and aluminum are etched by parallel-plate RF diode reactors. Resist patterns are used as etching masks. The negative resist is CMS and the positive resist is FPM. Plasma polymerization is found to have significant effect on etching selectivity, undercutting, and residue. Directional etching profiles are realized and 1-µm patterns with less than 0.05-µm undercutting are obtained. High etching selectivities are achieved. Methods for preventing and removing contamination as well as damage are established. With these, dry etching proves to bring no adverse effects on device characteristics. Pattern-width fluctuations caused by negative-resist pattern foot are decreased to below 0.1 µm by a new foot trimming technique. Resist step coverage is also clarified.     

A 1-µm bipolar VLSI technology

A 1-µm VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 µm. Both nonisolated I²L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a scaled LSI, I²L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 µm. Scaled SPB0400's have been fabricated that operate at clock speeds 3 × higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I²L and STL device designs. Power-delay products of 14 fJ for I²L and 30 fJ for STL have been measured.     

Submicrometer electron-beam direct writing technology for 1-Mbit DRAM fabrication

A 1-Mbit DRAM with 0.5-µm minimum linewidth is fabricated using variable shaped e-beam direct writing technology. A simple linewidth control technique using newly developed submicrometer resists is developed to achieve high resolution and better linewidth accuracy. In addition, a highly accurate registration technique is developed to ensure required overlay. These techniques are successfully used to achieve overlay accuracy of 0.04 µm(σ) and linewidth deviation of 0.018 µm(σ) in the fabrication.     

Deep-implant 1-µm MOSFET structure with improved threshold control for VLSI circuitry

MOSFET structures with an optimized doping profile show improved threshold control and subthreshold performance. This is achieved by a low-dose shallow implant defining the level of the threshold and a higher dose deep implant improving short-channel effects like SDIBL and VDIBL. Besides surface and volume barrier lowering, body effect, parasitic capacitance, avalanche multiplication, and breakdown voltage have been investigated. In spite of the increased substrate sensitivity and junction capacitances, the deep-implant concept only provides transistors with reasonable terminal characteristics in the 1-µm and submicrometer range.     

1.0-µm n-well CMOS/bipolar technology

High-performance 1.0-µm n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-µm CMOS with a new "hot carrier resistant" self-defined polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors, it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n⁺-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n⁺-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

A 2-µm silicon-gate C-MOS/SOS technology

A 2-µm silicon gate deep-depletion C-MOS/SOS technology is described and characterized. The fabrication technology features all dry processing (ion milling and plasma etching) ion implanted source and drain, 2-µm features on all levels, phosphorous glass reflow for improved yield, and low-temperature processing (T ≤ 875°C). Characterization of the static electrical parameters as a function of channel length is presented. Circuit performance was characterized using a ring oscillator and a pattern generator. The ring oscillator exhibited stage delay as small as 220 ps at 5 V and an associated speed power product of less than 5 pJ. The pattern generator achieved an 80-MHz data rate. The potential of this technology for extension to submicrometer geometries was demonstrated by fabrication of discrete transistors with O.5-µm channel lengths.     

Electron beam direct writing technology applied to 512 kbit ROM with 1 µm geometry

A 512 kbit read-only memory (ROM) to store Chinese ideographs has been fabricated using variable-shaped electron beam and dry-etching lithography. 1.0-µm minimum line width was used to delineate device area spacings smaller than those obtained with conventional design rules using photoimaging techniques. SiO2, Si3N4, and polysilicon etchings were accomplished by reactive sputter techniques with CF4+ H2and CCl3F gases using negative electron beam resist PGMA and positive resist AZ-2400. Al etching was carried out by plasma with CCl4gas using negative electron beam resist NER-1. The alignment marks detectability and their locating accuracy were improved by properly using the basis arithmetic operations, subtraction and summation, in backscatter signal processings. 6.6 mm × 8.9 mm chip-by-chip alignment yielded about 0.2-µm level-to-level registration accuracy. Memory cell size and chip size are 5.2 µm × 8.4 µm and 6.6 mm × 8.9 mm, respectively; access time and power dissipation are 400 ns and 800 mW, respectively.     

Broadband modulation of 3-µm light by 10-µm light in p-germanium

High-power CO2laser radiation at 1045 cm^-1is shown to enhance the room temperature transmission of p-Ge in a spectral region extending at least from 3000 to 4000 cm^-1. The interaction arises from radiation-induced changes of the hole populations within the three valence bands. Ultrafast nonradiative relaxation is responsible for the very large interaction bandwidth observed and allows the prediction of a minimum switching time of 1 ps.     

A systems approach to 1-µm NMOS

In 1977, groups from diverse disciplines at Bell Labs were brought together for the first time, with the goal of applying a systems approach to high-performance NMOS technology. These groups, namely, solid-state physics, device design, materials, processing, and lithography found a symbiotic relationship that has produced not only NMOS devices with unparalleled performance, but also improved materials, processes, and tools-many of which are in production today.     

Mark detection technology in electron-beam direct writing

Monte Carlo (MC) simulation and experimental results are used to investigate mark detection technology in electron-beam (e-beam) direct writing for a 10-kV acceleration voltage. The simulation is based on a single scattering and a continuously slowing down approximation model, and also takes into account the Gaussian profile of the e-beam in order to calculate the backscattered electrons from the mark edges in detail. The simulation results for the alignment signals from a 66° tapered pedestal mark with a 1.1-µm-thickness resist are in good agreement with the experimental results. For the 10-keV e-beam, a location accuracy of about 0.15 µm (3 σ) is obtained by an alignment mark 2.3 µm high and 3.8 µm wide under the same conditions as the simulation. In this study, it is revealed that the simulation for the mark signal makes it possible to evaluate the accuracy of mark detection.     

Design methodology of a 1.2-µm double-level-metal CMOS technology

An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-µm gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.     

An experimental nanosecond Josephson 1K RAM using 5-µm Pb-alloy technology

A high-speed fully decoded Josephson 1K RAM has been designed and tested. Several bits of the 1K RAM were successfully operated with a typical read access time of 3.3 ns and associated power dissipation of 2.0 mW. The chip, containing about 10 000 Josephson junctions, was fabricated using 5-µm Pb-alloy technology, including a novel junction oxide barrier formation technique. A nondestructive readout (NDRO) Josephson ring cell operating with all current levels equal and an on-chip timing circuit for read/write operations were employed.     

Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's

The first device performance results are presented from experiments designed to assess FET technology feasibility in the 0.1-µm gate-length regime. Low-temperature device design considerations for these dimensions lead to a 0.15-V threshold and 0.6-V power supply, with a forward-biased substrate. Self-aligned and almost fully scaled devices and simple circuits were fabricated by direct-write electron-beam lithography at all levels, with gate lengths down to 0.07 µm. Measured device characteristics yielded over 750-mS/mm transconductance, which is the highest value obtained to date in Si FET's.     

1 µm MOSFET VLSI technology: Part VI—Electron-beam lithography

This paper discusses the fabrication of 1 µm minimum linewidth FET polysilicon-gate devices and circuits. These were designed for the tight dimensional ground rules (resolution, linewidth control, and overlay) achievable using direct wafer write scanning electron-beam lithography with individual chip registration. The present work focuses on vector-scan electron-beam technology and processing, while other papers in this series discuss other aspects of the work. Different types of 1 µm MOSFET chips were written on 57 mm Si wafers using a totally automated electron-beam system which performs table stepping, registration to fiducial marks, and pattern writing in a vector scan mode (on an individual shape basis) with control of exposure dose for individual shapes. The pattern data were prepared by batch processing which includes proximity correction as well as sorting of shapes to achieve data compaction and minimal distance between shapes. A novel two-layer positive resist system has been developed to achieve reproducible liftoff profiles over topography and better linewidth control. The final results presented here demonstrate that there are no fundamental barriers to the extension of this work to small dimensions.     

1 µm MOSFET VLSI technology: Part VIII—Radiation effects

In this paper the effect of electron-beam radiation on polysilicon-gate MOSFET's is examined. The irradiations were performed at 25 kV in a vector scan electron-beam lithography system at dosages typical of those used to expose electron-beam resists. Two types of studies are reported. In the first type, devices fabricated with optical lithography were exposed to blanket electron-beam radiation after fabrication. In the second, discrete devices from a test chip, fabricated entirely with electron-beam lithography, were used. It is shown that in addition to the threshold voltage shift, caused by the accumulation of radiation-induced positive charge in the gate oxides, these charged centers and additional uncharged (neutral) electron traps lead to an increase in the electron trapping in irradiated oxides. Temperatures above 550°C are shown to be required to anneal both the positive and neutral traps completely from the oxide underlying polysilicon after exposure to radiation. Annealing of the radiation-induced positive charge from the oxide is shown to depend on the metallurgy overlying the gate insulator during heat treatment. Annealing treatments which remove the charged centers from aluminum-gated MOS structures are demonstrated to leave small (about 5 × 10¹⁰cm^-2) but significant amounts of charge in certain polysilicon-gate structures. The dependence of positive and neutral trap densities on direct electron-beam exposure was studied in the range between 10 and 200 µC/cm². Studies on the electron-beam fabricated devices indicate that indirect exposure of the gate oxide by electrons scattered from the primary beam during lithography in areas away from the gate oxide is sufficient to cause appreciable damage. After postmetal annealing at 400° C for 20 min, the minimum residual charge density found in the electron-beam fabricated devices is 4 × 10¹⁰cm^-2.     

1 µm MOSFET VLSI technology: Part I—An overview

This paper attempts to provide a technical perspective for a 1 µm MOSFET VLSI technology described in the technical papers that follow. Highlights of various aspects of the technology development are discussed briefly. These include device design, circuit design, hot-electron effects, processing technology, electron-beam lithography, metal silicide interconnections and radiation effects.     

1-µm MOS process using anisotropic dry etching

Anisotropic and selective etching of silicon has been obtained using a planar-reactive sputter-etching system and CCl3F gas. The Si to SiO2etch-rate ratio was 5 : 1. This etch process in CCl3F was interpreted as mainly involving physical reaction as opposed to etching in SF6. The influence of reactive sputter etching on junction leakage and threshold voltage shift, in comparison with a conventional wetetch process, could not be observed in the electrical characteristics of polysilicon gate MOS devices. An all dry-etched MOS process, consisting of an anisotropic etching for Si3N4, polysilicon, SiO2, and aluminum, was applied to the fabrication of a 1-kbit static RAM with 1-µm minimum geometry. It was confirmed that this anisotropic etching technology was useful for very fine-geometry patterning and could be applied to a 1-µm MOSLSI manufacturing process.