Unterminated 4H-SiC Schottky barrier diodes with novel HfNxBy electrodes

4H-SiC Schottky barrier diodes (SBDs) were fabricated and characterized from room temperature to 573 K using HfN_xB_y as Schottky electrodes. The results are compared to SBDs fabricated using other electrodes that include Ni, Pt, Ti and Au. The Schottky barrier height Φ_b for as-deposited HfN_xB_y/n−/n+ diodes, determined from room temperature current-voltage characteristics, is 0.887 eV. This is lower than those of SBDs fabricated using other metals such as Au, where Φ_b is 1.79 eV. The HfN_xB_y/n−/n+ diodes studied have a much higher on-resistance R_on of around 38.24 mΩ-cm², which is about four times that of Au/n−/n+ diodes, due to the higher sheet resistance of the sputtered HfN_xB_y electrode layer. The barrier height Φ_b and ideality factor η of the HfN_xB_y/n−/n+ diodes remain almost unchanged after 400 and 750 °C anneal in N₂. This suggests excellent thermal and chemical stability of HfN_xB_y in contact with 4H-SiC.     

Roughness improvement of the CoSi2/Si-interface for an application as buried silicide

The material CoSi₂ is preferred for the fabrication of buried silicide films between silicon device layer and buried oxide of SOI substrates for BICMOS integrations. Such an application needs excellent quality of the interface between the silicide and the silicon device layer. Using the conventional cobalt salicide process the roughness and waviness of the interface is too large for a device application. In this presentation three technologies to improve the CoSi₂/Si-interface quality were characterized. Using the first technology a very thin single crystalline CoSi₂ film was fabricated on a silicon substrate. This film acts as initial layer to produce thicker single crystalline silicide films. By the second technology an interlayer between cobalt and the silicon substrate was used to mediate an epitaxial CoSi₂ growth. Different types and materials were tested. Using the third technique a sacrificial layer of polycrystalline silicon between cobalt and the silicon substrate was consumed during the silicidation reaction. This method gives the best results with interface roughness values of less than 1 nm. The interface roughness was measured after CoSi₂ removal using AFM. A possible epitaxial growth of the silicide films was investigated with XRD analysis. Cross sectional SEM images were prepared to analyze the interface waviness and the CoSi₂ structure.     

Direct measurement of interfacial structure in epitaxial Gd2O3 on GaAs (0 0 1) using scanning tunneling microscopy

The epitaxial growth of Gd₂O₃ on GaAs (0 0 1) has given a low interfacial density of states, resulting in the demonstration of the first inversion-channel GaAs metal-oxide-semiconductor field-effect transistor. Motivated by the significance of this discovery, in this work, cross-sectional scanning tunneling microscopy is employed herein to obtain precise structural and electronic information on these epitaxial films and interfaces. At the interface, the interfacial stacking of Gd₂O₃ films is directly correlated with the stacking sequence of the substrate GaAs. Additionally, from the local electronic states across the gate oxides, the spatial extent of the GaAs wavefunctions into the oxide dielectric may suggest a minimum Gd₂O₃ thickness to be of bulk properties.     

Temperature dependent current–voltage (I–V) characteristics of Au/n-Si (1 1 1) Schottky barrier diodes with PVA(Ni,Zn-doped) interfacial layer

Current–voltage (I–V) characteristics of Au/PVA/n-Si (1 1 1) Schottky barrier diodes (SBDs) have been investigated in the temperature range 80–400 K. Here, polyvinyl alcohol (PVA) has been used as interfacial layer between metal and semiconductor layers. The zero-bias barrier height (Φ_B0) and ideality factor (n) determined from the forward bias I–V characteristics were found strongly dependent on temperature. The forward bias semi-logarithmic I–V curves for different temperatures have an almost common cross-point at a certain bias voltage. The values of Φ_B0 increase with the increasing temperature whereas those of n decrease. Therefore, we have attempted to draw Φ_B0 vs. q/2kT plot in order to obtain evidence of a Gaussian distribution (GD) of the barrier heights (BHs). The mean value of BH and standard deviation (σ₀) were found to be 0.974 eV and 0.101 V from this plot, respectively. Thus, the slope and intercept of modified vs. q/kT plot give the values of and Richardson constant (A^?) as 0.966 eV and 118.75 A/cm²K², respectively, without using the temperature coefficient of the BH. This value of A^* 118.75 A/cm²K² is very close to the theoretical value of 120 A/cm²K² for n-type Si. Hence, it has been concluded that the temperature dependence of the forward I–V characteristics of Au/PVA/n-Si (1 1 1) SBDs can be successfully explained on the basis of the Thermionic Emission (TE) theory with a GD of the BHs at Au/n-Si interface.     

On the temperature dependence of series resistance and interface states in Al/SiO2/p-Si (MIS) Schottky diodes

The capacitance-voltage-temperature (C-V-T) and conductance-voltage-temperature (G/w-V-T) characteristics of metal-semiconductor (Al/p-Si) Schottky diodes with thermal growth interfacial layer were investigated by considering series resistance effect in the wide temperature range (80-400 K). It is found that in the presence of series resistance, the forward bias C-V plots exhibit a peak, and experimentally shows that the peak positions shift towards higher positive voltages with increasing temperature, and the peak value of the capacitance has a maximum at 80 K. The C-V and (G/w-V) characteristics confirm that the N_ss and R_s of the diode are important parameters that strongly influence the electric parameters in (Al/SiO₂/p-Si) MIS Schottky diodes. The crossing of the G/w-V curves appears as an abnormality when seen with respect to the conventional behaviour of the ideal MS or MIS Schottky diode. It is thought that the presence of a series resistance keeps this intersection hidden and unobservable in homogeneous Schottky diodes, but it appears in the case of inhomogeneous Schottky diode. In addition, the high frequency (C_m) and conductance (G_m/w) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance.     

石墨烯掺杂Cs2CO3作为高效电子注入层的OLEDs性能研究

研制了石墨烯掺杂Cs₂CO₃(Cs₂CO₃:Graphe ne )作为高效电子注入层、结构为ITO/N,N′-bis-(1-naphthyl) -N,N′-diphenyl-1,1′-biphenyl-4,4′-diamine (NPB)(50 nm)/tris-(8-hydroxy quinoline)-aluminum Alq₃(80 nm)/Cs₂CO₃:Gra phene (mss 20% 1nm)/Al(120 nm)的OLEDs。将其与标准器件ITO/NPB(50 nm)/Alq₃(80 n m)/LiF(0.5 nm)/Al(120 nm)作性能比较,研究石墨烯掺杂在Cs₂CO₃中作为电子注入层 对 OLEDs性能的影响。结果表明,基于Cs₂CO₃:Graphene结构作为电子注入层的器 件效率要高于LiF作为电子注入层的器件,其最大电流效率达到2.02 cd/A, 是标准器件的2.59倍;亮度也高于LiF作为电子注入层的器件,在10 V时达 到最大值7690cd/m²,是标准器件最大亮度 的2.07倍。性能得到提高的主要机理是由于Cs₂CO₃:Graphene的引入提高了电子注入效率。     

Epitaxial growth of Dy2O3 thin films on epitaxial Dy-germanide films on Ge(0 0 1) substrates

Ultra-thin films of Dy are grown on Ge(0 0 1) substrates by molecular beam deposition near room temperature and immediately annealed for solid phase epitaxy at higher temperatures, leading to the formation of DyGe_x films. Thin films of Dy₂O₃ are grown on the DyGe_x film on Ge(0 0 1) substrates by molecular beam epitaxy. Streaky reflection high energy electron diffraction (RHEED) patterns reveal that epitaxial DyGe_x films grow on Ge(0 0 1) substrates with flat surfaces. X-ray diffraction (XRD) spectrum suggests the growth of an orthorhombic phase of DyGe_x films with (0 0 1) orientations. After the growth of Dy₂O₃ films, there is a change in RHEED patterns to spotty features, revealing the growth of 3D crystalline islands. XRD spectrum shows the presence of a cubic phase with (1 0 0) and (1 1 1) orientations. Atomic force microscopy image shows that the surface morphology of Dy₂O₃ films is smooth with a root mean square roughness of 10 Å.     

Towards barrier height modulation in HfO2/TiN by oxygen scavenging - Dielectric defects or metal induced gap states?

The band alignment between a dielectric and a metal gate is crucial as it controls the MOSFET threshold voltage as well as the leakage in metal-insulator-metal (MIM) structure. In the ideal Schottky-Mott model the barrier height should be controlled only by the workfunction and the electron affinity of the materials considered. However, this seems the case only for few insulating materials other than SiO₂ (i.e., Fermi level pinning).The most popular explanation invokes metal-induced gap states (MIGS), where electron states from the bulk of a metal tails into the insulator. The MIGS hypothesis explains a rather large series of experimental results and, importantly, predicts that the MI barrier height will mostly be controlled by the energy distribution of electron states in the bulk of the contacting metal and dielectric. In this paper, we analyze the band alignment of contacting metal (TiN) and dielectric (HfO₂) by using internal photoemission. It will be shown that defects in the dielectric rather than MIGS control the barrier height.     

Effective formation of interface controlled Y2O3 thin film on Si(1 0 0) in a metal-(ferroelectric)-insulator-semiconductor structure

Yttrium was deposited on the chemical oxide of Si and annealed under vacuum to control the interface for the formation of Y₂O₃ as an insulating barrier to construct a metal-ferroelectric-insulator-semiconductor structure. Two different pre-annealing temperatures of 600 and 700 °C were chosen to investigate the effect of the interface state formed after the pre-annealing step on the successive formation of Y₂O₃ insulator and Nd₂Ti₂O₇ (NTO) ferroelectric layer through annealing under an oxygen atmosphere at 800 °C. Pre-anneal treatments of Y-metal/chemical-SiO₂/Si at 600 and 700 °C induced a formation of Y₂O₃ and Y-silicate, respectively. The difference in the pre-anneal temperature induced almost no change in the electrical properties of the Y₂O₃/interface/Si system, but degraded properties were observed in the NTO/Y₂O₃/interface/Si system pre-annealed at 600 °C when compared with the sample pre-annealed at 700 °C. C-V characteristics of the NTO/Y₂O₃/Si structured system showed a clockwise direction of hysteresis, and this gap could be used as a memory window for a ferroelectric-gate. A smaller hysteric gap and electrical breakdown values were observed in the NTO/Y₂O₃/Si system pre-annealed at 600 °C, and this was due to an unintentional distribution of the applied field from the presence of an interfacial layer containing Y-silicate and SiO₂ phases.     

Influence of the oxidation temperature on the non-trigonal Ge dangling bonds at the (1 0 0)Ge/GeO2 interface

GeO₂ was proposed as valuable passivation layer at the surface with Ge to integrate oxide with high dielectric constant in Ge-based logic devices. Hence, the identification of the defects present at different Ge/GeO₂ interfaces becomes a mandatory issue to predict the electrical features of devices based on such materials. High sensitive electrically detected magnetic resonance measurements were performed to study the microstructure of defects occurring at such an interface. The influence of the oxidation temperature on the electrically active paramagnetic traps was investigated.     

Study of thick film Ni(1−x)CoxMn2O4,(0?x?1) using overlay technique on thick film microstrip ring resonator

The effect of thick film Ni_(1−x)Co_xMn₂O₄ in-touch overlay on the X band resonance characteristics of thick film microstrip ring resonator is studied. The thick film overlay decreases the resonance frequency and increases the peak output. From the frequency shift the dielectric constant of the thick film Ni_(1−x)Co_xMn₂O₄ has been calculated. For the first time Ag thick film microstrip ring resonator has been used to study thick film Ni_(1−x)Co_xMn₂O₄ in the X band.     

Effect of titanium dioxide (TiO2) seed layer on the phase composition of 0.7Pb (Mg1/3Nb2/3)O3-0.3PbTiO3 film prepared by pulsed laser deposition

Lead-magnesium niobate-lead titanate (PMN-PT) thin films with and without the TiO₂ seed layer were deposited on Pt/Ti/SiO₂/Si substrates through pulsed laser deposition. The study aimed to characterize the effect of the TiO₂ seed layer on the phase composition and properties of PMN-PT film. Without the TiO₂ seed layer, the pure perovskite phase could be obtained in the thinner PMN-PT film while with the TiO₂ seed layer, the pure perovskite phase was formed in the thicker PMN-PT film. The ferroelectric properties of PMN-PT films with the TiO₂ seed layer were exhibited. As a result, the maximum amount of remnant polarization reached the amount of 32 μC/cm² for the PMN-PT thin film with the TiO₂ seed layer.     

Structural and electrical properties of Er-doped HfO2 and of its interface with Ge (0 0 1)

Er-doped HfO₂ thin films with Er content ranging from 0% to 15% are deposited by atomic layer deposition on native oxide free Ge(001). The crystallographic phase is investigated by X-ray diffraction and is found to depend on the Er%. The cubic fluorite structure develops on Ge for Er% as low as 4% and is stable after annealing at 400 °C in N₂. Microstrain increases with increasing the Er content within the fluorite structure. Time of flight secondary ion mass and electron energy loss spectroscopy evidence a Ge diffusion from the substrate that results in the formation of a Ge-rich interfacial region which does not present a structural discontinuity with the oxide. The diffusion of Ge is enhanced by the annealing and causes a reordering of the crystal lattice. In annealed films the interface defect density measured by low temperature conductance measurements is found to decrease with decreasing the Er content.     

Fabrication of high-Ge-fraction strained Si1−xGex/Si hole resonant tunneling diode using low-temperature Si2H6 reaction for nanometer-order ultrathin Si barriers

Low-temperature Si barrier growth with atomically flat heterointerfaces was investigated in order to improve negative differential conductance (NDC) characteristics of high-Ge-fraction strained Si_1−xGe_x/Si hole resonant tunneling diode with nanometer-order thick strained Si_1−xGe_x and unstrained Si layers. Especially to suppress the roughness generation at heterointerfaces for higher Ge fraction, Si barriers were deposited using Si₂H₆ reaction at a lower temperature of 400 °C instead of SiH₄ reaction at 500 °C after the Si_0.42Ge_0.58 growth. NDC characteristics show that difference between peak and valley currents is effectively enhanced at 11-295 K by using Si₂H₆ at 400 °C, compared with that using SiH₄ at 500 °C. Non-thermal leakage current at lower temperatures below 100 K tends to increase with decrease of Si barrier thickness. Additionally, thermionic-emission dominant characteristics at higher temperatures above 100 K suggests a possibility that introduction of larger barrier height (i.e. larger band discontinuity) enhances the NDC at room temperature by suppression of thermionic-emission current.     

微波法制备高活性H1-xSr2Nb3-xMoxO10 (x = 0, 0.05, 0.1, 0.15 and 0.2) 光催化剂

通过微波辅助法制备出高活性H1-xSr2Nb3-xMoxO10光催化材料,制备过程和时间均被大大缩短。采用X射线粉末衍射（XRD）、扫描电镜（SEM）、紫外-可见吸收吸收光谱（UV-Vis DRS）等表征其材料性能。考察了催化材料在40W汞灯辐照下催化降解甲基橙的催化性能。实验结果表明,MoO3的掺入量为15%（摩尔分数）时,材料的光催化性能最优。