Electrical Analyses of Germanium MIS Structure and Spectroscopic Measurement of the Interface Trap Density in an Insulator/Germanium Interface at Room Temperature

In this paper, we present an equivalent circuit model of a germanium (Ge) MIS structure that is biased in the inversion region, which includes the effects of the high intrinsic carrier density and high diffusion-limited conductance of the Ge substrate at room temperature. The model can successfully express the gate bias and frequency dependences of the capacitance characteristics that are specific to the Ge MIS capacitor. Moreover, it will be shown that the interface trap density and its gate bias dependence in the inversion region can be spectroscopically determined from the gate bias and measurement frequency dependences of the equivalent parallel conductance of the Ge surface.     

High-accuracy extraction of buried-channel m.o.s. transistor threshold voltages

A new experimental method is presented, which yields threshold voltages and their dependence on substrate bias for buried-channel, usually ion-implanted m.o.s. transistors with an accuracy typically < 10 mV. The extraction follows from two current measurements in the linear region, one as a function of gate voltage and fixed substrate bias, the other as a function of substrate bias roughly at the flat-band voltage.     

Correlation between substrate and gate currents in MOSFET's

A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.     

Influence of the surface and the episubstrate interface on the drain current drift of GaAs MESFET's

Long-term drift of GaAs MESFET's under gate bias and under substrate bias was extensively investigated to discover whether the dominant cause of the phenomenon is due to the surface or the epi-substrate interface. It was found that the activation energy of the ordinary drain current drift under gate bias scatters greatly from 0.16 eV to 0.8 eV, depending on the amount of the drift, whereas the activation energy of the drift due to substrate bias is always constant at 0.82 eV. Ordinary drift under gate bias and its activation energy are greatly influenced by surface conditions, but drift due to substrate bias is not so influenced. Changes of the high frequency parameters are also different for each case. These results indicate that the drift in GaAs MESFET's performance, which has often been observed in the past, is dominated by surface conditions, probably mobile charges on the surface.     

背栅应力对LOCOS隔离的SOI器件背栅阈值电压的影响

LOCOS隔离的SOI器件的性能强烈依赖于其背栅特性,而背栅应力会影响到背栅的特性。常温下在SOI器件的背栅上施加大电压并持续30秒以上可以显著改变背栅的阈值电压。这种改变是稳定的和时不变的。对NMOS加正的背栅压和对PMOS加负的背栅压都可以提高其背栅阈值电压。实验结果表明沿着硅岛的边缘有一条从源到漏的寄生漏电通道,而且将栅,源,漏接地并在背栅上加大的偏压可以强烈影响漏电通道。因此我们可以得到结论,背栅应力会影响与漏电流直接相关的背栅阈值电压。     

Effect of reverse substrate bias on ultra-thin gate oxide n-MOSFET degradation under different stress modes

Degradation of ultra-thin gate oxide n-MOSFET with halo structure is studied under different stress modes with the increase of reverse substrate bias. The variation of device degradation is characterized by monitoring the substrate current during stress. When the gate voltage is smaller than a critical value, the device degradation first decreases and then increases with the increase of reverse substrate voltage; otherwise, the device degradation increases continually. The critical gate voltage can be determined by measuring the substrate current variation with the increase of reverse substrate voltage.     

Evidence for bulk trap generation during NBTI phenomenon in pMOSFETs with ultrathin SiON gate dielectrics

Negative bias temperature instability (NBTI) of pMOSFETs with direct-tunneling SiON gate dielectrics was studied in detail. By investigating the effects of applying positive gate bias on pMOSFETs after exposure to NBT stress, the generation of bulk charge traps in the gate dielectrics during NBTI was clearly demonstrated. In particular, it was found that a positive charge generated by negative bias temperature stress (NBT stress) can be neutralized and that the neutralized site can return to the positive state. We consider that the bulk trap is due to hydrogen atoms released from the interface between the SiON gate dielectric and the Si substrate (and this is what has conventionally been considered a positive fixed charge). Moreover, the bulk trap generation was shown to give rise to stress-induced leakage current.     

Substrate bias and operating temperature effects on the performance of Schottky-barrier SOI nMOSFETs

The substrate bias and operating temperature effects on the performance of erbium-silicided Schottky-barrier SOI nMOSFETs have been studied. The temperature dependence of the threshold voltage, the current ratio of I_ON/I_MIN, and the subthreshold swing has been investigated. From temperature dependence of the drain current, it is confirmed that the carrier transport mechanism changes from thermionic emission and tunneling at low gate voltage to drift-diffusion at the high gate voltage. By applying substrate bias voltage, the I_ON/I_MIN ratio and subthreshold swing can be improved. By investigating the substrate bias dependence of I_ON/I_MIN ratio, subthreshold swing, and DIBL, the optimum substrate bias voltage is suggested.     

一种基于栅交叉耦合连接的电荷泵设计

对于普通CMOS工艺中容易产生的衬底偏置效应,基于dickson电荷泵原理,本文采用了一种栅交叉耦合的方式来选择相应PMOS管的衬底电压,从而消除了衬底偏置效应的影响。再结合相应的电路,诸如时钟控制电路和整流电路等,为EEPROM提供稳定擦写电流。该设计能有效消除衬底偏置效应影响,更好的提高电荷泵工作效率。     

Noise Reduction in CMOS Circuits Through Switched Gate and Forward Substrate Bias

A new concept of noise reduction in CMOS circuits is presented taking advantage of a strong reduction of MOSFET low-frequency noise occurring under switched gate bias conditions and forward substrate bias. The effect of forward substrate bias on noise reduction is significantly larger in switched compared to constant gate bias conditions. Experimental results reveal that forward substrate bias is most effective when applied during the off-state of the transistor. A bias scheme adopting forward substrate bias only during the transistor off-state is suggested by the measurement results of transconductance efficiency ${rm gm}/{rm Id}$ and intrinsic voltage gain ${rm gm}/{rm gds}$ showing that these figures of merit are degraded when a forward substrate bias is applied during the on-state. As a first example exploiting the found noise reduction on circuit level, a 14 GHz pMOS VCO is presented. Our results show a significant reduction of close to carrier phase noise when a forward substrate bias is applied to the MOSFETs providing the negative conductance stage for the oscillation of the VCO. The outlined principles can be extended to other circuits and motivate new topologies and biasing schemes for analog and radio frequency CMOS circuits.      

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

Leakage currents of m.o.s. devices under surface-depletion conditions

It is found that the drain current of m.o.s.t. devices depends exponentially on gate voltage over a wide range of current when the surface of the device is depleted. An explanation of this effect is given. The results show that low-current measurements of this type for a variety of substrate bias conditions can provide information on the density of midgap states and the amount of impurity segregation in practical structures.     

Negative-gate to substrate erase transient simulation for flash memory

We present a detailed and accurate physics based transient simulation for modeling flash memory erasing. Typical cells are erased by moving electrons from the floating gate to the drain, source or substrate. This paper addresses substrate erasing using a negative gate bias voltage based on the approximate solution to Poisson’s equation. Substrate erasing using a negative gate bias voltage is one of the more prevalent ways to erase flash memory in currently available consumer products. Many papers have been published on this topic but rarely present detailed derivations and none using this exact set of equations to model this erasing process.     

Tunneling in field induced diode in indium antimonide

Tunneling in the forward bias polarity of a field induced diode in indium antimonide is treated theoretically and experimentally. The theory leads to tunneling current-voltage characteristics with a region of negative resistance which are dependent upon the various parameters of the device, such as the gate voltage, substrate acceptor concentration and oxide thickness. A three-terminal device in which the gate voltage controls the tunneling I–V characteristics can thus be realized.Measurements were performed on an experimental device obtained by diffusion of cadmium into N-type InSb semiconductor. A chemically deposited SiO₂ layer was used to isolate the evaporated CrAu gate electrode from the substrate. Deviations from theory are shown to result from the two-dimensional character of the device.     

The effect of substrate bias on hot-carrier damage in NMOS devices

Hot-carrier stressing carried out as a function of substrate voltage on 2-μm NMOS devices under bias conditions V_d =8 V and V_g=5.5 V is discussed. The time power-law dependence of stressing changes as a function of substrate bias (V_b), having a power-law gradient of 0.5 for V_b=0 V and 0.3 for V_b=-9 V. Investigation of the type of damage resulting from stressing shows that at V_b=0 V, interface state generation results, while at V_b=-9 V, the damage is mostly by charge trapping. Measurements of the gate current under these two substrate bias conditions show that the gate electron current increases by over two orders of magnitude upon application of a strong back bias. It is suggested that the electron trapping arises from this enhanced gate electron current under large substrate voltage conditions     

Generation of interface states by hot hole injection in MOSFET's

The emission of hot electrons and hot holes from n-channel MOSFET's into the gate oxide is investigated as a function of the gate bias for a given lateral electric field. The resulting electron gate current as well as the substrate current are analyzed for both the saturation and the linear regime of the transistor. In the saturation regime, a remarkable increase of interface states occurs which can be correlated with the hole generation due to avalanche multiplication in the high-field region. In this case, the electric field normal to the Si-SiO2interface near the drain aids in the injection of hot holes along the channel which initiates acceptor-type interface states. In the linear operation regime, however, no pronounced generation of interface states can be detected.     

Reliability of ultrathin silicon dioxide under combined substratehot-electron and constant voltage tunneling stress

An experimental investigation of breakdown and defect generation under combined substrate hot-electron and tunneling electrical stress of silicon oxide ranging in thickness from 2.0 nm to 3.5 nm is reported. Using independent control of the gate current for a given substrate and gate bias, the time-to-breakdown of ultrathin silicon dioxide under substrate hot-electron stress is observed to be inversely proportional to the gate current density. The thickness dependence (2.0 nm to 3.5 nm) of substrate hot-electron reliability is reported and shown to be similar to constant voltage tunneling stress. The build-up of defects measured using stress-induced-leakage-current and charge-pumping for both tunneling and substrate hot-electron stress is reported. Based on these and previous results, a model is proposed to explain the time-to-breakdown behavior of ultrathin oxide under simultaneous tunneling and substrate hot-electron stress. The results and model provide a coherent understanding for describing the reliability of ultrathin SiO₂ under combined substrate hot-electron injection and constant voltage tunneling stress     

Sudden failures associated with the gate oxide of CMOS transistors

Sudden failures appearing during static gate bias — temperature aging of CMOS transistors are investigated in this paper. Shorts between the gate and substrate as well as open gate circuits are found to be failure modes appearing during testing. The subsequent failure analysis reveals that the reaction between the aluminium and gate oxide is the failure mechanism, while defects in P⁺-diffusion regions (which are transferred onto the gate oxide) are the cause of the observed failures.     

On the electrical monitor for device degradation in the CHISEL stress regime

This paper reports a complete characterization of hot carrier-induced degradation in the CHannel Initiated Secondary ELectron (CHISEL) regime covering a large set of different stress bias conditions. Using several physical and electrical parameters, our results demonstrate that in the CHISEL regime, differently from the channel hot electrons case, the device degradation is univocally related to the gate current independently of the drain, source, substrate bias, and of the oxide electric field. The gate current is thus identified as the electrical monitor for device degradation in the CHISEL stress conditions.     

Temperature dependence of hot carrier induced MOSFET degradation at low gate bias

This paper reports a new experimental finding on the temperature dependence of the substrate current and hot carrier induced device degradation at low gate bias. It has been found that the substrate current increases and the drain current degradation is more significant for high operating temperature at low gate bias. It has been observed that the hot carrier induced performance degradation of a latch-type input buffer increases at the elevated temperature.