Development of packaging technologies for microsystems

［1］ESASHI M. MEMS packaging and assembly[A]. Pacific Rim Workshop on Transducers and Micro/Nano Technology[C]. Xiamen, China, 2002, 1-10. ［2］TAKIZAWA T, YAMAMOTO S, ITOI K, et al. Conductive interconnection through thick silicon substrates for 3D packaging[A]. MEMS 2002 Technical Digest of 15th IEEE Int Conf on Micro Electro Mechanical Systems[C]. Las Vegas, USA, 388-391. ［3］WANG Z.F, CAO W, ARULVANAN P, et al. Packaging of a fiber optical MEMS switch[A]. Proc. of 4th Electronics Packaging Technology Conf[C]. Singapore, 2002, 96-100. ［4］NAJAFI K. Micropackaging technologies for integrated Microsystems[A]. Proc of SPIE[C]. San Jose, CA. USA, 2003,Vol. 4979, 1-19.     

Development of packaging technologies for microsystems

It is well known that packaging plays a very important role in developing microsystems. Packaging accounts for about 60%～80% of cost and function of a microsystem. Package is required to provide mechanical protection, media separation or coupling, signal conditioning, etc.     

3-D packaging methodologies for microsystems

Issues associated with the packaging of microsystems in plastic and three-dimensional (3-D) body styles are discussed. The integration of a microsystem incorporating a micromachined silicon membrane pump, into a 3-D plastic encapsulated vertical multichip module package (MCM-V) is described. Finite element techniques are used to analyze the encapsulation stress in the structure of the package. Cracks develop in the chip carrier due to thermomechanical stress. Based on the results of a finite element design study, the structures of the chip carriers are modified to reduce their risk of cracking. Alternative low stress 3-D packaging methodologies based on chip on board and plastic leadless chip carriers are discussed.     

Reliability of industrial packaging for microsystems

Packaging concepts for silicon-based micromachined sensors exposed to harsh environments are explored. By exposing the sensors directly to the media and applying protection at the wafer level the packaging and assembly will be simplified as compared to conventional methods of fabrication.Protective coatings of amorphous silicon carbide and tantalum oxide are suitable candidates with etch rates below 0.1 Å/h in aqueous solutions with pH 11 at temperatures up to 140°C. Si-Ta-N films exhibit etch rates around 1 Å/h. Parylene C coatings did not etch but peeled off after extended exposure times at elevated temperatures. The best diamond-like carbon films we tested did not etch, but delaminated due to local penetration of the etchants.Several glue types were investigated for chip mounting of the sensors. Hard epoxies, such as Epotek H77, on the one hand exhibit high bond strength and least degradation and leakage, but on the other hand introduce large sensor output drift with temperature changes. Softening of the Epo-tek H77 was observed at 70°C.An industrially attractive thin-film anodic silicon-to-silicon wafer bonding process was developed. Glass layers are deposited at 20 nm/s (1.2 μm/min) by electron-beam evaporation and bond strengths in excess of 25 N/mm² are obtained for bonding temperatures higher than 300°C.Through-hole electrical feedthroughs with a minimum line width of 20μm and a density of 250 wires per cm were obtained by applying electro-depositable photo-resist. Hermetically sealed feedthroughs were obtained using glass frits, which withstand pressures of 4000 bar.     

Thermal issues in microsystems packaging

Miniaturization of electronic/mechanical systems is achieved by packing different functional components into tight space. The heat transfer analysis for such systems has to deal with geometrically complex heat transfer paths, and it needs to be done quickly in response to every design alteration. This paper proposes a concept that aims at reduction of analysis load on the packaging designer. The proposed scheme is composed of two major steps. First, a computer program "configuration generator" is used to generate possible geometric configurations of heat transfer paths in a systematic manner. Second, temperature solutions for these configurations are compressed into "fast estimate" formulas that free the packaging designer from the need to perform involved heat transfer analysis. This approach is illustrated using a topic of heat spreading on the planar substrate as an example. Miniaturization of systems also raises another issue for the thermal design; that is the coupling between the system configuration and the overall heat dissipation to the environment. A model situation is considered where heat diffuses from a zone on the system shell and to the environment by natural convection and radiation. In the parametric domain spanned by the thermal conductivity of shell material and the system's characteristic length there is a zone where the system-level heat transfer is sensitive to the system's configuration. Such characteristic length is around 1 cm for systems encapsulated in plastics, 3-10 cm for those in ceramic and alloy shells, and 10-40 cm in copper or aluminum clad systems.     

An AS-level overlay network for IP traceback

Distributed denial of service attacks currently represent a serious threat to the appropriate operation of Internet services. To deal with this threat, we propose an overlay network that provides an IP-traceback scheme at the level of autonomous systems. Our proposed autonomous system-level IP-traceback system contrasts with previous works because it does not require a priori knowledge of the network topology and allows single-packet traceback and incremental deployment. Our first contribution is a new extension to the Border Gateway Protocol update-message community attribute that enables information to be passed across autonomous systems that are not necessarily involved in the overlay network. The second contribution is a new sequence-marking process to remove ambiguities in the traceback path. Two different strategies for incremental system deployment are investigated and evaluated. We show that strategic placement of the system on highly connected autonomous systems produces relevant results for IP traceback even if the system operates on only a few autonomous systems. The main conclusion is that the proposed system is suitable for large-scale networks such as the Internet because it provides efficient traceback and allows incremental deployment.     

Chemical microsensors for measurement microsystems

Microsensors for chemical measurement microsystems exploit a wide variety of chemical and physical transduction principles and a correspondingly wide variety of practical electrical and electronic implementation technologies. To keep this article's scope manageable, the devices discussed in detail are limited to specialized electrical circuit components - resistors and capacitors - whose parametric values depend on their chemical environment; furthermore, the discussion and examples focus on chemical sensors for gas phase versus liquid phase or biological environments. The article looked in detail at chemiresistors, resistors fabricated of materials whose resistivity changes dramatically with their atmospheric environment, and humidity sensors, which are especially interesting because it is possible to compare commonly available devices based on resistive, capacitive, and thermal conductivity principles. Since many of the most practically important of these sensors are currently at a stage of their miniaturization path that makes it more accurate to call them "minisensors" than "microsensors," devices at this scale are also discussed.     

An overlay architecture for managing lightpaths in optically routed networks

Existing solutions for optically routed networks (ORNs) lack certain key management functions available to electronically routed networks. In particular, ORNs have extremely limited capabilities to trace the path of an optical signal through the network. In this paper, we present a method for embedding path identification and other management information into the transport stream in such a way that the management information can be read by a low-bandwidth, low-cost receiver, without having to terminate or decode the full-rate payload stream. We outline a method for embedding such management information, using a digital coding process at the transmitter, and two distinct digital decoding processes for receiving the management and payload data streams, respectively. Feasibility of the method is demonstrated by computing the bit-error performance of example codes under realistic operating conditions, including multiple management streams in multiwavelength systems.     

Packaging of microsystems for harsh environments

Micromachined devices have great potential but using these fragile structures in aggressive environments can pose a challenge. Mechanical shock, chemical exposure, and temperature extremes can damage delicate microsystems. Also, substantial effort is often put forth to develop a device concept only to find later that the device is difficult or expensive to package suitably in a consumer or automotive environment. The cost of materials, processing, and manufacturing make the sensor or actuator device impractical for some applications. A successful MEMS device manages the proper balance for its application between the high device performance and low unit cost. The packaging of MEMS begins with a consideration of the microsystem's environment. An aerospace, automotive, or industrial component could be subjected to temperatures ranging from -40°C to over 150°C. Mechanical shocks in the 10 g to +500 g range can be experienced which can fracture poorly designed silicon beams. Chemical exposure, which can corrode silicon, or the metal interconnection lines on silicon, and shift electrical parameters, are challenges that must be overcome in these applications     

Distributed dynamic channel assignment for in-building microsystems

Several fully distributed measurement-based dynamic channel assignment (DCA) schemes are compared for the large-scale uncoordinated deployment of in-building microsystems: DCA based on the first quality of service (DCA-FQZOS) channel selection, DCA based on best QOS channel selection (DCA-BQOS), DCA-WO (channel) (DCA with weighted channel orderings), and DCA-WO (carrier) (DCA with weighted carrier orderings). The DCA schemes are evaluated in terms of their blocking probabilities and algorithm processing delay. We also investigate how the DCA performance depends on the number of radio ports per base station, asynchronous time-slot transmission, and propagation conditions. Of the proposed DCA schemes, the simulation results show that there are tradeoffs in selecting a DCA scheme. Finally, a new scheme called DCA with limited selection weighted ordering (DCA-LSWO) is proposed that combines some previous strategies to improve performance for in-building microsystems     

In-plane biocompatible microfluidic interconnects for implantable microsystems

Small mammals, particularly mice, are very useful animal models for biomedical research. Extremely small anatomical dimensions, however, make design of implantable microsystems quite challenging. A method for coupling external fluidic systems to microfluidic channels via in-plane interconnects is presented. Capillary tubing is inserted into channels etched in the surface of a Si wafer with a seal created by Parylene-C deposition. Prediction of Parylene-C deposition into tapered channels based on Knudsen diffusion and deposition characterizations allows for design optimization. Low-volume interconnects using biocompatible, chemical resistant materials have been demonstrated and shown to withstand pressure as high as 827 kPa (120 psi) with an average pull test strength of 2.9 N. Each interconnect consumes less than 0.018 mm3 (18 nL) of volume. The low added volume makes this an ideal interconnect technology for medical applications where implant volume is critical.     

Ferroelectric thin and thick films for microsystems

Ferroelectric oxide thin and thick films are interesting materials for microsystem devices because of their wide range of useful properties, particularly the pyroelectric and piezoelectric effects. The ability to grow these films at relatively low temperatures onto a wide range of substrates, including silicon, is especially important. This paper discusses the use of CSD processes to grow high-quality ferroelectric PZT30/70 thin films onto platinised silicon substrates at low temperatures (from 400°C to 575°C), with particular reference to their use in pyroelectric infra-red detector arrays and other MEMS devices. The various factors important to the use of sol–gel processes are discussed, including mechanisms for sol ageing and for perovskite nucleation and growth. The latter is interesting, involving the formation of a transient Pt₃Pb phase that acts as a nucleation layer for the templated growth of the PZT layer. The effects of Mn doping on the resulting materials properties are discussed. It leads to a strong asymmetry in the ferroelectric hysteresis behaviour as well as improved pyroelectric performance. Techniques for increasing the thickness of sol–gel layers, and the reasons for the appearance of nanoporosity, are reviewed. Finally, the use of sol–gel techniques for the fabrication of composite piezoelectric ceramic thick films (10–20 μm thick) at low temperatures (710°C) are discussed.     

Silicon on sapphire CMOS for optoelectronic microsystems

we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that one faces when employing bulk silicon CMOS technologies. In the bulk silicon CMOS processes that are used for high-speed interface electronics the substrate is absorbing at both 850 nm and 980 nm wavelengths, necessitating complex and expensive integration procedures such as VCSEL substrate removal to enable the implementation of optical vias through the substrate. Working together, the optical transparency of the sapphire substrate, its superb thermal conductivity and the excellent high speed device characteristics of silicon-on-sapphire CMOS circuits make this technology an excellent choice for cost effective optoelectronic Die-AS-Package (DASP) systems and for implementing optical interconnects for high performance computer architectures. What is perhaps even more important, packaging and input/output interface issues can now be addressed at the CMOS wafer fabrication level where input/output structures can be accurately defined, optimized and processed using lithographic techniques, eliminating problematic die post-processing and packaging-related optical alignment issues     

Differential read-out architecture for CMOS ISFET microsystems

The operation of a pH (H/sup +/ ion concentration) sensitive ion-sensitive field-effect transistor (ISFET) microsystem with a sensitivity of 40-45 mV/pH is demonstrated. This system has two identical ISFETs as the inputs to a pair of ISFET operational transconductance amplifiers (IOTAs) arranged in a novel differential architecture. The IOTAs have different sized p-MOSFET load transistors that enable pH sensitive operation without any post-fabrication processing or material deposition. The CMOS ISFET chip is fabricated in an unmodified 1.5 /spl mu/m commercial process.     

一种改进的快速嵌入式字符识别方法

针对手持式字符识别系统开发中系统对实时性要求较高、系统资源有限以及传统的支持向量机(SVM)分类方法难以同时满足识别率和识别速度的缺点,提出一种快速的SVM(FCSVM)分类算法。对支持向量集采用变换的方式,用少量的支持向量代替全部支持向量进行分类计算,在保证不损失分类精度的前提下使得分类速度较传统SVM算法有较大提高。实验结果表明,FCSVM算法较大幅度地减少了计算复杂度,提高了分类速度,尤其在嵌入式系统中效果更加明显。     

High-performance large-inductance embedded inductors in thin array plastic packaging (TAPP) for RF system-in-package applications

We report the first demonstration of high-Q embedded inductors fabricated using a thin-array-plastic-packaging (TAPP) technology. The TAPP technology provides a platform that integrates digital, analog, RF integrated circuits, along with high-performance passive components for system-in-package implementation. Embedded inductors ranging from 14 to 300 nH were fabricated. All the inductors with inductance less than 100 nH exhibit self-resonant frequency above 1 GHz. For a 14-nH inductor, Q factor of 35 was achieved at 1.6 GHz and the self-resonance frequency was measured at 6.15 GHz.     

A self-oscillating detuning-insensitive class-E transmitter for implantable microsystems

This paper describes a low-cost, self-oscillating, detuning-in-sensitive, class-E driver for transcutaneous power and data transmission to implantable microsystems. A voltage feedback scheme using a fast comparator for zero-crossing detection and a CMOS start-up circuit were used to stabilize the class-E operation for various transmitter coil inductance values. This technique solves the common problem of mismatch between the switching frequency of the driving device and the resonant frequency of the load network, which can cause excessive power loss and damage to the active device. Data is transmitted by AM modulation of the carrier through switching the power supply between two levels. The transmitter uses a 9-V supply, consumes 212 mA, operates at 3.9 MHz, and has an efficiency of 71%. The efficiency is stable (< 2% change) against 13% variations in the inductance value of a pancake shaped transmitter coil. Index Terms-Biomedical microsystems, class-E transmitter, implantable electronics, inductive powering, transcutaneous links.