分布RLC树形互连线的时延估算稳定模型

基于分布RLC互连线模型,提出一种保证结果稳定的树形互连线的时延估算模型.此模型针对树形互连线,提出"等效ABCD矩阵"的概念,在此基础上通过二阶矩匹配估算树形互连线时域响应,并通过曲线拟合给出了解析形式的50%时延估算公式.新模型保证结果的稳定性,并且大大快于传统的仿真方法.实验表明,新模型与电路仿真软件HSPICE仿真结果相比较误差小于15%.     

集成运算放大器的噪声模型和精确测量

本文针对目前使用的集成运算放大器噪声模型及其测量方法的缺点，提出比其更加完善适用的噪声模型，根据叠加原理和等效噪声电路理论，推导出求解反相输入端与同相输入端噪声模型的等效噪声功率谱公式，并给出该模型的测量方法。     

时变时延的在线自适应估计

本文提出了一种时变时延的在线自适应估计新方法,首先,本文给出了一种修正的强跟踪滤波器算法,并且建立了时变时延的估计模型,基于此模型,时变时延可以被当成系统状态由修正的强跟踪滤波器算法直接进行估计,所提出的方法具有使用简单,跟踪迅速,精度高等特点,最后,仿真实验结果验证了本文方法的有效性。     

光接收机前端等效输入噪声电流谱密度与噪声系数间的关系

根据光接收机前端等效电路模型,建立了噪声系数与等效输入噪声电流谱密度的关系.提出通过测量光接收机前端电路噪声系数间接获得等效输入噪声电流谱密度的方法.155Mb/s高阻结构光接收机前置放大器的电路仿真与计算验证了推导公式的正确性.最后给出在芯片测试实例.     

光接收机前端等效输入噪声电流谱密度与噪声系数间的关系

根据光接收机前端等效电路模型,建立了噪声系数与等效输入噪声电流谱密度的关系.提出通过测量光接收机前端电路噪声系数间接获得等效输入噪声电流谱密度的方法.155Mb/s高阻结构光接收机前置放大器的电路仿真与计算验证了推导公式的正确性.最后给出在芯片测试实例.     

基于输出过采样的IIR信道迫零盲均衡

本文提出一种新的针对单输入单输出IIR信道的盲均衡算法.首先通过对信道输出的过采样建立特殊的多信道模型.对多信道模型的输出应用线性预测,证明了预测误差只包含多信道模型冲激响应在第一个时隙的参数,并给出最佳线性预测器的长度.通过预测误差的协方差矩阵可以求解该冲激响应参数.基于该参数可构造出不同时延的迫零均衡器.仿真结果显示了本文算法的有效性.     

微波功率测量的热等效误差

本文提出了热敏电阻功率传感器在功率测量时的传热模型,得出了传感器有效效率和热导、热容的关系表达式.定义了换热差异给微波功率测量带来的热等效误差.详细分析了热等效误差的来源,提出了该误差的表达式,最后给出了消除该项误差的办法.     

应用卷积和的离散线性时不变因果系统零输入响应求解

离散线性时不变因果系统的时域分析通常应用时域经典方法或卷积和方法.通常定义因果激励与系统脉冲响应的卷积和是系统的零状态响应.本文针对全激励序列输入时,给出求解离散线性时不变系统零输入响应的卷积和方法,并证明与等效激励法等价.同时,给出例题介绍提出的卷积和方法如何应用.     

室内宽带多输入多输出抽头时延线新模型研究

根据室内无线电波传播规律和实测数据,研究建立了一个新的抽头时延线模型,该模型可以简单有效地估计视距和非视距路径下室内平均功率时延谱,并与实验结果一致.在广义平稳非相关散射信道前提下,通过分析抽头时延模型频率相关系数、抽头系数分布和相关性、抽头多普勒频谱等特性参数,给出了评估抽头时延线模型的新方法.文中建立的信道模型和参数,对于室内多输入多输出无线信道模拟仿真有较为重要的意义.     

精确时延模型下满足时延约束的缓冲器数目最小化的算法

提出了在精确时延模型下,满足时延约束的缓冲器数目最小化的算法.给出一个两端线网,该算法可以求出满足时延约束的最小缓冲器数目.运用高阶时延模型计算互连线的时延,运用基于查找表的非线性时延模型计算缓冲器的时延.实验结果证明此算法有效地优化了缓冲器插入数目和线网的时延,在二者之间取得了较好的折中.算法的运行时间也是令人满意的.     

A new characterization of sub-μm parallel multilevelinterconnects and experimental verification

This paper describes the generation of a new universal design chart for submicron multilevel interconnection and its verification using test-structures. This has been developed to give the precise interconnect-capacitance for parallel submicron multilevel interconnections. Parasitic effects of a passivation film (Si₃N₄) on the interconnect capacitance have been also studied. The results of the test-structures designed have shown an excellent agreement with the design-chart with a maximum error of 8%. Furthermore, a simple propagation delay and response voltage model to a step voltage input have been developed incorporating the parallel-interconnect capacitance model. The new model is based on a lossy-transmission line equation and demonstrates an excellent agreement with RC lumped circuit simulations, resulting in a new simple and accurate prediction method for interconnect delay for use in VLSI timing design     

Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects

This paper presents novel methods for modeling and analysis of on-chip Single and H-tree distributed resistance inductance capacitance interconnects. The matrix pade-type approximation and scaling and squaring methods are employed for the numerical estimation of delay in single interconnect, and H-tree interconnects. The proposed models, which are based on these methods, provide rational function approximation for obtaining a passive interconnect model. Multiple single input single output model approximated transfer functions are developed for H-tree interconnects structure. With the equivalent reduced order lossy interconnect transfer functions, finite ramp responses are obtained, and line delay is estimated for various line lengths, input ramp rise times, source resistances, parasitic capacitances and load capacitances. In order to demonstrate the accuracy of proposed models, the estimated 50 % delay values are compared with the standard HSPICE W-element model and are found to be in good agreement. The proposed models worst case 50 % delay errors of single interconnect are 0.27 and 0.24 % respectively, while the worst case 50 % delay errors of H-tree structure are 5.73 and 3.94 % respectively.     

Power estimation techniques for FPGAs

The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and interconnect capacitance. In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs. We develop empirical prediction models for these parameters, suitable for use in power-aware layout synthesis, early power estimation/planning, and other applications. We examine how switching activity on a net changes when delays are zero (zero delay activity) versus when logic delays are considered (logic delay activity) versus when both logic and routing delays are considered (routed delay activity). We then describe a novel approach for prelayout activity prediction that estimates a net's routed delay activity using only zero or logic delay activity values, along with structural and functional circuit properties. For capacitance prediction, we show that prediction accuracy is improved by considering aspects of the FPGA interconnect architecture in addition to generic parameters, such as net fanout and bounding box perimeter length. We also demonstrate that there is an inherent variability (noise) in the switching activity and capacitance of nets that limits the accuracy attainable in prediction. Experimental results show the proposed prediction models work well given the noise limitations.     

FPGA潜在缺陷测试技术综述

在FPGA的设计、生产过程中,测试是保证器件质量的关键步骤。针对FPGA典型的潜在缺陷,阐述了主流的FPGA测试方法,对各方法的优缺点做了简要对比和总结。同时提出了对构成FPGA的可编程逻辑资源、互联线资源、端口资源、内嵌核4大模块分别进行测试的分类测试法,分析每个模块的典型缺陷,归纳对应的测试方法。     

GMRES方法在3-D寄生电容计算中的应用

随着VLSI向深亚微米发展、集成电路密度不断提高,互连延迟成了加快器件速度的一个限制因素,由于互连延迟是由金属连线间的电阻及电容所产生的,因此萃取寄生参数的工作更显重要.文章使用GMRES方法求解了3-D寄生电容分析的复系数线性方程组,并将其与SOR迭代法相比较.这种方法可以降低方程的迭代次数约20%,并明显减少了方程的求解时间.     

GaAs基高性能MEMS微波功率检测芯片

为了提高电容式MEMS微波功率检测芯片的性能,设计了一种GaAs基高性能MEMS微波功率传感芯片。通过建立双导固支梁电容模型,分析了传感芯片的传输特性、过载功率与灵敏度特性。在双导固支梁电容模型中提出了平行极板的两个等效条件;同时提出了一种新的梁宽等效方式,解决了双梁结构等效梁宽的失配问题,减小了模型的相对误差。双导固支梁电容模型很好地解释了导向梁的厚长比与初始高度对传感器过载功率和灵敏度的影响。测试结果表明,双导固支梁MEMS微波功率传感芯片在200 mW输入功率内的灵敏度为14.3 fF/W,而灵敏度的理论值为13.5 fF/W,两者的相对误差仅5.6%。因此,该理论模型对固支梁MEMS微波功率传感芯片的设计具有一定的借鉴意义。     

Comments on the optimum CMOS tapered buffer problem

Two recent papers, one by Li et al. (see ibid., vol 25, p1005-8,1990) and the other by Prunty and Gal (see ibid., vol. 27, no. 1, p118-9,1992), on the optimum CMOS tapered buffer problem are commented on. These papers claim that an equivalent “short-circuit” current capacitance should be added to the output capacitance of an inverter to account for the increased propagation delay obtained because of the short-circuit current that flows when a real input waveform is considered instead of an input step voltage. The reasoning results in an optimum tapering factor that is dependent on the waveform rise and fall times. However, the propagation delay only depends on the load capacitance and the ratio of the input to output transition times. In a fixed-taper buffer these transition times are equal making the optimum tapering factor independent of the “short-circuit” current. The comments also suggest an improved method of determining the optimum tapering factor in practical situations based on circuit simulations     

一种面向存算的高速字线驱动电路

在非易失性存算芯片(CIM)中,大规模阵列的栅极等效电容以及远距离传输导线的等效电容严重限制了字线驱动电路(WLDC)的切换速度.非易失性存算器件工作所需的多电压域的压差已远超字线驱动电路中单管耐压范围.文章提出了一种面向存算的高速字线驱动电路,结合阵列的工作原理,采取多级预处理电压控制方法,将多电压域多种高压进行可选...     

Analysis of input and output queueing for nonblocking ATM switches

A switch model for ATM networks is analyzed. Its interconnection network is internally nonblocking and is provided with dedicated input and output queues, one per switch inlet and one per switch outlet. The switch operates with an internal speed-up: more than one packet per slot can be transferred from the head-of-line positions of the input queues to each output queue by the interconnection network. Two different operation modes are considered for the interaction between input and output queues: backpressure mode and queue loss mode. The analytical model developed for the evaluation of the switch performance under random traffic assumes an infinite size for the switch, arbitrary values for input and output queue size, as well as for the speed-up factor. Switch throughput, packet delay and loss performance are evaluated and the analytical model accuracy is assessed using computer simulation results     

Flexibility of interconnection structures for field-programmablegate arrays

The relationship between the routability of a field-programmable gate array (FPGA) and the flexibility of its interconnection structures is examined. The flexibility of an FPGA is determined by the number and distribution of switches used in the interconnection. While good routability can be obtained with a high flexibility, a large number of switches will result in poor performance and logical density because each switch has significant delay and area. The minimum number of switches required to achieve good routability is determined by implementing several industrial circuits in a variety of interconnection architectures. These experiments indicate that high flexibility is essential for the connection block that joins the logic blocks to the routing channel, but a relative low flexibility is sufficient for switch blocks at the junction of horizontal and vertical channels. Furthermore, it is necessary to use only a few more routing tracks than the absolute minimum possible with structures of surprisingly low flexibility