A 500-MHz 16*16 complex multiplier using self-aligned gate GaAs heterostructure FET technology

A 16*16-bit complex multiplier using self-aligned gate GaAs heterostructure FET technology has been demonstrated. The multiplier uses a modified Booth's algorithm and three stages of pipeline with an embedded accumulator to allow the computation of a complex multiply function. A total of 4500 gates and over 20000 devices are required to implement this function and self-test functions. The chip produces a 20-bit output allowing 40 bits to describe a complex number result. Direct coupled NOR-gate FET logic was used throughout. The complex multiplier operated at a clock rate of 520 MHz with a power dissipation of 4 W under self-test. This corresponds to an average 'loaded' gate delay of 96 ps at 0.89 mW/gate. It also means that the multiplier produces a complex product, generated using four real multiplications and two additions, in less than 8 ns. This result demonstrates the high-speed capability of LSI digital circuits fabricated using MBE-grown GaAs heterostructure FET technology.<>     

A high-speed multiplier using a redundant binary adder tree

A 16-bit /spl times/ 16-bit multiplier for 2 two's-complement binary numbers based on a new algorithm is described. This multiplier has been fabricated on an LSI chip using a standard n-E/D MOS process technology with a 2.7-/spl mu/m design rule. This multiplier is characterized by use of a binary tree of redundant binary adders. In the new algorithm, n-bit multiplication is performed in a time proportional to log/SUB 2/ n and the physical design of the multiplier is constructed of a regular cellular array. This new algorithm has been proposed by N. Takagi et al. (1982, 1983). The 16-bit/spl times/16-bit multiplier chip size is 5.8 /spl times/ 6.3 mm/SUP 2/ using the new layout for a binary adder tree. The chip contains about 10600 transistors, and the longest logic path includes 46 gates. The multiplication time was measured as 120 ns. It is estimated that a 32-bit /spl times/ 32-bit multiplication time is about 140 ns.     

A 230-MHz half-bit level pipelined multiplier using truesingle-phase clocking

An 8-bit×8-bit signed two's complement pipelined multiplier megacell implemented in 1.6-μm single-poly, double-metal N-well CMOS is described. It is capable of throughputs of 230,000,000 multiplications/s at a clock frequency of 230 MHz, with a latency of 12 clock cycles. A half-bit level pipelined architecture, and the use of true single-phase clocked circuitry are the key features of this design. Simulation studies indicate that the multiplier dissipates 540 mW at 230 MHz. The multiplier cell has 5176 transistors, with dimensions of 1.5 mm×1.4 mm. This multiplier satisfies the need for very high-throughput multiplier cores required in DSP architectures     

A 100-MHz 4-mW four-quadrant BiCMOS analog multiplier

A four-quadrant analog multiplier based on a simple, very linear, and fast BiCMOS transconductor using MOS transistors operating in the triode region and NPN bipolar devices is presented. The four quadrant operation is obtained by crosscoupling-in a Gilbert-cell fashion-two transconductors with a third stage used to modulate the transconductances of the former two. A chip prototype of the multiplier has been integrated in a 1.2-μm BiCMOS process to validate the idea. It has been designed to achieve high linearity on both inputs: measured results show a total harmonic distortion (THD) of less than -40 dB with a 3-V peak-to-peak input signal at 5 MHz from a 5-V supply and an output -3 dB bandwidth of 100 MHz while dissipating 4 mW from a 3-V supply. The integrated chip prototype active area is 1 mm²     

A 12-Bit 200-MHz CMOS ADC

A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of these errors to zero. Fabricated in 90-nm digital CMOS technology, the ADC achieves a DNL of 0.78 LSB, an INL of 1.7 LSB, and an SNDR of 62 dB at an analog input frequency of 91 MHz while consuming 348 mW from a 1.2 V supply.      

A low logic depth complex multiplier using distributed arithmetic

A combinatorial complex multiplier has been designed for use in a pipelined fast Fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input-to-output delay as short as possible. A new architecture based on distributed arithmetic, Wallace-trees, and carry-lookahead adders has been developed. The multiplier has been fabricated using standard cells in a 0.5-μm process and verified for functionality, speed, and power consumption. Running at 40 MHz, a multiplier with input wordlengths of 16+16 times 10+10 bits consumes 54% less power compared to an distributed arithmetic array multiplier fabricated under equal conditions     

A 200-MHz 64-b dual-issue CMOS microprocessor

A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU is described. The chip is fabricated in a 0.75-μm CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm×13.9 mm and contains 1.68 M transistors. The chip includes separate 8-kbyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both IEEE and VAX standard floating-point data types. It is designed to execute two instructions per cycle among scoreboarded integer, floating-point, address, and branch execution units. Power dissipation is 30 W at 200-MHz operation     

200-MHz superscalar RISC microprocessor

Design and implementation details of the MIPS R10000, 200-MHz, 64-b superscalar dynamic issue RISC microprocessor is presented. It fetches and decodes four instructions per cycle and dynamically issues them to five fully pipelined, low latency execution units, Its hierarchical nonblocking memory system helps hide memory latency with two levels of set-associative, write-back caches. The processor has over 6.8 M transistors and is built in 3.3-V, 0.30 μm, four-layer metal CMOS technology with under 30 W of power consumption. The processor delivers peak performance of Spec95int of 9 and Spec95fp of 19 operating at 200 MHz. Clock and power distribution as well as circuit design techniques of several blocks are addressed     

A 600-MHz 54×54-bit multiplier with rectangular-styledWallace tree

This paper presents an efficient layout method for a high-speed multiplier. The Wallace-tree method is generally used for high-speed multipliers. In the conventional Wallace tree, however, every partial product is added in a single direction from top to bottom. Therefore, the number of adders increases as the adding stage moves forward. As a result, it generates a dead area when the multiplier is laid out in a rectangle. To solve this problem, we propose a rectangular Wallace-tree construction method. In our method, the partial products are divided into two groups and added in the opposite direction. The partial products in the first group are added downward, and the partial products in the second group are added upward. Using this method, we eliminate the dead area. Also, we optimized the carry propagation between the two groups to realize high speed and a simple layout, We applied it to a 54×54-bit multiplier. The 980 μm×1000 μm area size and the 600 MHz clock speed have been achieved using 0.18 μm CMOS technology     

A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valuedMOS current-mode circuits with dual-rail source-coupled logic

A new multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current, the switching speed of the circuit is improved at low supply voltage. As an application to arithmetic systems, a 200 MHz 54×51-b pipelined multiplier using the proposed circuits with a 1.5 V supply voltage is designed with a 0.8-μm standard CMOS technology. The performance of the proposed multiplier is evaluated to be about 1.4 times faster than that of a corresponding binary implementation under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the multiple-valued arithmetic circuit     

A low-power 200-MHz receiver for wireless hearing aid devices

The design of a low-power receiver for a wireless hearing aid system working in the 174-223-MHz range and its implementation in a 0.8-/spl mu/m BiCMOS technology is shown. The chip comprises a low-noise amplifier, an RF mixer, a variable-gain IF amplifier, and a demodulator. The latter consists of a digital phase shifter and I/Q IF mixers, fifth-order Bessel filters, and dc amplifiers. Measurements demonstrate that merely 667 /spl mu/A is consumed for the reception of an 8-ary phase-shift keying signal with a data rate of 336 kb/s. The receiver works with different modulation formats, including those carrying information in the amplitude.     

A 200-MHz CMOS phase-locked loop with dual phase detectors

A high-frequency integrated CMOS phase-locked loop (PLL) including two phase detectors is presented. The design integrates a voltage-controlled oscillator, a multiplying phase detector, a phase-frequency detector, and associated circuitry on a single die. The loop filter is external for flexibility and can be a simple passive circuit. A 2-μm CMOS p-well process was used to fabricate the circuit. The loop can lock on input frequencies in excess of 200 MHz with either or both detectors and consumes 500 mW from a single 5-V supply. The oscillator is a ring of three inverting amplifiers and draws from an internal supply voltage regulated by an on-chip bandgap reference. This combination serves to reduce the supply and temperature sensitivity is less than 5%/V, and the oscillator temperature variation is 2.2% in the range of 25 to 80°C. The typical oscillator tuning range is 112 to 209 MHz. The multiplying phase detector and phase-frequency detector exhibit input-referred phase offsets of <4° and -24°, respectively. A numerical system simulation program was written to explore the time-domain behavior of an idealized model based on the PLL design     

High-performance VLSI multiplier with a new redundant binary coding

This paper describes the design of a 16×16 redundant binary multiplier for signed 2's complement numbers. The multiplier uses a new coding scheme for representing radix-2 signed digits. The coding results in a factor of two reduction in the number of summands used with respect to the modified Booth algorithm. The design has a small number of modular cells and regular routing, making it suitable for automatic synthesis of larger data-width multipliers. In addition, the row-based redundant binary adder tree is an ideal structure for high-throughput applications.This work was supported in part by National Science Foundation grant MIP-9019862.     

A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration

In this paper, a novel calibration method for high-accuracy current-steering DACs is presented. Different from traditional calibration methods which achieves the calibration by adjusting the current values of the current sources, our method does the calibration by dynamically rearranging the switching sequence of the current sources. Since this resequencing is performed after chip implementation, even random errors can be cancelled. In this way, the total area needed for the current sources can be greatly reduced. The 14-bit DAC has been implemented in a standard 1P6M 0.18-mum CMOS technology. The core area of the chip is around 3 mm², among which the area of the current-source block is only 0.28 mm². The measured SFDR is 81.5 dB at 1 MHz signal frequency and 100 MHz sampling frequency. For 2 MHz signal frequency and 200 MHz sampling frequency, the measured SFDR is 78.1 dB.     

A 10-bit 200-MHz CMOS video DAC for HDTV applications

This paper describes a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications. The proposed 10-bit DAC is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB’s, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascade current sources and differential switches with deglitch latch improve dynamic performance. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter achieves a spurious-free dynamic range (SFDR) of above 55 dB over a100-MHz bandwidth and low glitch energy of 1.5 pVs. The circuit is fabricated in a 0.25 μm CMOS process and occupies 0.91 mm². When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3 V power supply.     

A 6-Bit/200-MHz Full Nyquist A/D Converter

This paper deals with the development of an extremely fast 6-bit flash A/D converter. To gain insight into the nature of speed limitations, the effects arising from operation at very high sampling rates have been investigated. This led to the implementation of an optimized double-stage comparator circuit. The chip has been fabricated in a fast standard oxide isolated bipolar process. At a sampling rate of 200 MHz, measurements show excellent dynamic performance (high signal-to-noise ratio, no error codes) up to input frequencies of 100 MHz.     

A 200-MHz IF BiCMOS signal component separator for linear LINCtransmitters

The linear amplification with nonlinear components (LINC) transmitter is an architecture that provides linear amplification using nonlinear but power efficient amplifiers. The signal component separator (SCS) is a crucial signal processing function of LINC. It forms two constant-amplitude phase-modulated signal components from the input signal. Due to the nonlinear signal processing involved, digital signal processing (DSP) implementation of the SCS at baseband has so far been assumed to be the best choice although it suffers from matching, bandwidth and power consumption problems. In this paper a new SCS architecture based on analog integrated circuit techniques is presented to avoid the disadvantages in a DSP based realization. A 200-MHz IF SCS chip using the proposed architecture was designed and fabricated in a 0.8 μm BiCMOS process. An experimental LINC transmitter was built with the SCS chip, nonlinear amplifiers and a power combiner. Test results showed that spurious levels around -50 dBc could be obtained with a π/4-shifted DQPSK modulated North American Digital Cellular (NADC) signal. This implies a high degree of linearity in the implemented LINC transmitter     

A 200-MHz sub-mA RF front end for wireless hearing aid applications

A hearing-aid system with RF connection between both ear-pieces is described and its transceiver is introduced. A suitable 200-MHz RF front end has been implemented in a 0.8-μm BiCMOS technology. Low power consumption and area constraint were key requirements. The chip comprises a low noise amplifier (LNA), a single balanced mixer, a varactor tuned LC local oscillator with buffer and a 16/17 dual-modulus prescaler. The LNA has a measured gain of 17.5 dB at 200 MHz. The conversion g_m of the mixer is 1.88 mS. The overall voltage gain and noise figure are 26 dB and 5.2 dB, respectively. The voltage-controlled oscillator's (VCO's) phase noise is -104.7 dBc/Hz at an offset of 24 kHz     

A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply

A sample-and-hold amplifier designed for the front end of high-speed low-power analog-to-digital converters employs a BiCMOS sampling switch and a low-voltage amplifier to achieve a sampling rate of 200 MHz while allowing input/output voltage swings of 1.5 V with a 3-V supply. The circuit also incorporates a cancellation technique to relax the trade-off between the hold-mode feedthrough and the sampling speed. Fabricated in a 20-GHz 1-μm BiCMOS technology, an experimental prototype exhibits a harmonic distortion of -65 dB with a 10-MHz analog input and occupies an area of 220×150 μm². The measured feedthrough is -52 dB for a 50-MHz analog input and the droop rate is 40 μV/ns     

A high-performance monolithic multiplier using active feedback

Since its conception in 1967, the linearized transconductance multiplier (LTM) has rapidly gained acceptance as the preferred approach to the realization of monolithic analog multipliers, and its simplicity has commended it for use in low-cost modular designs. Accuracies of these units have been limited to about 0.5 to 2 percent, and drift and noise performance have generally been worse than that possible using the dominant alternative technique of pulse-width-height modulation. This paper shows that when careful attention is given to all the sources of error it is possible to attain a five-fold improvement in accuracy and corresponding reductions in the drift and noise levels. Odd-order nonlinearities can be reduced to negligible magnitudes by the use of active feedback, by substituting the usual resistive-bridge feedback path by an amplifier identical to that used as the input stages.