Architectural and Basic Circuit Considerations for a Flexible 128 × 128 Mixed-Signal SIMD Vision Chip

From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35 m standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (7 bits) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330 GOPs (Giga Operations per second), and uses the power supply (180 GOP/Joule) and the silicon area (3.8 GOPS/mm²) efficiently, and is able to maintain VGA processing throughputs of 100 Frames/s with about 10–20 basic image processing tasks on each frame.     

A mixed-signal VLSI competitive neuroprocessor for video motion detection

VLSI design of a competitive neural network for video motion detection is presented. Massively parallel neurocomputing is performed by compact and efficient neuroprocessors. Local data transfer between the neuroprocessors is carried out by using an analog point-to-point interconnection scheme, while global data communication between the host computer and neuroprocessors is achieved through a digital common bus. Experimental results of the analog circuit blocks and system-level analysis on a sequence of real-world images are also presented.This research was partially supported by National Science foundation under Grant MIP-8904172 and by TRW Inc.     

Testing of programmable analog neural network chips

Artificial neural network chips can achieve high-speed performance in solving complex computational problems for signal and information processing applications. These chips contain regular circuit units such as synapse matrices that interconnect linear arrays of input and output neurons. The neurons and synapses may be implemented in an analog or digital design style. Although the neural processing has some degree of fault tolerance, a significant percentage of processing defects can result in catastrophic failure of the neural network processors. Systematic testing of these arrays of circuitry is of great importance in order to assure the quality and reliability of VLSI neural network processor chips. The proposed testing method consists of parametric test and behavioral test. Two programmable analog neural chips have been designed and fabricated. The systematic approach used to test the chips is described, and measurement results on parametric test are presented.This research was partially supported by DARPA under Contract MDA 972-90-C-0037 and by National Science Foundation under Grant MIP-8904172.     

A Mixed-Mode Analog Neural Network Using Current-Steering Synapses

A hardware neural network is presented that combines digital signalling with analog computing. This allows a high amount of parallelism in the synapse operation while maintaining signal integrity and high transmission speed throughout the system. The presented mixed-mode implementation achieves a synapse density of 4 k per mm² in 0.35 μm CMOS. The current-mode operation of the analog core combined with differential neuron inputs reaches an analog precision sufficient for 10 bit parity while running at a speed of 0.8 Teraconnections per second.     

A digital array based bit serial processor for arbitrary window size kernel convolution in vision sensors

The high speed and in-pixel processing of image data in smart vision sensors is an important solution for real time machine vision tasks. Diverse architectures have been presented for array based kernel convolution processing, many of which use analog processing elements to save space. In this paper a digital array based bit serial architecture is presented to perform certain image filtering tasks in the digital domain and hence gain higher accuracies than the analog methods. The presented method benefits from more diverse convolution options such as arbitrary size kernel windows, compared with the digital pulse based approaches. The proposed digital cell structure is compact enough to fit inside an image sensor pixel. When incorporated in a vision chip, resolutions of up to 12 bit accuracy can be obtained in kernel convolution functions with 35×28 μm² layout area usage per pixel in a 90 nm technology. Still, higher accuracies can be obtained with larger pixels. The power consumption of the approach is approximately 10 nW/pixel at a frame rate of 1 kfps.     

模拟神经元电路实现研究现状与进展

人工神经网络是现代信息处理领域的一个重要的方法。相对于软件实现 ,硬件实现方式能充分发挥神经网络并行处理的特点。用模拟电路实现神经网络电路形式简单、功耗低、速度快、占用芯片面积小 ,可以提高在神经网络芯片上神经元的集成度 ,神经元电路适合用模拟电路实现。文中综述了当前神经网络单元的模拟 VLSI实现的成果、新技术以及作者的工作成果。针对应用最广泛的线性和平方突触神经元 ,详细从权值存储单元、突触电路和阈值函数电路三方面来叙述。对各种实现方式的优缺点进行了比较 ,同时指出了神经网络实现电路中需要考虑的因素。最后 ,展望了用集成电路技术实现自学习神经网络的发展方向     

A programmable analog cellular neural network CMOS chip for highspeed image processing

A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4×4 CNN prototype system has been designed in a 2.4 μm CMOS technology and successfully tested. The cell density is 380 cells/cm² and the cell time constant is 10 μs. The current drain for a typical template is 40 μA/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128×128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies     

Initial Timing Acquisition for Binary Phase‐Shift Keying Direct Sequence Ultra‐wideband Transmission

This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra‐wideband (DS‐UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog‐to‐digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase‐shift keying DS‐UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo‐random noise sequence generated with a primitive polynomial, 1+x²+x⁵, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo‐random noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS‐UWB proposal.     

一种用于暗光环境下的CMOS图像传感器的非线性模数转换器

从优化算法、硬件结构和模拟结果入手,通过对CMOS图像传感器暗光环境下模数转换电路的优化设计,提出了一种暗光环境下性能提升的大动态范围非线性模数转换器的设计.在模拟电路模块完成了暗光优化图像处理算法,使暗光环境下光电转换数字码密度增大,在不增加额外芯片面积和功耗的同时,提高了CMOS图像传感器的暗光图像性能.     

Design and characterization of analog VLSI neural network modules

A systematic method for testing large arrays of analog, digital, or mixed-signal circuit components that constitute VLSI neural networks is described. This detailed testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2 μm double-polysilicon CMOS technologies are presented to demonstrate the testing procedure     

A CMOS facsimile video signal processor

A CMOS image scanning signal processor which can be used for CCITT Group-4 facsimile has been developed. To obtain high-speed processing (5 MHz) and high-precision shading distortion correction (up to 70%), hybrid architecture of digital and analog techniques and parameter setting by software are combined. Image sensor and printer interfaces and a digital processor which can do linear zooming and data format conversion are built into a chip. The 6.5/spl times/7.8-mm chip is fabricated using 2.5 /spl mu/m CMOS technology and contains 25000 transistors.     

A 0.8-μm CMOS two-dimensional programmable mixed-signalfocal-plane array processor with on-chip binary imaging and instructionsstorage

This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose values are programmable with 7-b accuracy. The internal programming signals are analog, but the external control interface is fully digital. On-chip nonlinear digital-to-analog converters (DAC's) map digitally coded weight values into analog control signals, using feedback to predistort their transfer characteristics in accordance to the response of the analog programming circuitry. This strategy cancels out the nonlinear dependence of the analog circuitry with the programming signal and reduces the influence of interchip technological parameters random fluctuations. The chip includes a small digital RAM memory to store eight sets of processing parameters in the periphery of the cell array and four 2-D binary images spatially distributed over the processing array. It also includes the necessary control circuitry to realize the stored instructions in any order and also to realize programmable logic operations among images. The chip architecture is based on the cellular neural/nonlinear network universal machine (CNN-UM). It has been fabricated in a 0.8-μm single-poly double-metal technology and features 2-μs operation speed (time required to process an image) and around 7-b accuracy in the analog processing operations     

CMOS realization of two-dimensional mixed analog-digital Hamming distance discriminator circuits for real-time imaging applications

The architecture of an integrated Hamming artificial neural network, and its use as a versatile signal/image processing circuit is presented. The circuit operation relies on the charge-based processing of sum-of-products terms, complemented with digital post-processing. The synthesis of complex functions such as winner-(loser)-take-all, k-winner-(loser)-take-all, rank ordering are demonstrated with a minimal hardware overhead. Different operation modes and corresponding hardware configurations are presented. The VLSI realization of the core two-dimensional Hamming distance discriminator, and the chip measurements are discussed. As such, the presented Hamming discriminator is uniquely suitable for real-time image processing and alignment applications.     

A 1000 FPS at 128/spl times/128 vision processor with 8-bit digitized I/O

This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-/spl mu/m fully digital CMOS technology, contains /spl sim/ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 /spl mu/s have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.     

Digital Design of Discrete Exponential Bidirectional Associative Memory

The exponential bidirectional associative memory (eBAM) was proved to be a systematically stable high-capacity memory. Considering the difficulty of the implementation of such an eBAM by analog circuits and the compactability with binary logic circuits, we adopt the digital logic methodology to design such a neural network. Besides, we also count in other factors, e.g., scalability and speed, so that the complete digital design of this neural network is feasible. In order to realize the eBAM by digital circuitry only, some special design is required such that the exponential function can be implemented without the loss of operating speed. For example, a high-speed 8-to-9 exponent value generator is required in the design. In addition, because the traditional add/sub accumulator costs too much area when the dimension of patterns is large, a cascaded increment/decrement accumulator (IDA) is proposed in the design, which can also speed up the addition or subtraction besides the saving of chip area. For the sake of area saving, regenerated IDA is also proposed to reduce the cost of chip area. At last, thorough simulations by MAGIC and IRSIM are proceeded to verify the performance of the design.     

A CMOS triple 100-Mbit/s video D/A converter with shift register and color map

A 100-Mb/s CMOS video digital-to-analog converter (VDAC) chip is described. The VDAC provides all output functions for a four-plane color video subsystem. Included in this chip are: direct drivers for 75-/spl Omega/ cables; three 100-MHz 4-bit DACs; a color-map memory; video shift registers; cursor logic and a processor interference. The design approaches for both the analog and digital circuitry are discussed. The bench and automatic testing of this high-speed, high-pin-count, combined analog/digital chip are presented.     

Nonlinear digital filters mimicking cellular neural networks

This work is motivated by the need forFaithful digital simulation of cellular neural networks (CNNs) that maintains most of their qualitative properties of stability and convergence. An interconnection of nonlinear digital filters mimicking behaviors of the analog CNNs is proposed, and the main properties are studied in detail. The discrete model obtained is proven to have the same convergence properties as the original analog network. The key to this development is the use of anAppropriate discretization scheme. Our discrete approximation to the nonlinear state-space representation of cellular neural networks is such that the Lyapunov function used to show convergence in analog cellular neural networks is still a Lyapunov function (when appropriately discretized) for our nonlinear digital filter network. This is in contrast to other digital simulations of CNNs, which have not been proven to preserve the convergence properties. The network of nonlinear digital filters so introduced thus adds another item to the catalog of digital filters obtained viaappropriate discretization of analog circuits, e.g., wave digital filters, orthogonal filters, and certain other of their more recently studied nonlinear counterparts.All authors were with the Stevens Institute of Technology, Hoboken, NJ, 07670 when this work was performed.Support from NSF grant MIP 9696176.     

High-Speed CORDIC Based on an Overlapped Architecture and a Novel σ-Prediction Method

This paper presents architectural and algorithmic approaches for achieving high-speed CORDIC processing in both of the two operating modes: vectoring and rotation. For vectoring mode CORDIC processing, a modified architecture is proposed, which aims at reduction of computation time by overlapping the stages for redundant addition and selection of rotation direction. In addition, a novel rotation direction prediction scheme for rotation mode CORDIC is presented. The method is based on approximation of the binary angle input to a number with the arctangent weights (tan^–1 2^–i). The implementation is designed to keep the fast timing characteristics of redundant arithmetic in the x/y path of the CORDIC processing. The characteristics are analyzed with respect to latency time and area, and compared with those obtained by conventional CORDIC implementations. The results show that the proposed techniques reduce not only the block latency but also the overall computation time. Thus, they achieve higher throughput in pipelining.     

A 1.3 GHz SOI CMOS test chip for low-power high-speed pulseprocessing

A test chip has been fabricated in a fully depleted SOI CMOS process with 0.25-μm drawn gate length, It successfully demonstrates the types of circuits required to perform digital filtering, detection, and data thinning functions at high clock speeds. The test chip contains over 5000 transistors and was clocked at speeds up to 1.3 GHz. A target application for these circuits is a very wideband compressive receiver for real-time spectral analysis, which requires digital signal processing to be performed on a 20-Gb/s data stream formed by digitizing a stream of fast analog pulses. Adjustable high-speed on-chip clocks, input and output registers, and large decoupling capacitors allowed testing of the chip to be performed using an inexpensive, low-speed probe card and a standard wafer prober     

A Mixed Signal Fuzzy Controller Using Current Mode Circuits

A mixed analog-digital fuzzy logic inference processor chip, designed in a 0.35-μm CMOS technology, is presented. The analog fuzzy engine is based on a novel current-mode CMOS circuit used for the implementation of fuzzy partition membership functions. The architecture consists of a 3 inputs—1 output analog fuzzy engine, internal digital registers to store the parameters of the fuzzy controller, and a digital subsystem that allows the programmability of the fuzzy controller via an I ² C interface. The architecture, circuits, and some Cadence Spectre simulations are presented.