Banyan multipath self-routing ATM switches with shared buffer typeswitch elements

The asynchronous transfer mode (ATM) has been selected as the multiplexing and switching technique for use in the public broadband ISDN (B-ISDN). We propose a large-scale ATM switch architecture in which a banyan multipath self-routing network is combined advantageously with a shared buffer type switch element. The proposed banyan space-division concept yields a simple architecture having the potential to accommodate easily the growth of switch size. Since the interconnection network between switch modules or between switch elements has a twofold banyan architecture, expansion in crosspoints or interconnections with the increase of switch size can be lessened. The multipath self-routing concept makes the switch performance better and leads to an efficient realization of a switch element on a single chip as the fundamental building block of a large-size switch. We analyze the required capacity for queuing buffers in the switching network. The multipath approach inevitably creates information sequence disturbances. Therefore, we also analyze the out-of-sequence phenomenon of a banyan multipath switching system. To satisfy the sequence integrity requirement for ATM, a simple approach is proposed for the multipath switch by using a spacing controller. In addition, we quantify the improvement of out-of-sequence performance under the spacing controller scheme     

A traffic-handling comparison of centralized and distributed ATMswitching systems

This paper describes a geographically distributed ATM switching architecture that exploits new possibilities offered by lightwave technology. Small modules that provide both an access and an ATM switching function are distributed over some extended geographical area and connected to a passive optical medium. Each module is equipped with some small number of electrooptic transmitters and receivers that provide access to the medium. Assignment of wavelengths to transmitter/receiver pairs create logical channels that are wavelength-multiplexed onto the medium, thus creating a logical connection diagram among the modules. Advantages of the lightwave-based distributed architecture are the huge bandwidth of the medium, a high degree of modularity to facilitate growth, high reliability, and the ability to provide “clear channels” among modules. On the other hand, if the externally offered flow of ATM cells among modules is too uniform, then each module may be capable of supporting only a fraction of the load that could be carried by any port of a fully connected centralized ATM switch with output queueing. Fortunately, under the much more realistic assumption of nonuniform traffic, the independence between the logical connection diagram and the physical topology of the medium can be exploited by reconfiguring the connection diagram to “match” the nonuniformity of the cell traffic. Simulation results show that, as the nonuniformity becomes larger, the reconfiguration technique allows the traffic-handling capability of a distributed switch to match that of a centralized switch     

An expandable time-division circuit switching LSI and networkarchitecture for broadband ISDN

A broadband network architecture is proposed that integrates multimedia services, such as data, video, and telephony information, using 52-Mb/s based STM-paths at the user network interface (UNI). The user can access any new service via the STM-based access network via either synchronous transfer mode (STM) switching or asynchronous transfer mode (ATM) switching. STM circuit switching supports long duration, constant bandwidth data transfer services such as video and high-definition television (HDTV) distribution and will also be used for the crossconnect system. Circuit switching can provide transparent transmission during long connection periods. This paper also proposes an expandable time-division switch architecture, an expandable time-division switching LSI, and an expandable switching module for small to large size system applications. The proposed time-division switching LSI, module, and system handle 52-Mb/s bearer signals and have throughputs of 2.4 Gb/s, 10 Gb/s, and 40 Gb/s, respectively. The time-division switch realizes video distribution with 1:n connections. Finally, a local switching node that features an expandable 52-Mb/s time-division circuit switching network is shown for multimedia access networking     

An efficient architecture for fault-tolerant ATM switches

A cost-effective fault-tolerant architecture called FAUST is presented for ATM switches. The key idea behind the architecture is the incorporation of spare units and associated commutation logic into strategic partitions of the switching system. The definition of a replaceable unit is flexible, and based on packaging considerations. The commutation logic can switch in a spare unit in place of a failed one at cell rate, and is distributed entirely in the existing switch control units. So the additional overhead is almost entirely in the spare modules provided. The technique is far superior to a duplex configuration in terms of reliability improvement vs. component redundancy, and can be applied to established architectures for ATM switches, including multistage sort and shared memory based architectures. Its scalability also makes it applicable to system sizes from a few tens of lines to a few thousand     

多平面ATM交换网络结构及其性能分析

本文提出一种新的多平面ＡＴＭ交换网络结构。该结构比单平面结构有更好的性能,并且在网络平扩容和冗余备份等方面均具有优良的特性。通过采用虚拟队列和概率母函数的方法,分析了在随机均匀业务模型下该交换网络缓存器的平均队长、平均信元时延和交换网络最大吞吐率等性能参数的封闭表达式,计算机仿真结果表明了分析结果具有很高的精确度。该分析方法不需复杂的叠代算法,在交换机的工程设计中同时也具有重要的实际意义。     

Large-scale ATM multistage switching network with shared buffermemory switches

The configuration of an asynchronous transfer mode (ATM) switch architecture using a shared buffer memory switch (SBMS) is discussed. The scaling factors of the ATM switching network under a condition of mixed applications, including a conventional mix and telecommunication with video, are analyzed. The use of the SBMS as the unit switch for a multistage switching network is examined. A prototype system and its performance evaluation and experimental data are presented. The data indicate excellent performance under a burst cell arrival condition. The buffer size of the SBMS can be reduced in comparison with that of an individual (nonshared) buffer memory switch. A configuration for a large-scale ATM switching network with multistage switches is proposed     

ATM in B-ISDN communication systems and VLSI realization

The Asynchronous Transfer Mode (ATM) is considered to be a key technology for B-ISDN. This paper discusses VLSI trends and how VLSI's can be applied to realize ATM switching node systems for B-ISDN. Implementing a practical ATM node system will require the development of technologies such as high-throughput ATM switch LSI's with up to 10 Gb/s capacity and SDH termination technology based on optical fiber transmission. An ATM traffic-handling mechanism with Quality of Service (QoS) controls such as ATM layer performance monitoring, virtual channel handling, usage parameter control, and VP shaping requires several hundred thousand logic gates and several megabytes of high-speed static RAM; VLSI's must be introduced if such mechanisms are to be implemented. ATM node system architecture is based on design principles of a building-block-type structure and hierarchical multiplexing. The basic ATM call handling module, the AHM, is composed mainly of a line termination block and a self-routing switch block; we analyzed this module from the viewpoint of the amount of hardware it requires. Finally, future ATM node systems are discussed on the basis of 0.2-μm VLSI development trends and hardware requirements such as the need for ultrahigh integration of logic gate with memory, multichip modules, and low power dissipation technology     

The Tera project: a hybrid queueing ATM switch architecture for LAN

The Tera ATM LAN project at Carnegie Mellon University addresses the interconnection of hundreds of workstations in the Electrical and Computer Engineering Department via an ATM-based network. The Tera network architecture consists of switched Ethernet clusters that are interconnected using an ATM network. This paper presents the Tera network architecture, including an Ethernet/ATM network interface, the Tera ATM switch, and its performance analysis. The Tera switch architecture for asynchronous transfer mode (ATM) local area networks (LAN's) incorporates a scalable nonblocking switching element with hybrid queueing discipline. The hybrid queueing strategy includes a global first-in first-out (FIFO) queue that is shared by all switch inputs and dedicated output queues with small speedup. Due to hybrid queueing, switch performance is comparable to output queueing switches. The shared input queue design is scalable since it is based on a Banyan network and N FIFO memories. The Tera switch incorporates an optimal throughput multicast stage that is also based on a Banyan network. Switch performance is evaluated using queueing analysis and simulation under various traffic patterns     

TORUS: terabit-per-second ATM switching system architecture basedon distributed internal speed-up ATM switch

A high-speed and distributed ATM switch architecture, called the TORUS switch, is proposed with the aim of achieving a terabit-per-second ATM switching system. The switch is a distributed and scalable internal speed-up crossbar-type ATM switch with cylindrical structure. The self-bit-synchronization technique and optical interconnection technology are combined to achieve gigabit-rate cell transmission, where high-density implementation technologies such as multichip module technology are not required at all. Also, distributed contention control based on the fixed output-precedence scheme is newly adopted. This control is very suitable for high-speed devices because its circuit is achieved with only one gate in each crosspoint. A TORUS switch is fabricated as a 4×2 switch module using optical interconnection technology and very high-speed crosspoint LSIs, constructed using an advanced Si-bipolar process. Measured results confirm that the TORUS switch can be used to realize an expandable terabit-rate ATM switch     

The UniMIN switch architecture for large-scale ATM switches

A general expansion architecture is proposed that can be used in building large-scale switches using any type of asynchronous transfer mode (ATM) switch. The proposed universal multistage interconnection network (UniMIN) switch is composed of a buffered distribution network (DN) and a column of output switch modules (OSMs), which can be any type of ATM switch. ATM cells are routed to their destination using a two-level routing strategy. The DN provides each incoming cell with a self-routing path to the destined OSM, which is the switch module containing the destination output port. Further routing to the destined output port is performed by the destination OSM. Use of the channel grouping technique yields excellent delay/throughput performance in the DN, and the virtual FIFO concept is used for implementing the output buffers of the distribution module without internal speedup. We also propose a “fair virtual FIFO” to provide fairness between input links while preserving cell sequence. The distribution network is composed of one kind of distribution module which has the same size as the OSM, regardless of the overall switch size N. This gives good modular scalability in the UniMIN switch. Performance analysis for uniform traffic and hot-spot traffic shows that a negligible delay and cell loss ratio in the DN can be achieved with a small buffer size, and that DN yields robust performance even with hot-spot traffic. In addition, a fairness property of the proposed fair virtual FIFO is shown by a simulation study     

雷达组网通信中的ATM交换机

介绍了ＡＴＭ交换技术在雷达组网通信中的应用。通过对基于中央处理站的雷达组网通信技术需求的分析，提出了一种类似于用户—服务器模式的ＡＴＭ交换结构。ＡＴＭ技术是Ｂ—ＩＳＤＮ的基础，ＡＴＭ交换技术是ＡＴＭ技术的核心，它不仅可用于民用通信业务，而且对于电子干扰环境下雷达网对密集多目标跟踪时所涉及的通信业务也很有效。文章对ＡＴＭ交换机在雷达网中的数据交换作了分析，并以计算机仿真手段评估了三种特定通信环境下输出缓冲型ＡＴＭ交换机的利用率和输出队列概率分布情况。     

Practical implementation and packaging technologies for alarge-scale ATM switching system

The practical implementation of a trial large-scale asynchronous transfer mode (ATM) switching system and its packaging technologies are described. The architecture of the ATM switching system is discussed with an emphasis on system scalability. A building block architecture in which switching capacity can be expanded in a modular fashion is introduced. The design of the ATM switching system, including the ATM switch element, is described. The implementation of the VLSIs for the ATM switch which realize a highly modular system is explained. Bit-slice techniques are effectively used to realize a high-speed switch element as a CMOS VLSI chipset. An edge-to-edge orthogonal packaging technique is also presented     

A high-speed CMOS circuit for 1.2-Gb/s 16*16 ATM switching

The authors describe a 0.7- mu m CMOS asynchronous transfer mode (ATM) switch circuit of 350 K transistors, the kernel of a fully autonomous 16*16 ATM switching matrix devoted to telecommunications. This matrix is able to switch ATM multiplexes with a throughput of up to 1.2 Gb/s per access line, and was implemented using 16 receiver/transmitter circuits and a control circuit. The architecture of the ATM switch circuit is based on a large embedded and shared dual-access memory. Each chip processes 4-b slices of each incoming multiplex. Seven such chips working in parallel are enough to achieve standard ATM cell switching. Up-to-date test features, such as boundary scan, built-in self-test, and redundancy were implemented in the circuit.<>     

APON系统中交叉连接的研究与实现

介绍了一种用于通信网络的APON无源光网络系统,该系统通过ATM交换模块实现信号的转换与传输,主要讨论了ATM交换的原理、交换单元的结构以及APON系统中交叉连接的实现。     

Hybrid optical switch using passive polymer waveguides andsemiconductor optical amplifiers

Optical switching can be performed by using optical amplifiers combined with a passive waveguiding network. Recently, most of the effort in optical amplifier switch modules have been focused on monolithic switches in which the entire device is fabricated on an InP substrate together with the semiconductor optical amplifiers (SOA's). In this paper, we investigate the use of SOA's with passive polymer waveguides to make hybrid switches of varying sizes. The optical amplifiers serve dual purposes, gating the signal and amplifying the signal. Amplification is needed in order to offset the losses associated with the passive waveguide elements as well as the losses from component misalignments in the switch module. Our analysis finds the largest switch module size that can be made with the architecture used. We also calculate the maximum number of switch modules which can be cascaded in order to retain a bit-error rate (BER) under 10^-9     

Fault tolerance in Clos–Knockout multicast ATM switch

In this paper, we propose a new architecture for multicast ATM switches with fault tolerant capability based on the Clos–Knockout switch. In the new architecture, each stage has one more redundant switch module. If one switch module is faulty, the redundant module would replace the faulty one. On the other hand, under the fault‐free condition, the redundant modules in the second and third stages will provide additional alternative internal paths, and hence improve the performance. The performance analysis shows that the cell loss probability is lower than the original architecture when all modules are fault free, and the reliability of the original architecture is improved. Copyright © 2002 John Wiley & Sons, Ltd.     

Gigabit networking research at Bellcore

A communication architecture appropriate for gigabit networks, the multimedia end-to-end communication architecture (MECA), is described. MECA provides multimedia applications with the service they require in a single communication system. MECA encompasses the network, host-network interface, and associated protocols. The architectural characteristics of MECA are compared with those of existing communication systems and the TP++ transport protocol used by MECA is compared to existing transport protocols. Three host-network interfaces built for AURORA, a five-gigabit testbed network that includes an experimental asynchronous transfer mode (ATM) network running over a synchronous optical network (SONET), are described. The Sunshine ATM switch that supports MECA using a scalable Batcher-Banyan switching fabric and highly programmable port controllers is discussed     

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8×8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-μm gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s     

Performance analysis of a growable architecture for broad-bandpacket (ATM) switching

The performance of a growable architecture for broadband asynchronous transfer mode (ATM) switching consisting of a memoryless self-routing interconnect fabric and modest-size packet switch modules is examined. The cell loss probability is the focus because the architecture attains the best possible delay-throughput performance if the packet switch modules use output queuing. There are two sources of cell loss in the switch. First, cells are dropped if too many simultaneous arrivals are destined to a group of output ports. Second, because a simple, distributed path-assignment controller is used for speed and efficiency, cells are dropped when the controller cannot schedule a path through the switch. The authors compute an upper bound on arrivals, possibly including isochronous circuit connections, and show that both sources of cell loss can be made negligibly small     

A modular architecture for very large packet switches

Switch modules, the building blocks of this system, are independently operated packet switches. Each module consists of a Batcher sorting network, a stack of binary trees, and a bundle of banyan networks. The modular architecture is a unification of the Batcher-banyan switch and the knockout switch, and can be physically realized as an array of three-dimensional parallel processors. Switch modules are interconnected only at the outputs by multiplexers. The partitioned switch fabric provides a flexible distributed architecture, which is the key to simplify the operation and maintenance of the whole switching system. The modularity implies less stringent synchronization requirements and makes higher-speed implementation possible. The proposed modular switch is intended to meet the needs of broadband telephone offices of all sizes. It is estimated that a modular switch with terabit capacity can be built using current VLSI technologies