Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO2 gate insulator

Polysilicon thin-film transistors (poly-Si TFT's) with liquid phase deposition (LPD) silicon dioxide (SiO₂) gate insulator were realized by low-temperature processes (<620°C). The physical, chemical, and electrical properties of the new dielectric layer were clarified. The low-temperature processed (LTP) poly-Si TFT's with W/L=200 μm/10 μm had an on-off current ratio of 4.95×10 ⁶ at V_D=5 V, a field effect mobility of 25.5 cm ²/V·s at V_D=0.1 V, a threshold voltage of 6.9 V, and a subthreshold swing of 1.28 V/decade at V_D=0.1 V. Effective passivation of defects by plasma hydrogenation can improve the characteristics of the devices. The off-state current (I_L) mechanisms of the LTP poly-Si TFT's were systematically compared and clarified. The I_L is divided into three regions; the I_L is attributable to a resistive current in region I (low gate bias), to pure thermal generation current in region II (low drain bias), and to Frenkel-Poole emission current in region III (high gate bias and drain bias)     

Gate bias stress in hydrogenated and unhydrogenated polysilicon thin film transistors

Polysilicon Thin Film Transistors (TFT's), fabricated at temperature lower than 600°C, are now largely used in many applications, particularly in large area electronics. The reliability of these TFT's under different electrical conditions is then questionable. In this work, Gate bias stress is studied in two types of polysilicon TFT's originated from the same process. One type is unhydrogenated and the other is submitted to a Radio-Frequency hydrogen plasma. As this hydrogenation step is known to improve the TFT's performances but to introduce unstability, the unhydrogenated TFT's are expected to be more stable. The behaviours of the two types of TFT's under the gate bias stress are found however only different. The bias aging of unhydrogenated TFT's fit with the known model of the n-channel c-Si MOSFET's bias stress. The behaviour of the hydrogenated TFT's is explained from the model of defect creation in hydrogenated amorphous silicon.     

Gate-overlapped lightly doped drain poly-Si thin-film transistorsfor large area-AMLCD

We have fabricated a gate-overlapped lightly doped drain (GO-LDD) polycrystalline silicon thin-film transistor (poly-Si TFT) applicable for large area AMLCD by employing the uniform and low-temperature doping techniques, such as ion shower doping and in situ doping. Experimental results show that the leakage current of the proposed TFT's is reduced by more than the magnitude of two orders, compared with that of conventional nonoffset TFT, while the ON current is scarcely decreased. It is verified by the device simulator that the electron concentration in the LDD region is increased under the ON state and decreased under the OFF state due to the field plate with gate potential over the LDD region. Furthermore, the vertical peak electric field in the LDD region is decreased significantly by the extended field plate potential during the OFF state. It is observed that the gate bias stress degrades significantly the subthreshold slope of the ion shower doped GO-LDD TFT's at the low drain bias but does not degrade the device characteristics of those with in situ doping due to the high-quality TEOS SiO₂ interlayer     

Stability of short-channel P-channel polysilicon thin-filmtransistors with ECR N2O-plasma gate oxide

Stability of hydrogenated short-channel (⩽3 μm) p-channel poly-Si TFT's with very thin (12 nm) electron cyclotron resonance N₂O plasma gate oxide is investigated. The fabricated poly-Si TFT's with gate length not less than 2 μm show excellent stability characteristics of less than 0.1 V in the threshold voltage shift and less than 3% in the percent change of transconductance after harsh electrical stresses. In a small |V_G| stress, an effective shortening of channel length is observed due to trapping of hot-electrons and the minimum leakage current is decreased. However, a large |V_G| stress causes more degradation on the subthreshold slope and minimum leakage current due to trapping of hot-holes     

Thinner liquid phase deposited oxide for polysilicon thin-filmtransistors

To scale down the gate insulator thickness of polysilicon thin-film transistors (poly-Si TFT's), a thinner oxide is developed by liquid-phase deposition with a small quantity of H₂O added, producing a rather high-quality oxide. Poly-Si TFT with such a thin oxide reveals good performances in electric characteristics. Thus, the novel thinner oxide is a good candidate as a poly-Si TFT gate insulator in the near future     

A new patterning process concept for large-area transistor circuitfabrication without using an optical mask aligner

A new concept to produce large thin film transistor liquid crystal displays (TFT-LCD's) without using an optical mask aligner is proposed which emphasizes patterning technology. Some experimental thin film transistors (TFT's) are fabricated according to the concept and operated like conventional transistors fabricated by using an optical mask aligner. The concept includes improvement of printing technology and development of a double-layer resist method. The latter method employs a printed ink pattern and a photoresist. This prevents contamination of thin films by metal impurities which affect electrical characteristics of the TFT's. A special gravure offset printing technology is proposed, composed of a large thixotropy valued UV ink, and a fine, precision etched glass intaglio. The experimental TFT's, with a designed minimum gate length of 10 μm, have comparable electric characteristics to those of conventional poly-Si TFT's     

Stress-induced leakage current in p+ poly MOS capacitorswith poly-Si and poly-Si0.7Ge0.3 gatematerial

The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si_0.7 Ge_0.3) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory devices     

Rapid thermal anneal of gate oxides for low thermal budget TFT's

The performance and reliability of deposited gate oxides for thin film transistors (TFT's) has been studied as a function of rapid thermal annealing (RTA) conditions. The effect of temperature ranging from 700 to 950°C and the annealing ambients including oxygen (O₂), argon (Ar), and nitrous oxide (N₂O) is investigated. Improvement in charge to breakdown (Q_bd) is seen starting from 700°C, with marked increase at 900°C temperature and above. The N₂O and Ar ambients result in higher Q_bd compared to O₂ ambient and we attribute this to reduced interfacial stress. Fourier Transform Infrared spectroscopy (FTIR) is used to qualitatively measure the stress. The bias temperature instability is decreased by RTA. The TFT characteristics are significantly improved with RTA gate oxide. The RTA-Ar anneal at 950°C results in the lowest trap density in TFT's as measured from charge pumping technique     

Performance and reliability improvements in poly-Si TFT's byfluorine implantation into gate poly-Si

High-performance and high-reliability TFT's have been obtained using a fluorine ion implantation technique. The fluorine implantation into the gate poly-Si of TFT caused a positive Vth shift, increased the ON current, and decreased the leakage current significantly. Our investigation indicates that the Vth shift originates from negative charges generated in the gate oxide by the fluorine implantation. The improvement of drain current is attributed to fluorine passivation of trap states in the poly-Si and to a modulation of offset potential due to the same negative charges under the offset region. Furthermore, high immunity against the -BT stress and TDDB of the gate oxide was achieved by the fluorine implantation. It is considered that the strong Si-F bonds created by the fluorine implantation raise the stress immunity     

Novel gate dielectric films formed by ion plating forlow-temperature-processed polysilicon TFTs

A novel SiO₂ film formed by ion plating (IP) at room temperature was developed for low-temperature-processed (LTP) (<625°C) polysilicon thin-film transistors (poly-Si TFT's). The IP SiO₂ film is a high-density dielectric with strained bonds, and also a high-performance insulator with low-leakage current and high-breakdown voltage. Poly-Si TFT with IP SiO₂ as a gate insulator shows satisfactory performance     

Performance Improvement of Ultralow Temperature Polycrystalline Silicon TFT on Plastic Substrate by Plasma Oxidation of Polycrystalline Si Surface

The thin-film transistor (TFT) performances were enhanced and stabilized by the plasma oxidation of the polycrystalline Si surface prior to the plasma enhanced atomic layer deposition of an Al₂O₃ gate dielectric film. The authors attribute this improvement to the formation of a high-quality oxide interface layer between the gate dielectric film and the poly-Si film. The interface oxide has a predominant effect on the TFT's characteristics and is regulated by the plasma oxidation temperature and the gap distance between the electrode and polycrystalline Si surface     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

A new self-aligned offset staggered polysilicon thin-filmtransistor

A new self-aligned offset staggered polysilicon thin-film transistor (poly-Si TFT) has been proposed and demonstrated to have a suppressed leakage current. For the self-aligned offset structure, planarization with thick photoresist and etchback of photoresist are successfully utilized. The offset length can be easily controlled by the thickness of the gate material without photolithographic limitation. In the self-aligned offset polysilicon TFT's, the leakage current decreases with an increasing offset length     

Self-passivated copper gates for amorphous silicon thin-filmtransistors

A solution to the amorphous silicon transistor gate metallization problem in active matrix liquid crystal displays (AMLCD's) is demonstrated, in the form of a self-passivated copper (Cu) process. Cu is passivated by a self-aligned chromium (Cr) oxide encapsulation formed by surface segregation of Cr in dilute Cu-10-30 at.%Cr alloys at 400°C, solving the problems of chemical reactivity during the plasma deposition, diffusion, poor adhesion to the substrate, and oxidation. The performance of self-passivated Cu bottom-gate thin-film transistors (TFT's) and their stability during thermal bias stress testing is comparable to that of Cr-gate reference TFT's. The gate line resistivity (including encapsulation) is 4.5 μΩ·cm at present     

Degradation due to electrical stress of poly-Si thin filmtransistors with various LDD lengths

The degradation phenomena of polycrystalline silicon (poly-Si) thin film transistors (TFT's) with various lightly-doped drain (LDD) length have been investigated. It is observed that the threshold voltage shift due to electrical stress varies with LDD length. The threshold voltage shift after 4 hours electrical stress of V_g=V_d =30 V in conventional, 0.5 μm, and 2 μm LDD poly-Si TFT's are about 2.7 V, 5.2 V, and 0.8 V, respectively     

Characteristics of polysilicon thin-film transistor with thin-gatedielectric grown by electron cyclotron resonance nitrous oxide plasma

Polysilicon thin-film transistors (poly-Si TFT's) with thin-gate oxide grown by electron cyclotron resonance (ECR) nitrous oxide (N₂ O)-plasma oxidation is presented. ECR N₂O-plasma oxidation successfully incorporates nitrogen atoms at the SiO₂/poly-Si interface, consequently forms a nitrogen-rich layer with Si≡N bonds at a binding energy of 397.8 eV. ECR N₂ O-plasma oxide grown on poly-Si films shows higher breakdown fields than thermal oxide. The fabricated poly-Si TFT's with N₂ O-plasma oxide show better performance than those with ECR O₂ -plasma oxide, which results not only from the smooth interface but also oxygen- and nitrogen-plasma passivation     

A comparison of hydrogen and deuterium plasma treatment effects onpolysilicon TFT performance and dc reliability

We compare the performance and dc reliability of conventional top-gate, self-aligned polysilicon (poly-Si) thin-film transistors (TFT's) after passivation by plasma deuteration and conventional plasma hydrogenation. An optimum deuteration temperature of 300°C is found, as compared to 350°C for hydrogenation. Deuteration yields comparable TFT performance as hydrogenation, while deuterated TFT's exhibit increased resistance to threshold voltage degradation under dc stress. These results indicate that deuteration is a promising alternative to hydrogenation for achieving high-performance, high-reliability poly-Si TFT's for applications such as flat-panel displays     

Characteristics of PBTI and Hot Carrier Stress for LTPS-TFT With High- $kappa$ Gate Dielectric

In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with gate dielectric are well investigated for the first time. Under room temperature stress condition, the. PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for LTPS-TFT. In addition, an abnormal behavior of the degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of device's performance under high-temperature stress condition can be attributed to the damages of both the gate dielectric and the poly-Si grain boundaries.     

Stability of N-channel polysilicon thin-film transistors with ECRplasma thermal gate oxide

The effects of electrical stress on n-channel polysilicon thin-film transistors (poly-Si TFTs) with electron cyclotron resonance (ECR) plasma gate oxide have been investigated. The plasma-hydrogenerated low-temperature (⩽600°C) TFT's exhibited very a small increase of threshold voltage (ΔV_th<0.3 V) under the stress conditions (V_gs=15 V, V_ds=0 V ~15 V, and stress time=5×10⁴ s). The ΔV_t h was larger for the stress in the linear region than in the saturation region. It was found that the device degradation for the stress in the saturation region was caused by the hot-carriers. Increase of OFF current was maximum for the stress at V_gs=V_ds while for the stress at V_gsds, degradation of transconductance was the dominant effect seen     

A novel ultrathin elevated channel low-temperature poly-Si TFT

A novel ultrathin elevated channel thin-film transistor (UT-ECTFT) made using low-temperature poly-Si is proposed. The structure has an ultrathin channel region (300 Å) and a thick drain/source region. The thin channel is connected to the heavily doped drain/source through a lightly doped overlapped region. The lightly doped overlapped region provides an effective way to spread out the electric field at the drain, thereby reducing significantly the lateral electric field there at high drain bias. Thus, the UT-ECTFT exhibits excellent current saturation characteristics even at high bias (V_ds=30 V, V_gs=20 V). Moreover, the UT-ECTFT has more than two times increase in on-state current and 3.5 times reduction in off-state current compared to conventional thick channel TFT's