BE-SONOS flash memory along with metal gate and high-k dielectrics in tunnel barrier and its impact on charge retention dynamics

We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO₃/HfAlO/SiO₂. These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon(BE-SONOS). In the proposed structure HfAlO and AlLaO₃ replace Si₃N₄ and the top SiO₂ layer in a conventional oxide/nitride/oxide(ONO) tunnel stack. Due to the lower conduction band offset(CBO) and high permittivity of the proposed material in the tunnel layer, it offers better program/erase(P/E) speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high-k materials while scaling, for the same equivalent oxide thickness(EOT). We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4%(at room temperature) after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time.     

Soft breakdown of MOS tunnel diodes with a spatially non-uniform oxide thickness

The effect of electric stress on the characteristics of Al/SiO₂/p⁺-Si MOS tunnel diodes (d_ox=2.5–3 nm) is studied. Along with the gradual current changes, superimposed by the soft-breakdown-related steps, a non-trivial abrupt decrease in current is also revealed during the constant voltage stress. The latter occurred predominately under high bias and may be considered as an unusual appearance of the same soft breakdown events. In case of substantial spatial oxide thickness deviation, this effect is important even if it occurs within a small area.     

Scaling of multidielectric nonvolatile SONOS memory structures

Present-day low-power, portable lap-top computers and consumer products require non-volatile semiconductor memory (NVSM) operating at 5 V with a trend towards reducing this level to 3.3 V. The SONOS technology, an acronym for the polySilicon-blocking Oxide-Nitride-tunnel Oxide-Silicon structure used in capacitors and transistors, shows promise as a technology for present and future low voltage NVSM applications. The nitride layer in the dielectric sandwich permits the storage of charge resulting in adjustable threshold voltages. This paper examines the physics and characterization of scaled SONOS NVSM transistors in relation to reducing the programming voltage. We develop a model for the transient characteristics of the SONOS NVSM transistor with: (1) a simple closed-form solution valid for short programming times; and (2) a numerical solution covering the entire range of programming times. The simple closed-form solution clearly illustrates the dependence of the turn-on time and erase/white slope on the dielectric thicknesses, initial stored charge in the nitride, and programming voltage. In particular, we have examined: (1) decreasing the tunnel oxide thickness; and (2) scaling the blocking oxide thickness. By properly scaling the dielectric films (11 Å tunnel oxide, 50 Å nitride, 40 Å blocking oxide), a ±8 V programmable SONOS device has been obtained with a 50 μs write time and a 100 μs erase time for a 3 V memory window, and a ±5 V programmable device with a 100 ms erase and write time for a 1.5 V memory window.     

MOS capacitor loaded frequency agile microstrip antenna

A new MOS capacitor loaded frequency agile microstrip patch antenna is proposed in which the operating frequency of the rectangular microstrip antenna is electronically controlled by the bias voltage of the MOS capacitor. Theoretical investigations, based on a modal expansion cavity model as well as an improved theory of Richards et al. (1981, IEEE Transactions on Antennas and Propagation, 29, 38-41), are carried out for five different oxide (Si₃N₄) thicknesses from 100 Å to 500 Å for the (Au-Si₃N₄-Si) MOS structure. The maximum obtainable frequency tuning range (76.08%) is achieved for the lowest value of oxide thickness (100 Å); this is almost 1.5 times the value reported for the varactor loaded patch antenna. The larger frequency variation is achieved with lower variation in the bias voltage as compared with the varactor.     

Conduction mechanisms of silicon oxide/titanium oxide MOS stack structures

During the last years, high-k dielectrics have been studied intensively looking for an alternative material to replace the SiO₂ films as gate dielectric in MOS transistors. Different materials and structures have been proposed. An important concern not yet solved, is the interfacial quality between high-k materials and silicon substrate. For this reason, stack structures with SiO₂ as an interfacial layer between silicon substrate and high-k film have been studied. In this contribution we analyze the main conduction mechanism observed in SiO₂/TiO₂ MOS stack structures obtained by room temperature plasma oxidation in different conditions and reactors. Films fabricated in a parallel-plate type reactor showed better quality with low current density where thermionic conduction mechanism is predominant. In lower quality films, for example those fabricated in a barrel type equipment, the current density is higher and the conduction mechanism observed is Poole–Frenkel. Finally we show that the presence of thermionic mechanism provides a weak thickness dependence and a strong current density reduction with respect to silicon oxide MOS structures with the same equivalent oxide thickness.     

Performance improvement of flash memory using AlN as charge-trapping Layer

Potential of high-k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si₃N₄) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of high-k dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high-k AlN films with SiO₂ as a blocking oxide in p-Si/SiO₂/AlN/SiO₂/poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented.     

Surface-state spectra from thick-oxide MOS tunnel junctions

The conductance and capacitance of thick-oxide MOS tunnel junctions (SiO₂ thickness $\text{40～65}\text{A}\text{?}$)have been measured from 35 Hz to 210 kHz. It is demonstrated that the use of a thick-oxide MOS tunnel junction enables one to obtain the surface-state data throughout the whole silicon band-gap with better resolution and better sensitivity than the conventional MOS capacitance techniques. A slight departure from equilibrium may occur in the voltage range where large tunnel current flows. Corrections to the energy scale must be made in this voltage range. A method for the evaluation of the junction quality is discussed. The simplified equivalent circuits necessary for the calculation of surface-state data are constructed under various bias conditions by an approach different from a previously published work. The present work supports the model that at least some of the observed surface states are a consequence of the diffusion of contact metals into the oxide.     

Non-volatile memory based on silicon nanoclusters

Write/erase and charge retention characteristics of a memory element for the electrically programmable read-only memory based on the silicon/oxide_l/oxide_2/silicon_dot/oxide/semiconductor structure were simulated. An alternative high-κ dielectric (ZrO₂) was used as a blocking oxide and the second tunnel oxide. A thin low-κ dielectric (SiO₂) was used as the first tunneling oxide. Due to such a configuration, injection characteristics of tunneling SiO₂ in the write/erase mode can be significantly improved; hence, the response rate and injected charge can be increased. At the same time, the use of the sufficiently thick blocking and second tunneling layers allows injected charge retention for a long time. Programming by a pulse 10 ms long with an amplitude of ±11 V makes it possible to obtain a memory window of ～6 V in 10 years.     

Influence of ISSG tunnel oxide with decoupled plasma nitridation on erase characteristic of NOR-type floating-gate flash memories

This paper investigated the influence of ISSG (in situ steam generation) tunnel oxide layer with decoupled plasma nitridation (DPN) on the erase reliability of NOR-type floating-gate flash memory devices. The experimental results demonstrated that the tunnel oxide with ISSG process achieves better thickness uniformity and higher breakdown voltage than that with conventional dry oxidation process. However, the erase performance of flash cells was significantly degraded when DPN was applied to the ISSG oxide. The higher bulk nitrogen content from DPN process could lead to more bulk traps generation by substituting the strong Si–O bonds for the weak Si–N bonds in the tunnel oxide. During program/erase cycling, the more electrons trapped in the bulk tunnel oxide the less the FN erase electric field will be, which is responsible for the degradation of erase performance.     

Nonvolatile Memory Effect in Indium Gallium Arsenide-Based Metal–Oxide–Semiconductor Devices Using II–VI Tunnel Insulators

This paper reports the successful use of ZnSe/ZnS/ZnMgS/ZnS/ZnSe as a gate insulator stack for an InGaAs-based metal–oxide–semiconductor (MOS) device, and demonstrates the threshold voltage shift required in nonvolatile memory devices using a floating gate quantum dot layer. An InGaAs-based nonvolatile memory MOS device was fabricated using a high-κ II–VI tunnel insulator stack and self-assembled GeO _x -cladded Ge quantum dots as the charge storage units. A Si₃N₄ layer was used as the control gate insulator. Capacitance–voltage data showed that, after applying a positive voltage to the gate of a MOS device, charges were being stored in the quantum dots. This was shown by the shift in the flat-band/threshold voltage, simulating the write process of a nonvolatile memory device.     

Multilevel charge storage in Si nanocrystals arranged in double-dot-layers within SiO2

We investigated charging/discharging characteristics of a MOS structure with two layers of Si-nanocrystals (NCs) embedded in the SiO₂ dielectric. The two-dimensional (2D) arrays of nanocrystals, of sizes 3 and 5 nm in the lower and upper NCs layer, respectively, were fabricated by low pressure chemical vapor deposition (LPCVD) of amorphous Si (a-Si), followed by oxidation/annealing. The tunnel oxide was 3.5 nm thick. Successive charging of the NCs layers by both electrons and holes injected from the substrate was clearly demonstrated by the observed steps in the flatband voltage shift (ΔV_FB) as a function of the applied positive (electrons) or negative (holes) pulses on the gate, thus opening the potential for multiple bit operation of the memory. Discharging of the structure by pulses of opposite sign was consistently obtained. The current-voltage (I-V) curves exhibited two transient peaks at voltages corresponding to the two steps in ΔV_FB vs. V_gate that were attributed to a displacement current from the substrate to the nanocrystal layers. Clear improvement of charge retention in the double-nanocrystal layer structure compared to the single one was obtained, opening the possibility for lowering the gate oxide thickness of the NC memory without compromising device reliability.     

Stack engineering of TANOS charge-trap flash memory cell using high-κ ZrO2 grown by ALD as charge trapping layer

ZrO₂ with a κ value of 30 grown by atomic layer deposition has been integrated as charge trapping layer alternative to Si₃N₄ in TANOS-like memory capacitors, with Al₂O₃ as blocking oxide, SiO₂ as tunnel oxide and TaN metal gate. The fabricated device featuring 24 nm ZrO₂ exhibits efficient program and erase operations under Fowler-Nordheim tunneling when compared to a Si₃N₄ based reference device with similar EOT and fabricated under the same process conditions. The effect of stack thermal budget (900-1030 °C range) on memory performance and reliability is investigated and correlated with physical analyses. Finally, scaling ZrO₂ down to 14 nm allows program and erase at lower voltages, even if the trapping efficiency and retention of these device need further improvements for the integration of ZrO₂ in next generation charge trapping nonvolatile memories.     

Embedded HIMOS(R) flash memory in 0.35 μm and 0.25 μm CMOStechnologies

In this paper, the performance and reliability characteristics of the 0.35 μm/0.25 μm High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler-Nordheim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 μm CMOS technology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS(R) cell exhibits a high degree of flexibility and scalability. A fast programming operation (10 μs) at 3.3 V supply voltage is combined with an endurance of well over 100000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125°C. Furthermore, the cell has been scaled to a 0.25 μm version, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V     

BE-TANOS: Feasibility and technology limitations

The aim of this work is to investigate the physical mechanisms behind the write/erase and retention performances of band gap engineering (BE) layers used as tunnel oxide in charge trap memory stack. The investigation of the BE layers alone will be completed with the analyses of its integration within a TANOS (TaN/Alumina/Nitride/Oxide/Silicon) stack, pointing out the correlation between electrical performance and reliability limits.Good write/erase/retention performances can be achieved with BE tunnel oxide by using silicon nitride layer integrated in SiO₂-Si₃N₄-SiO₂ stack, as long as all different mechanisms are taken into account in optimizing stack composition: hole injection which improves erase efficiency, charge trapping and de-trapping from the thin silicon nitride which causes program instabilities and initial charge loss which does not significantly impact long term retention. All these phenomena make very crucial the BE tunnel process control and difficult its use for multi-level application.     

SiO2隧穿层不同气氛氮化退火对MONOS存储器性能的改善

Metal–oxide–nitride–oxide–silicon(MONOS)capacitorswiththermallygrownSiO2asthetunnellayer arefabricated,andtheeffectsofdifferentambientnitridation(NH3,NOandN2O)onthecharacteristicsofthememory capacitors are investigated.The experimental results indicate that the device with tunnel oxide annealed in NO ambient exhibits excellent memory characteristics,i.e.a large memory window,high program/erase speed,and good endurance and retention performance(the charge loss rate is 14.5%after 10 years).The mechanism involved isthatmuchmorenitrogenisincorporatedintothetunneloxideduringNOannealing,resultinginalowertunneling barrier height and smaller interface state density.Thus,there is a higher tunneling rate under a high electric field and a lower probability of trap-assisted tunneling during retention,as compared to N2O annealing.Furthermore,compared with the NH3-annealed device,no weak Si–H bonds and electron traps related to the hydrogen are introduced for the NO-annealed devices,giving a high-quality and high-reliability SiON tunneling layer and SiON/Si interface due to the suitable nitridation and oxidation roles of NO.     

Edge Profile Effect of Tunnel Oxide on Erase Threshold-Voltage Distributions in Flash Memory Cells

The erase threshold-voltage (VT) distribution in Flash electrically erasable programmable read-only memory cells was investigated versus the tunnel oxide edge profiles in self-aligned shallow trench isolation (SA-STI) and self-aligned poly (SAP) cells. The capacitive coupling with offset voltage correction is transcribed into VT transient for simulating erase VT dispersion without numerous full structure device simulations. It is shown that SAP gives rise to smaller VT dispersion, compared with SA-STI. The VT dispersion resulting from variations in dielectric thickness and oxide edge profiles is shown to fall far short of observed VT distribution, calling for examination of additional process and cell parameters     

Stress-induced leakage current of tunnel oxide derived from flashmemory read-disturb characteristics

This paper describes the characteristics of the stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics. The following three items were newly observed. First, the threshold voltage shift (ΔV_th) of the memory cell under the gate bias condition (read disturb condition) consists of two regions, a decay region and a steady-state region. The decay region is due to both the initial trapping or detrapping of the carriers in the tunnel oxide and the decay of the stress-induced leakage current of the tunnel oxide. The steady-state region is determined by the saturation of the stress-induced leakage current of the tunnel oxide. Second, the read disturb life time is mainly determined by the steady-state region for the oxide thickness of 5.7-10.6 nm investigated here. Third, a high-temperature (125°C) write/erase operation degrades the steady-state region characteristics in comparison with room temperature (30°C) operation. Therefore, accelerated write/erase tests can be carried out at higher operation temperatures     

Improvement of oxide thickness determination on MOS structures using capacitance–voltage measurements at high frequencies

It is well known that capacitance–voltage (C–V) measurements provide a simple determination of oxide thickness, but with the scaling down of components the classical method is not appropriated any more. We have observed that for two devices with the same oxide thickness and different surfaces, the classical method is accurate for large area but it is not adapted for the small one. We present a new procedure to make an accurate electrical determination of the oxide thickness on metal-oxide-semiconductor (MOS) structures of low dimensions in U.L.S.I. technology. Our method does not require a measurement in strong accumulation. It is based on C–V measurements at frequencies higher than 1 MHz associated to a non-linear optimisation of the experimental and theoretical band bending versus bias voltage curve (Ψ_S=f(V_g)), in the depletion mode. By this way, a corrective factor is estimated with precision in order to make an accurate determination of the oxide thickness value. We show that the frequency associated to the non-linear optimisation of Ψ_S=f(V_g) is function of the MOS device dimensions and is increased when the surface decreases. The experimental results obtained on low-dimension MOS structures and different oxide thickness are precise and in total agreement with those measured by ellipsometry. By using our new procedure the accuracy of oxide thickness determination is improved.     

Current-voltage characteristics of Al/SiO2/p-Si MOS tunnel diodes with a spatially nonuniform oxide thickness

The effect of nonuniform distribution of the insulator thickness on the behavior of Al/SiO₂/p-Si MOS tunnel structures with a (1–4)-nm-thick insulator is studied. The character and magnitude of the effect depend on the applied bias. In any conditions, the nonuniformity of the SiO₂ thickness enhances the total through currents as compared to those flowing across a uniform oxide layer of the same nominal thickness. Further, the potential of the inversion layer changes in the inversion mode. The calculations performed take into account the tunnel transport between the Si conduction band and the metal, that between the Si valence band and the metal (including in the inversion mode, the resonant transport, which is less clearly pronounced because of the thickness nonuniformity), and the band-to-band tunneling in the semiconductor.     

A new write/erase method to improve the read disturbcharacteristics based on the decay phenomena of stress leakage currentfor flash memories

This paper describes a new write/erase method for flash memory to improve the read disturb characteristics by means of drastically reducing the stress leakage current in the tunnel oxide. This new write/erase operation method is based on the newly discovered three decay characteristics of the stress leakage current. The features of the proposed write/erase method are as follows: 1) the polarity of the additional pulse after applying write/erase pulse is the same as that of the control gate voltage in the read operation; 2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower than that of a control gate in a write operation; and 3) an additional pulse is applied to the control gate just after a completion of the write/erase operation. With the proposed write/erase method, the degradation of the read disturb life time after 10⁶ write/erase cycles can be drastically reduced by 50% in comparison with the conventional bipolarity write/erase method used for NAND type flash memory. Furthermore, the degradation can he drastically reduced by 90% in comparison with the conventional unipolarity write/erase method fur NOR-, AND-, and DINOR-type flash memory. This proposed write/erase operation method has superior potential for applications to 256 Mb flash memories and beyond