Electrical overstress and electrostatic discharge

Semiconductor devices have a limited ability to sustain electrical overstress (EOS). The device susceptibility to EOS increases as the device is scaled down to submicron feature size. At present, EOS is a major cause for IC failures. Published reports indicate that nearly 40% of IC failures can be attributed to EOS events. Hence, EOS threats must be considered early in the design process. For semiconductor devices, EOS embodies a broad range of electrical threats due to electromagnetic pulses, electrostatic discharge (ESD), system transients, and lightning. EOS-related failures in semiconductor devices can be classified according to their primary failure mechanisms into: thermally-induced failures, electromigration, electric-field-related failures. In general, thermally-induced failures are related to the doping level, junction depth, and device characteristic-dimensions whereas electric-field induced failures are primarily related to the breakdown of thin oxides in MOS devices     

Experiences on reliability simulation in the framework of the PROPHECY project

Electromigration and oxide time dependent dielectric breakdown simulations based on library elements of a 0.35 μm CMOS technology have been performed. In the case of hot carrier degradation simulations as well as experiments using 99-stage ring oscillators of the same 0.35 μm CMOS technology have been carried out and compared. The frequency behaviour as a function of supply voltage and temperature has been investigated. Relaxation effects on the ring oscillators have been found. These effects are not covered by the reliability simulation tool. In a certain region of supply voltage and operation time the results of simulations could be confirmed by experiments. In all other cases the measured frequency degradation was smaller than the simulated degradation.     

CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage

A robust CMOS on-chip ESD protection circuit is proposed, which consists of four parasitic lateral SCR devices with low ESD trigger voltages to protect NMOS and PMOS devices of the internal circuits against the ESD pulses with both positive and negative polarities with respect to either VDD or VSS(GND) nodes. For each ESD stress with positive or negative polarity, there is an efficient and direct shunt path generated by the SCR low-impedance latching state to quickly bypass the ESD current. Thus, this four-SCR ESD protection circuit can perform very efficient protection in a small layout area. Since there is no diffusion or polysilicon resistor in the proposed ESD protection circuit, the RC delay between each I/O pad and its internal circuits is very low and high-speed applications are feasible. The experimental results show that this four-SCR protection circuit can successfully perform very effective protection against ESD damage. Moreover, the proposed ESD protection circuit is fully process-compatible with n-well or p-well CMOS and BiCMOS technologies.     

Software maintenance during system testing: enhanced methods forthe System X project

The author describes improvements introduced during 1986 to the development process for the System X project, a large-scale stored-program-control telephone exchange system. Attention is given to improvements within the system testing phase of the life cycle, in particular, the methods whereby subsystem developers provide solutions to software problems identified by the system testing engineers. Software maintenance can be performed either by fixing the software object code or by editing and recompiling the software source code. The adoption of the latter approach as the standard means of maintaining software during system testing has necessitated the generation of novel management, technical, and quality procedures. This approach is now also being applied to maintenance of the in-service product     

A new gas discharge device for electrostatic printing

A new gas discharge device for electrostatic printing is described, which is flat in shape, simple in structure, and has inherent scanning capability. As a glow discharge is sequentially transferred in the device, voltage pulses are generated from the discharge spaces and fed to recording styluses one after another. These voltage pulses are applied to the dielectric coating of the electrostatic recording paper and form latent electrostatic images on the dielectric coating in response to recording signal voltages applied simultaneously to the back side of the paper. A facsimile receiver employing the device has satisfactorily recorded facsimile signals at a rate of 9000 picture elements per second.     

Numerical modeling of electrostatic discharge generators

The discharge current and the transient fields of an electrostatic discharge (ESD) generator in the contact mode are numerically simulated using the finite-difference time-domain method. At first the static field is established. Then the conductivity of the relay contact is changed, which initiates the discharge process. The simulated data are used to study the effect of design choices on the current and fields. They are compared to measured field and current data using a multidecade broadband field and current sensors. The model allows accurate prediction of the fields and currents of ESD generators, thus it can be used to evaluate different design choices.     

二次静电放电仿真与实验研究

二次静电放电（secondary electrostatic discharge，SESD）是一种由一次静电放电引起的发生在仪器内部微小缝隙间的击穿放电现象，可对晶体管等很多元件造成破坏.文章首先搭建由静电放电模拟电路、二次放电模拟电路和电流靶电路组成的电路级仿真模型，初步探索SESD的波形，并与初始模型进行对比分析，验证已知的理论.其次基于实验研究与数据分析的方法，总结二次放电波形特点、峰值特性和时延特性.研究表明:二次放电电流峰值大于一次放电电流峰值，且受放电电压、放电时延等参数影响；二次放电的时延呈正态分布.这一研究结果符合并验证了目前对二次放电微观过程研究所得出的相关理论.     

静电放电测试仪低气压控制系统设计与研究

为了在静电放电测试仪中定量研究不同气压对非接触静电放电的影响,以STM32为核心设计了低气压自动控制系统,包含LCD、触摸屏、信号采集、驱动电路等硬件模块。分析控制系统的数学模型,针对系统非线性、时变性的特点设计以自适应模糊PID为核心的控制算法。由于控制系统的执行元件质量流量控制器输出受限易产生积分饱和,采用遇限削弱积分法对控制算法进行改进。通过Malab对改进后的自适应模糊PID和PID的控制过程进行仿真,结果表明自适应模糊PID控制具有更好的动态性能。     

Modeling and measurement approaches for electrostatic discharge in semiconductor devices and ICs: an overview

Electrostatic charges can be generated everywhere. When they are discharged through semiconductor devices and integrated circuits, an event called an electrostatic discharge (ESD), failure of electronics systems using these devices and ICs can occur. This paper first gives an overview of the ESD sources and models. Then the emphasis is placed on the modeling and measurements of the most commonly used of these models called the human body model (HBM). Various HBM protection circuits are examined to look at ways of preventing ICs from being damaged should ESD events occur. The issue of HBM measurements is also addressed so that the rapid transient associated with this ESD model can be accurately measured and characterized.     

Partial discharge testing of solder fillets on PCBs in a partial vacuum: new experimental results

This work investigates the influence on the partial discharge (PD) onset due to the geometry of solder fillets of aerospace and spacecraft component assemblies operating in vacuum and at high voltages. An automatic measuring system has been developed and calibrated to detect PD signals in vacuum (proportional to the apparent charge) which are recorded and displayed in terms of amplitude and temporal distributions. The experimental part of the project is aimed at investigating the influence of the geometry of solder fillets (produced according to the European space industry standard, ECSS-Q-70-08), on the occurrence of PD activity. Stranded terminals of high voltage cables were soldered to circular copper pads on FR4 fiberglass epoxy printed circuit board (PCB). Various copper electrode configurations have been produced and, prior to the test program, they were characterized for dimensional, electrical and optical properties. Two types of solder fillet geometries have been realized for each electrode configuration: round joints with an abundance of solder and sharp pointed joints made with minimal solder. The minimum distance between electrodes for all samples is nominally 5 mm. Paschen-like curves were established from measurements performed where the product of pressure x distance lies in the range of 2 mbar mm-50 mbar mm. Corona inception voltage (CIV) and corona extinction voltage (CEV) values were recorded at different values of pressure x distance. Stable glow discharge triggering voltage and current were also measured. The experimental results indicated that the PD activity for the sharp pointed pads and sharp pointed joints is greater than the other cases, but no significant differences (less than 50 V) of the values of CIV and CEV have been found.     

New fast turn-on speed SCR device for electrostatic discharge protection

A new SCR with the variation lateral base doping (VLBD) structure (VSCR) is proposed to improve the turn-on speed for electrostatic discharge (ESD) protection. The turn-on speed of the SCR was determined mainly by the base transit time of the parasitic p-n-p and n-p-n transistors of the SCR, and the VLBD structure can reduce the base transit time of the bipolar transistors to improve the turn-on speed of the SCR. The experimental and simulation results show that the turn-on time of the VSCRs with the VLBD structure is 12% less than that of the MLSCR with the traditional uniform base doping without adding extra process masks and increasing the chip area.     

电子计价秤抗静电放电问题分析

静电的产生具有隐蔽性、潜在累积性,可能会造成电子产品工作异常、损坏,甚至引发其他的安全问题.在研发阶段应对电子秤产品进行静电放电抗扰度试验,分析并验证各种整改措施,为电子秤的后期开发提供必要的参考和依据.采用标准的试验设备、环境及操作,对电子秤分别进行接触放电和空气放电试验.结果表明:易受影响的关键模块为A/D转换器,产品的开发应着力于其选型和电路设计.     

人体静电放电参数对带电电压的依赖关系研究

在带电电压为200～3000V的范围内测量了带电人体放电电流和上升时间,计算了其他放电参数;研究了放电参数与电压和电板速度的相关性.将RampeWeizel定理用于空气中带电人体的小间隙静电放电模型.观察发现在电压为800V时放电参数在电极运动速度影响下出现临界值.当电压高于1000V,或低于600V时,电极移动速度对放电参数的影响出现降低的趋势.     

微小间隙静电放电中两种放电模式的影响研究

设计实验讨论了被普遍认为是空气放电的带电体与受电体有相对运动速度的静电放电的参数变化性质。由于电极最终要碰触到放电靶上,所以,同时考虑接触放电模式的影响。在不同放电间隙情况下用静电放电发生器进行了实验,证实真实静电放电过程中存在两种放电模式。实验测量了在不同放电间隙状态下用静电放电发生器向靶运动放电的参数,分析了空气放电和接触放电对整个放电过程的作用影响。结果表明:有电极移动速度的静电放电应认为是接触放电与空气放电共同作用的综合放电过程。     

Designing power supply clamps for electrostatic discharge protection of integrated circuits

Power supply electrostatic discharge (ESD) clamping is needed to protect the IC power supply as well as to provide convenient discharge paths for ESD currents, and thereby simplify the total design problem. A variety of methods are reviewed and explored, notably those employing diodes or field effect transistor (FETs) built in bulk complementary metal-oxide semiconductor (CMOS) technology and avoiding avalanche behavior. Power clamping can occur across comparable power supplies or between a power supply and ground; there are diode and FET methods for each. Designs extend to clamping for mixed voltage supplies on a single chip, including power supplies above the gate oxide tolerance. New designs and results for power clamps based on PMOS FETs are presented for the first time.     

FDTD modelling of nonlinear spark in electrostatic discharge

An accurate numerical method for calculating nonlinear electrostatic discharges is presented. The method represents an improvement over the FDTD scheme in that it includes the arc model of Rompe and Weizel [1944]. Numerical results that demonstrate the validity and accuracy of the model are presented     

Accelerated dielectric breakdown and wear out standard testing methods and structures for reliability evaluation of thin oxides

This paper describes the various methods used for the assessment of the breakdown and wear out properties of thin oxides currently employed in CMOS and EEPROM technologies. Standard procedures for breakdown and wear out testing are given in conjunction with the associated test structures required for their accomplishment.     

Design and analysis of a NMOS triggered LIGBT structure for electrostatic discharge protection

A novel NMOS triggered LIGBT (NTLIGBT) structure is proposed for electrostatic discharge (ESD) protection in this paper. The structure utilizes internal NMOS to trigger SCR-like structure in LIGBT. The trigger voltage is significantly reduced because the embedded NMOS causes N⁺-drain/P-body junction being apt to avalanche breakdown. At the same time, the new parasitic PNP transistor including the newly added P⁺-region as a collector forms another path to bleed ESD current and then the conductivity modulation in the LIGBT is weakened. As a result, the holding voltage is increased. So, the proposed NTLIGBT structure has a narrow ESD design window. The simulation results show an improvement of 71.5% in trigger voltage and over 50% in holding voltage comparing with the conventional LIGBT structure.     

A novel on-chip electrostatic discharge (ESD) protection withcommon discharge line for high-speed CMOS LSIs

A novel on-chip electrostatic discharge (ESD) protection for high-speed CMOS LSI's that operate at higher than 500 MHz has been developed. Introduction of a newly developed common discharge line (CDL) can completely eliminate the protection device influence on the inner circuit operation. This enables minimization of the I/O capacitance by shrinking the dimension of the output transistor, which also serves as a protection device in conventional devices. This new protection (CDL protection) was applied to a high-speed DRAM of which I/O pin capacitance specification is 2 pF. As a result, the ESD tolerance of 4 kV for the charged device model test, 4 kV for the human body model test, and 700 V for the machine model test were obtained. In addition, the DRAM data rate higher than 660 MHz at room temperature was achieved. The results show significant improvement for both ESD and the I/O capacitance, compared with the conventional structure