An improvement of the interface properties of plasma anodized SiO2/Si system for the fabrication of MOSFET's

A new annealing process in chlorine ambient produced by passing argon through a CCl4container for reducing the interface states of the plasma anodized SiO2/Si system was developed. At optimum annealing conditions, the interface state density was reduced to about 1010states/eV . cm². Application of the oxide to the fabrication of MOSFET's shows that the devices obtained have lower threshold voltage and higher mobility than those fabricated with thermal oxidation in dry oxygen.     

Anodic Oxidation of Si in Oxygen/Chlorine Plasma

By adding a few percent of chlorine to oxygen plasma, the anodization rate of Si was enhanced; for example, the rate was doubled for oxygen containing 3-percent chlorine. With a chlorine concentration of 1.5 percent, the density of trap states at the Si-SiO/sub 2/ interface was reduced from 7 X 10/sup 11//cm/sup 2//spl dot/eV to 5 X 10/sup 11//cm/sup 2/ /spl dot/eV at the midgap of Si; after annealing at 800/spl deg/C in argon for 60 min, it was reduced to 8 X 10/sup 10//cm/sup 2//spl dot/eV, and did not return to the original value after heating the specimen to 800/spl deg/C. The density and capture cross section of traps in plasma-anodic oxide were also measured using the constant-current avalanche-injection method. The number of electron traps with small cross sections in plasma-anodic SiO/sub 2/ films was reduced by annealing them at 800/spl deg/C in argon, but SiO/sub 2/ films which were anodized in oxygen/chlorine plasma showed an increase of trap density under the same annealing condition.     

Dielectric loss and current—Voltage measurements in sodium-contaminated Si—SiO2—Cr structures

A detailed study of the small-signal ac response of ntentionally sodium-contaminated Si-SiO2-Cr structures has been made with mobile ion concentrations of 10¹⁰-10¹²ions/cm², in the frequency range of 0.05-100 Hz, between temperatures of 300 and 450°C. The time dependence of the observed relaxation phenomena, attributed to the existence of deep traps near the SiO2-Cr interface, is slow enough to consider the measured relaxation spectra as quasi static. The dc bias dependence of the relaxation mechanism, manifested by a loss maximum around 0.6 V and by a monotonic decrease of the absorption frequency with increasing bias, is ascribed to shallow traps located at the SiO2-Cr interface. The trapping as well as the long range migration of Na⁺ions in SiO2has been carefully studied by I-V and C-V measurements carried out on both contaminated and on ultraclean samples. The long-range motion of the ions leads to the thickness dependence of the relaxation time. However, since the ac response is determined in the two halves of the measuring cycle alternately by the migration of ions in the bulk of the SiO2and by their emission from the shallow traps, the relaxation time is also dependent on the effect of the traps. Consequently, the observed bias-dependent activation energies, ranging from 0.91 to 1.21 eV, may also be interpreted as intermediate values, arising from the conduction of Na⁺ions in SiO2films with an activation energy of less than 0.91 eV, and from the release of ions from the traps having activation energies equal to or greater than 1.21 eV.     

Device quality MOS Gate insulators: Sputter deposition and low temperature processing

A series of n-channel, Al-gate MOS transistors were fabricated using reactively sputtered SiO2as the gate insulator. The SiO2was deposited at low temperatures and low RF powers, and during subsequent processing was not subjected to temperatures in excess of 465°C. Test results showed that for gate oxides deposited at 20 W, the measured breakdown strength was 3-4 MV/cm with interface trapped charge density of 4-8 × 10¹⁰cm^-2and that the resulting electron mobility of the transistor was 470 cm²/V.s. After annealing in nitrogen at 1000°C, the deposited oxides exhibited electrical properties which are very similar to those of thermally grown SiO2.     

Tapered windows in SiO2by ion implantation

The enhanced etch rate of ion damaged SiO2has been used to controllably taper steps in thermally grown SiO2. A 50-keV Ar⁺implantation with a dose of 3 × 10¹³/cm²produces a uniform taper of 35-45° with no vertical step at the top edge of the window. These results are observed by viewing the sample on edge with a scanning electron microscope (SEM). The taper angle of the oxide varies from near vertical (90°) at a dose of 4 × 10¹²/cm²to very small angles at large dosages.     

Effects of subgrain boundaries on carrier transport in zone-melting-recrystallized Si films on SiO2-coated Si substrates

The transport properties of zone-melting-recrystallized Si films on SiO2-coated Si substrates have been studied by the fabrication and characterization of thin-film resistors and n-channel MOSFET's. Subgrain boundaries, which are the predominant crystal defects in the films, have a relatively low trapping state density (7-8 × 10¹¹cm^-2) and low resistance. N-channel MOSFET's fabricated in the films exhibit high surface electron mobilities (∼ 640 cm²/V-s) for electron transport either parallel or perpendicular to the subgrain boundaries.     

Relating computer simulation studies with interface state measurements on MIS solar cells

A lock-in-amplifier technique has been used to measure interface state density (NSS) values ranging from 2 × 10¹¹-3 × 10¹³states/cm². eV depending on energy in the gap, type of Si substrate, and choice of Schottky metal used in MIS diodes. Polycrystalline, ribbon, and     

Consideration of discrete interface traps in InGaAs/GaAs heterojunctions

Poisson's equation has been applied to model the capacitance-voltage (C-V) profile of a Schottky-barrier n-N heterojunction of Au/nIn0.1Ga0.9As/NGaAs. Interface traps, represented either as a box or sheet of charge, have been included in the calculation. Two electron accumulation peaks are observed. One, next to the region depleted of electrons, is related to the interface trap occupancy, and the other is related to the two-dimensional electron gas at the heterojunction. Qualitative agreement is obtained between the calculated and experimentally determined C-V electron profile (300 to 77 K) if a trap EC- 0.13 eV at a concentration -8 × 10¹⁰cm^-2in a 300-Å boxlike distribution is included in the calculation. For MBE grown nIn0.1Ga0.9As/NGaAs deep-level transient spectroscopy suggests that the interface traps are at EC- 0.13 and 0.17 eV with capture cross sections of about 2 × 10^-14and 1 × 10^-15is cm².     

Reduction in minority carrier storage effect by fluorine ion implantation damage

Damage is produced in p-n diodes by fluorine ion implantation to reduce minority carrier storage effect. The switching time, reverse leakage current, andI-Vcharacteristics were investigated for annealing temperature between 450°C and 650°C. The accelation energy is 130 keV and doses are 10¹³-10¹⁵/cm². Annealing causes restoration in switching time, but leakage current increases with annealing temperature rise for doses more than 1 × 10¹⁴/cm². The best diodes indicate 1.5-order reduction in switching time and 10 nA in reverse leakage current. These properties, caused by implantation damage, are retained after long-cycle annealing at 450°C and are expected to be stable under practical use. These diodes can be obtained by annealing at 450°C and they furnish satisfactory diode performance.     

C-V Characteristics of GaP MOS diode with anodic oxide film

Gallium phosphide was anodically oxidized in an aqueous H2O2solution and MOS diodes were fabricated by the evaporation of aluminum. The resistivity and electric breakdown strength were higher than 10¹⁴Ω.cm and 6 × 10⁶V/cm, respectively. Almost no frequency dispersion was observed in the C-V curves from 100 Hz to 1 MHz. The C-V curve showed the injection-type hysteresis. From the hysteresis window, the transferred charged carriers were estimated to be about 9 × 10¹¹/cm². By leaving the diode biased at negative voltage or by shining light with energy higher than 1.8 eV, the curve shifted to negative voltage direction. The results indicate that the density of the fast interface states which follow the 100-Hz signal is very low but there exist deep electron traps with activation energy higher than 1.8 eV near the surface in the oxide film and the shallower electron traps which cause the hysteresis in the dark.     

Electron and hole traps in SiO2 films thermally grown onSi substrates in ultra-dry oxygen

The densities of electron and hole traps in SiO₂ films, thermally grown on Si substrates in ultra-dry oxygen, were compared with those in SiO₂ films grown in pyrogenic steam (wet-oxide films). The results show that ultra-dry-oxide films have an undetectable density of electron traps that is less that 10¹¹/cm² , and little interface-states generation during carrier injection. However, hole traps in ultra-dry-oxide films are high, (2.6±0.1)×10¹²/cm² compared with (1.3±0.2)×10¹²/cm² in wet-oxide films, and these increase by a factor of two with post-oxidation anneal in ultra-dry Ar. The results of electron spin resonance measurements of E' centers in SiO₂ films are consistent with the results of electrical measurements. These suggest that there is a tradeoff correlation between the density of electron traps and hole traps, with respect to the amount of water- or hydrogen-related defects in SiO₂     

Antimony and arsenic segregation at Si-SiO2interfaces

The behavior of shallow Sb and As implants has been investigated in the vicinity of the Si-SiO2interface. The implants were performed through thin typically 10-nm oxides and then subjected to inert ambient annealing between 900 and 1000°C. It has been found that the diffusing dopants have an essentially unity sticking coefficient at the SiO2interface, until ∼ 2 × 10¹⁴/cm²is segregated. All indications are that the segregated Sb/As forms a single monolayer at the interface. The dopants in this layer are electrically inactive. Such a loss of active dopants must be taken into account in the design of submicrometer devices.     

Surface state and surface recombination velocity characteristics of Si-SiO2interfaces

A new device has been used to study the surface recombination velocity and surface state characteristics of Si-SiO2interfaces. The device consists of an epitaxially-formed junction diode. When the junction is forward-biased, minority carriers are injected from the heavily-doped substrate into the lightly-doped epitaxial region. The thickness of the epitaxial region is much less than the diffusion length for minority carriers. Thus, the diode current for a given junction forward bias is directly proportional to surface recombination velocity at the Si-SioO2interface. A gate electrode over the SiO2has been included to vary surface potential. Thus, this new device permits one to simultaneously study MOS capacitance-voltage characteristics as well as surface recombination velocity. The capacitance-voltage characterics indicate the surface states exhibit a quasi-continuous energy distribution. N-type surfaces exhibited donor levels lying in the range of ∼0.15 to ∼0.45 eV above the valence band; their density was found to vary from ∼5 × 10¹²to 5 × 10¹³states/cm²/eV. In contrast, p-type surfaces exhibited acceptor levels lying in the range of ∼0.15 to ∼0.45 eV below the conduction band; their density was comparable to those observed on n-type surfaces. The maximum value of surface recombination velocity was found to vary from 3 × 10³to > 10⁴cm/s. Surface recombination velocity was found to correlate directly with surface state density.     

An EEPROM cell using a low barrier height tunnel oxide

A new simple method to fabricate a thin oxide with low barrier height is proposed. An oxide is grown on a heavily implanted silicon substrate with As or P in excess of 5 × 10¹⁴/cm². When the oxide was grown in H2O + Ar gas after Ar annealing, the barrier height of the oxide conduction band with respect to the silicon conduction band decreased to 1.8 eV, about one half of the ordinary value of 3.2 eV. This phenomenon was applied to an EEPROM cell, which showed superior WRITE/ERASE characteristics. A moderately implanted As (2.5 × 10¹⁵/ cm²) sample shows excellent WRITE/ERASE endurance, over 10⁶cycles with 2-V Vthwindow, which could not realized by using an ordinary oxide.     

Reliability of MINP compared to MIS, SIS, and N/P silicon solar cells under 1.0-MeV electron and environmental effects

The effects of 1.0-MeV electron radiation are compared for MIS, SIS, N/P, and MINP silicon solar cells. MIS, SIS, and N/P silicon solar cells are comparable in performance except that SIS cells degraded faster due to use of n-type Si substrates. MINP cells exhibited superior performance in that efficiency degraded 9 percent at a fluence of 1 × 10¹⁵e^-/cm²and 32 percent at a fluence of 1 × 10¹⁶e^-/cm²compared to 29 percent and 49 percent, respectively, for N/P cells. MINP cells utilize an SiO2insulator layer over a thin N-region, and a low work function metal contact. This design gives a high ultraviolet response and low surface recombination velocity which maintains high efficiency since most of the radiation loss occurs in the infrared region due to bulk damage effects.     

Sodium distribution in thermal oxide on silicon by radiochemical and MOS analysis

Direct comparison has been made between Na distribution determined radiochemically and electrically in 6000 Å thermal oxide on 10Ω-cm n-type Si. Na withinsiml 1000Å of Si/SiO2interface correlates in most cases with MOS flat band voltage shift, i.e. NNa(siml 1000Å) ≈ +ΔQMOS. Appreciable Na, which does not appear to affect Si surface potential, is found through the bulk of the oxide. Neutron activation of "clean" oxide (grown in wet or dry oxygen) showed ∼1 ppm Na throughout, ∼10 ppm at free surface. Gold was also identified at ppm concentrations but did not correlate with ΔQMOS. The U-shaped profile seen after diffusion (300 to 1000°C in dry N2) or in-drift (∼200°C, 5 × 10⁵V/cm) is believed due to rate limitation at the free surface; electrostatic binding plus enhanced solubility at the Si/SiO2interface. Time dependence was observed in diffusion at 500 and 800°C, which is not expected from the fast diffusion of Na. This is also attributed to the surface rate limitation. The anion significantly affects Na diffusion kinetics and distribution in contamination experiments with radiotracer Na²⁴OH, Na²⁴Cl, and Na²⁴Br⁸². Br is found to accompany Na diffusion, suggesting anion neutralization of Na within the bulk oxide. P2O5. SiO2is seen to "getter" Na from the oxide. These results support the suggestion of Snow et al. that Na is responsible for uncontrolled drift of surface potential in oxidized Si devices.     

1 µm MOSFET VLSI technology: Part VIII—Radiation effects

In this paper the effect of electron-beam radiation on polysilicon-gate MOSFET's is examined. The irradiations were performed at 25 kV in a vector scan electron-beam lithography system at dosages typical of those used to expose electron-beam resists. Two types of studies are reported. In the first type, devices fabricated with optical lithography were exposed to blanket electron-beam radiation after fabrication. In the second, discrete devices from a test chip, fabricated entirely with electron-beam lithography, were used. It is shown that in addition to the threshold voltage shift, caused by the accumulation of radiation-induced positive charge in the gate oxides, these charged centers and additional uncharged (neutral) electron traps lead to an increase in the electron trapping in irradiated oxides. Temperatures above 550°C are shown to be required to anneal both the positive and neutral traps completely from the oxide underlying polysilicon after exposure to radiation. Annealing of the radiation-induced positive charge from the oxide is shown to depend on the metallurgy overlying the gate insulator during heat treatment. Annealing treatments which remove the charged centers from aluminum-gated MOS structures are demonstrated to leave small (about 5 × 10¹⁰cm^-2) but significant amounts of charge in certain polysilicon-gate structures. The dependence of positive and neutral trap densities on direct electron-beam exposure was studied in the range between 10 and 200 µC/cm². Studies on the electron-beam fabricated devices indicate that indirect exposure of the gate oxide by electrons scattered from the primary beam during lithography in areas away from the gate oxide is sufficient to cause appreciable damage. After postmetal annealing at 400° C for 20 min, the minimum residual charge density found in the electron-beam fabricated devices is 4 × 10¹⁰cm^-2.     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

Effect of the annealing conditions on the electrical characteristics of p+/n shallow junctions

Shallow p+/n junctions are produced by low-energy (10-keV) boron implantation into amorphous silicon layers formed by a prior implantation of Si+ ions. Junctions about 0.1 µm deep with good electrical characteristics (reverse current density Jr< 10^-7A/cm²at - 1 V) are obtained both by electron-beam annealing (1100°C, 2 s) and conventional furnace annealing (800°C, 30 min). It is shown that, in the case of the furnace treatment, lower annealing temperatures produce very high reverse currents, while excellent electrical characteristics (Jr< 10^-8A/cm²) are achieved at higher annealing temperatures (900°C), the junction extending, however, much deeper into silicon (0.26 µm).     

Radiation-hardened silicon-on-insulator junction field-effect transistors fabricated by a self-aligned process

A self-aligned process has been developed for fabricating JFET's in zone-melting-recrystallized (ZMR) Si films on SiO2-coated Si substrates. This process has been used to fabricate n-JFET's exhibiting transconductance values up to 63 mS/mm. For 228 devices within an area of about 4 × 4 cm², the mean threshold voltage is 578 mV and the standard deviation is 22 mV. With a -15-V bias applied to the Si substrate during irradiation and device operation, the devices show low threshold voltage shift (< -75 mV) and small transconductance degradation (∼30 percent) for exposure to total-dose radiation of 10⁸rad(Si).