Static RAM cell for ternary logic

A novel CMOS static RAM cell for ternary logic systems is described. This cell is based on the lambda diode. The operation of the cell has been simulated using the SPICE 2G program. The results of the simulation are given.     

抗辐射128kb PDSOI静态随机存储器

介绍在部分耗尽绝缘体上硅(PD SOI)衬底上形成的抗辐射128kb静态随机存储器.在设计过程中,利用SOI器件所具有的特性,对电路进行精心的设计和层次化版图绘制,通过对关键路径和版图后全芯片的仿真,使得芯片一次流片成功.基于部分耗尽SOI材料本身所具有的抗辐射特性,通过采用存储单元完全体接触技术和H型栅晶体管技术,不仅降低了芯片的功耗,而且提高了芯片的总体抗辐射水平.经过测试,芯片的动态工作电流典型值为20mA@10MHz,抗总剂量率水平达到500krad(Si),瞬态剂量率水平超过2.45×1011 rad(Si)/s.这些设计实践必将进一步推动PD SOI CMOS工艺的研发,并为更大规模抗辐射电路的加固设计提供更多经验.     

抗辐射128kb PDSOI静态随机存储器

介绍在部分耗尽绝缘体上硅(PD SOI)衬底上形成的抗辐射128kb静态随机存储器.在设计过程中,利用SOI器件所具有的特性,对电路进行精心的设计和层次化版图绘制,通过对关键路径和版图后全芯片的仿真,使得芯片一次流片成功.基于部分耗尽SOI材料本身所具有的抗辐射特性,通过采用存储单元完全体接触技术和H型栅晶体管技术,不仅降低了芯片的功耗,而且提高了芯片的总体抗辐射水平.经过测试,芯片的动态工作电流典型值为20mA@10MHz,抗总剂量率水平达到500krad(Si),瞬态剂量率水平超过2.45×1011 rad(Si)/s.这些设计实践必将进一步推动PD SOI CMOS工艺的研发,并为更大规模抗辐射电路的加固设计提供更多经验.     

高速双端口共享存储器 IDT7025及其应用

双端口共享存储器IDT7025是真正的双口存储单元,允许同一内存地址的同时存取.IDT7025为高速8K×16双口静态RAM,可用作单独的128K位双口RAM也可用作32位或者更多字系统的主从双口RAM的组合.它提供两个独立的口,这两个口可以单独控制、有独自的地址和I/O引脚,从而实现了对内存任何地址的独立的、异步的存取(读写).     

A dynamic RAM Cell in recrystallized polysilicon

A new, one-transistor, dynamic RAM cell has been fabricated in beam-recrystallized polysilicon. Placing thin oxides both above and below the storage region doubles the storage capacitance. Complete isolation of the storage region by oxides also reduces the susceptibility of the cell to soft errors from collection of charge injected into the substrate by the surrounding elements or by alpha particles. Long storage times are feasible, being limited only by the leakage of the access transistor. A thick oxide under the bit line reduces the bit-line capacitance, further increasing the ratio of storage capacitance to bit-line capacitance.     

New dynamic RAM Cell for VLSI memories

A novel high-alpha-particle-immunity and high-density dynamic RAM cell with readout signal gain is proposed. The cell is composed of a MOSFET for charge transfer, a MOS capacitor for charge storage and a junction FET (JFET) with buried channel under the MOS capacitor. The buried channel is dynamically switched according to whether there is charge-storage or not. The cell has extremely small collection efficiency for charges generated by alpha-particles, and allows a large amount of leakage charges due to its peculiar structure. Thus, it can achieve high packing density.     

A Novel JCMOS Dynamic RAM Cell for VLSI Memories

A high-density dynamic memory cell using the CMOS technology (JCMOS cell) is described. The cell is based on merging three different devices and occupies an area of a single MOS transistor. The cell consists of an enhancement surface MOSFET, a JFET, and a bipolar transistor. The data is stored on the MOS capacitor, sensed by the JFET, and written into the cell using the bipolar transistor. The cell simple processing, small size, high writing and reading speeds, very small leakage current, large readout signal (almost invariant to scaling), nondestructive reading, and suitability for scaling down to very small dimensions, make the JCMOS cell a very attractive candidate for future VLSI dRAM chips. The cell structure and lumped component equivalent circuit are presented. The cell principle of operation and its selective reading and writing are explained. The operation of the memory read/write circuitry is described and simulation results are presented. The cell performance and design considerations are discussed. A test cell was successfully fabricated to verify the cell operation and performance. Experimental results are presented.     

光电池的物理基础

为了指导光电池的研究和制造,本文从理论和实验角度,论证了以下三个问题:1.结型半导体电源,2.光电池电动势,3.太阳能电池三基本实验。     

模块化蓝光光存储性能静态测试系统

蓝光光存储是信息存储领域发展的一个重要方向。测试系统是研究蓝光光存储材料的必备条件，为建立蓝光光存储研究平台，设计和搭建了一套模块化蓝光光存储性能静态测试系统。激光工作波长为406．7nm。系统采用调制解调技术降低系统噪声，提高测量粘度：采用光点移动模式降低对样品尺寸的要求；采用纳米平台提高记录点的反复定位性能。实验结果证明测试系统性能良好，可以满足蓝光光存储性能静态测试要求。     

一种NMOS四值静态存贮单元的设计

<正> 一、引言 多值存贮器,尤其是用多值单元电路构成的多值存贮器是该领域需要研究的课题之一,其应用前景甚至超过了单纯多值电路的范围。关于多值ROM单元及由动态结构组成的多值存贮器已有一些报导,本文提出一种NMOS四值静态存贮单元电路。     

Ag-In-Te-Sb-O薄膜光学及短波长静态记录特性的研究

以Ag In Te Sb合金靶采用射频反应溅射在不同氧分压下制备了单层Ag In Te Sb O薄膜。对薄膜的反射光谱及光学常数 (n ,k)的研究结果表明 :在分压比PO2 /PAr =2 %～ 4%时制备的薄膜反射率较高 ,氩气保护下在30 0℃退火 30min后 ,在 5 0 0～ 70 0nm波长范围薄膜反射率增长可达 17%～ 2 5 % ;分压比PO2 /PAr=2 %时 ,薄膜在40 0～ 65 0nm波长范围有较强吸收 ,光学常数在退火前后也有较大差别。对薄膜静态记录性能的测试结果表明 :记录功率为 10mW ,脉宽为 10 0ns时 ,薄膜在记录前后反射率对比度高达 2 0 % ,具有良好写入灵敏性。连续多次进行写入 /擦除循环 ,擦除前后反射率对比度稳定 ,薄膜具有一定的可擦除性能。退火前后薄膜的X射线衍射 (XRD)结果说明退火后薄膜中仅有Sb的晶相 ,与Ag In Te Sb薄膜的结晶特性明显不同。薄膜的成分及各元素的化学状态用光电子能谱 (XPS)进行了分析。这类薄膜有望作为短波长高密度光存储材料。     

非晶硅太阳能电池的光学分析

我们采用一种新方法——光学导纳分析,把非晶硅太阳能电池看作由吸收膜和透明膜组成的多层膜系,计算了该膜系的光学导纳,分析了电池的光学性质。 电池吸收谱中存在干涉峰。通过考察各层膜光学参数对光吸收的影响,发现(ⅰ)高反射背接触的电池结构可增加0.6—0.7μm的吸收,(ⅱ)非晶硅膜厚能改变干涉峰在光谱中的位置;(ⅲ)减反膜(AR)与短波区的反射率密切相关,选择最佳AR膜厚能够减少反射损失;并且AR最佳膜厚几乎与非晶硅膜厚无关。     

A three-dimensional static RAM

A three-dimensional (3-D) 256-bit static random-access memory (RAM) with double active layers has been fabricated by using the laser recrystallization technique. Memory cells were located in a bottom active layer with an NMOS configuration and peripheral circuits were arranged in a top active layer with a CMOS configuration. Both active layers were connected by 112 via holes. The chip and cell sizes were 2.6 × 1.9 mm²and 50 × 70 µm², respectively. The memory operation was observed with a supply voltage from 4 to 8 V. The shortest address access time of 42 ns was obtained at the supply voltage of 8 V.     

内存技术发展趋势

随着市场上硬件技术的迅速发展,内存的研发也从EDO、PC-66 SDRAM发展到PC-100 SDRAM、PC-133 SDRAM,及DDR SDRAM、Direct Rambus DRAM,其目的在于提高内存的带宽(Bandwidth),以避免内存本身的带宽限制造成高速CPU运算的瓶颈。     

Static Gain, Optical Modulation Response, and Nonlinear Phase Noise in Saturated Quantum-Dot Semiconductor Optical Amplifiers

A rate equation model preserving charge neutrality for quantum-dot semiconductor optical amplifiers (QD-SOAs) is established to investigate the nonlinear gain dynamics in the saturation regime. The static gain of QD-SOA is calculated assuming overall charge neutrality and compared with that without overall charge neutrality. Optical modulation response and nonlinear phase fluctuation through saturated QD-SOAs are calculated numerically based on a small-signal analysis. The gain dynamics of QD-SOAs are strongly dependent on the current injection level. The carrier reservoir in the wetting layer and continuum state is necessary for QD-SOAs to operate with high gain, high saturation power, and ultrafast gain recovery.     

A transistorless-current-mode static RAM architecture

We propose a static memory architecture in which each bit consists of a single two-terminal device that is bistable in current. Current-mode operation of the memory array removes the need for cell-isolation transistors, thus, allowing huge increases in density over inverter-based SRAM and capacitor-based DRAM. Low power consumption and fast read/write speeds are ensured by taking advantage of the exponential nature of the memory's current-voltage characteristic     

The charge-coupled RAM cell concept

A new concept in MOS dynamic RAM cells is described and demonstrated. The charge-coupled RAM (CC RAM) cell combines the storage capacity and transfer gate of the one-transistor cell into a single gate. The resulting cell is simpler than the conventional one-transistor cell and possesses significant advantages in packing density and potentially higher yield. One of the variations of the CC RAM cell concept results in a cell whose operation is identical (voltage and timing) to that of the present one-transistor cell. In addition, the CC RAM cell fabrication is essentially the same as the present one-transistor cell process. The CC RAM is an attractive candidate for the next generation RAM's.