第十讲 红外系统弱信号前置放大器

在红外系统中,探测器把来自目标的弱辐射信号转换成微弱的电信号.为了不恶化探测器输出的信噪比,前置放大器的噪声必须很低,使红外系统的灵敏度主要由探测器输出的信噪比决定.本文在分析电阻性信号源晶体管放大器噪声特性的基础上,把探测器、偏置电路和前置放大器作为整体,导出偏置电路元件的选择原则和对第一级晶体管噪声特性的要求.介绍了几个用于实际红外系统中锑化铟(InSb)、碲镉汞(HgCdTe)、硫化铅(PbS)和钽酸锂(LiTa?3)等探测器的前置放大器电路.     

一款前置放大器的低噪声设计与分析

描述了有关放大器的噪声机理和特性,详细论述了前置放大器的低噪声设计步骤和过程,并根据晶体管的噪声特性曲线和噪声系数等值曲线对输入晶体管的偏置进行了理论计算。     

双极型晶体管AB类放大器偏置电路的设计

本文首先介绍了双极型晶体管在AB类工作状态下的一些固有特性，并对几种常用的偏置电路进行了分析，在此基础提出了一种能兼顾放大器各种主要性能指标的偏置电路设计方法。     

工作点稳定的偏置电路

前面叙述单管放大器的原理时已经指出:晶体管在静态时必须建立位于放大区中部的静态工作点Q,以使晶体管具有电流放大作用,并使交流信号输入时不会产生输出信号的失真,在放大电路中建立静态工作点,即产生直流偏置电流I_(BQ)与H_(CQ)的电路叫偏置电路。一、静态工作点不稳定的原因及对放大性能的影响:上面讲的单管放大器电路工作点是不稳定的,当环境温度上升,     

采用场效应晶体管的低噪声光电探测电路

光电二极管后接结型场效应晶体管的光电探测电路,可提供低频散粒噪声限性能。采用现有的微波场效应晶体管,散粒噪声限性能的频带宽可扩展到兆赫范围。低噪声光电探测器用光电二极管可探测的最小信号功率通常受放大器噪声,而不是光电二极管噪声的限制。不过,在光电二极管后接一个场效应晶体管放大器,可大大改进信噪比。对于临界频率f_c以下的频率,可获得散粒噪声限性能,所以,光电二极管与场效应晶体管组合就成了光电参量上变频器、光电倍增管及低频雪崩光电二极管的劲敌。在下面的讨论中,假定光电二极管接到共源组态的场效应晶体管的栅极上。参照图1,信噪比很容易计算。此图中,反向偏置光电二极管由结电容C_d与串联电阻R_s表     

基于InGaP/GaAs HBT工艺超宽带高线性度单片放大器

为解决传统达林顿结构的单片射频放大器线性度低和高低温下静态电流变化大的问题,设计了动态偏置电路和有源偏置电路来提高放大器的线性度和稳定静态电流.同时,为了扩展放大器的带宽和提高增益平坦度,设计了负反馈电路结构.基于2μm磷化镓铟/砷化镓异质结双极型晶体管(InGaP/GaAs HBT)工艺和达林顿结构,设计了单片微波放...     

双极晶体管LNA的分析与设计

低噪声放大器（LNA）在射频系统中是作为接收端的前端，其增益、噪声、非线性、匹配等性能对整个接收机至关重要。随着现代通信电子技术的发展，迫切需要低噪声、高增益、低偏置、小体积的射频放大器。我们利用Ansoft的设计软件designer，设计了用于1．5GHz的低噪声放大器，器件选用Philip公司的BFG425W双极晶体管，文章主要从共发LNA电路的噪声分析入手，通过对电路的分析与仿真，对其参数进行了优化，最后提出了几点改进的措施。     

温度传感器校准系统中红外信号检测电路设计

为了提高红外探测器检测红外微弱信号的精度,采用晶体管恒流偏置电路,使用低噪声高速运算放大器构成了前置放大电路。运用电路理论建立放大电路的噪声等效模型,采用叠加法计算1级放大输出端的噪声电压。通过中温黑体炉红外辐射实验,测试电路性能,取得了500℃~700℃时的电压波形,计算得出信噪比为7.25×103。结果表明,红外探测器前置放大电路达到高信噪比、响应速率快、抗干扰强的应用要求,可以对红外微弱信号检测放大。     

高速光传输用的低噪声光接收机

本文描述了用于高速光传输的硅双极晶体管低噪声光接收机的设计,研究了常用的共射一共集电极电路(CE-CC)和复合晶体管电路(带并联反馈的互阻抗放大器)。在400MHz带宽的情况下,为获得最小噪声电流,CE-CC的最佳集电极偏置电流是2.7mA,比复合晶体管电路的最佳电流1.2mA差。已经证明,复合晶体管电路的信噪比比CE-CC的信噪比约高1.5dB。锗雪崩光电二极管的低噪声复合晶体管光接收机,当速率为400Mb/s的归零(RZ)脉冲比特误码率为10~(-10)时,其灵敏度达到-41dBm,比普通的CE-CC接收机的光灵敏度改善2.5dB。     

晶体管放大器三种组态的En—In噪声分析与比较

准确评价晶体管三种组态的噪声性能是低噪声放大器电路组态优化设计的关键。本文在晶体管三种组态Ｅｎ－Ｉｎ噪声分析等方面给出了若干新结果。     

IF Amplifier using C/SUB c/ compensated transistors

An integrated bridge network of four transistors is used as a self-neutralized active element in tuned RLC amplifier designs. The bridge network compensates for the transistor collector-base junction capacitance (C/SUB c/), yielding a 95-percent reduction in the common-emitter reverse transmission admittance. IF amplifier stages that achieve the maximum unilateral power gain of a common-emitter transistor while maintaining excellent alignability are realized using the C/SUB c/ compensated transistor structure. Variations of the relative bias current levels of the transistors in the bridge network provides gain control by way of signal cancellation. This technique produces minimal frequency response variations of the amplifier stage being controlled. A noise analysis shows output signal to noise ratio at maximum attenuation can be a performance limitation.     

Instantaneous model of a MESFET for use in linear and nonlinearcircuit simulations

A formal approach for nonlinear modeling of FETs is presented. The intrinsic transistor is described by current and charge generators, that are instantaneously dependent on the two internal voltages. The extrinsic parasitic elements are also included. This instantaneous model is obtained from the small signal equivalent circuit computed at a number of bias points, by integration of the bias dependent elements. A program for using this model in nonlinear circuit analysis has been developed. The process has been carried out for two transistors, one being of low noise, and the other a power MESFET. Good agreement has been observed when comparing the nonlinear analysis with measured data. A solid-state power amplifier at 28 GHz has been designed using the power transistor, delivering 21 dBm at 1 dB compression point     

A table-based bias and temperature-dependent small-signal and noiseequivalent circuit model

A new algorithm is presented for construction of accurate table-based bias and temperature dependent field-effect transistor (FET) small-signal and noise models. The algorithm performs two-dimensional (2-D) linear interpolation on a single stored data table to quickly produce bias and temperature-dependent model simulations. Comparisons of simulated FET S-parameters, noise figure, and device figures of merit (e.g., G_max) versus measured data show the model to be accurate over a wide range of bias and temperatures. Model enabled simulations of a single-stage FET-based low-noise monolithic microwave integrated circuit (MMIC) amplifier are also shown to compare favorably with measured amplifier data. The new algorithm improves on previously available approaches in three ways: (1) it allows efficient and accurate small signal device and circuit simulations over bias and temperature; (2) it allows circuit optimization with respect to bias and temperature; and (3) it provides substantial data storage reduction over alternate approaches. Because one compact data table represents a single sample device, the approach can be readily adapted for use in a statistical FET model data base     

Effect of collector bias current on the linearity of common-emitter BJT amplifiers

Using a Volterra series,an explicit formula is derived for the connection between input 3rd-order intercept point and collector bias current(I_(CQ)) in a common-emitter bipolar junction transistor amplifier.The analysis indicates that the larger I_(CQ) is,the more linear the amplifier is.Furthermore,this has been verified by experiment.This study also integrates a method called dynamic bias current for expanding the dynamic range of an LNA(low noise amplifier) as an application of the analysis result obt...     

射频宽带低噪声放大器的设计与仿真

介绍了一种射频宽带低噪声放大器的设计过程,包括稳定性分析、偏置电路设计和匹配电路设计等内容.设计采用E-PHEMT晶体管(ATF-55143)器件模型和其他元件模型.通过采用ADS技术进行电路和电磁仿真,结果表明设计的放大器完全满足性能指标要求.     

Comparison of different high-linear LNA structures for PCSapplications using SiGe HBT and low bias voltage

Different high-linearity low noise amplifier (LNA) structures have been designed, simulated and compared, providing good performance results concerning noise figure, bandwidth, power gain, intermodulation and gain compression, when a low-level voltage supply is used. The structures were designed to be used in personal communication systems (PCSs), operating at 1900 MHz using a SiGe heterojunction bipolar transistor (HBT) and 2.4 V bias polarisation     

A low-noise low-offset capacitive sensing amplifier for a 50-/spl mu/g//spl radic/Hz monolithic CMOS MEMS accelerometer

This paper describes a CMOS capacitive sensing amplifier for a monolithic MEMS accelerometer fabricated by post-CMOS surface micromachining. This chopper stabilized amplifier employs capacitance matching with optimal transistor sizing to minimize sensor noise floor. Offsets due to sensor and circuit are reduced by ac offset calibration and dc offset cancellation based on a differential difference amplifier (DDA). Low-duty-cycle periodic reset is used to establish robust dc bias at the sensing electrodes with low noise. This work shows that continuous-time voltage sensing can achieve lower noise than switched-capacitor charge integration for sensing ultra-small capacitance changes. A prototype accelerometer integrated with this circuit achieves 50-/spl mu/g//spl radic/Hz acceleration noise floor and 0.02-aF//spl radic/Hz capacitance noise floor while chopped at 1 MHz.     

Channel temperature measurement using pulse-gate method [poweramplifier FET]

In this paper, we report on an approach of measuring power amplifier field-effect transistor (FET) channel temperature under real-world operating conditions. The principle of this approach is to compare the magnitude of power amplifier gain at both DC and pulse bias conditions. By utilizing the temperature-dependent gain characteristic of the power amplifier FET and applying pulse-gate control, the gain would gradually decrease with the rising temperature of the hot plate. The channel temperature is then determined when the decreasing gain reaches the level of the base line, which is measured under the specified DC bias and radiofrequency conditions     

A 3.1–10.6 GHz Ultra-Wideband Low Noise Amplifier With 13-dB Gain, 3.4-dB Noise Figure, and Consumes Only 12.9 mW of DC Power

A 3.1-10.6 GHz ultra-wideband two-stage pseudomorphit high electron mobility transistor low noise amplifier is presented. The first stage of the amplifier employs a resistive shunt feedback topology and two T-network sections to provide wideband input matching to a 50-Omega antenna. The current-sharing dc bias topology is used to ensure the low power consumption under fixed 3-V battery operation. The amplifier exhibits state of the art performance consuming only 12.9mW of dc power with a power gain of 12.5dB, plusmn0.5dB gain flatness, and 3.4-4.0dB noise figure. Input match is better than -12.0dB, output match is better than -15dB, and group delay is 184pSplusmn28pS     

晶体管放大器三种组态的En—In人噪声分析与比较

准确评价晶体管三种组态的噪声性能是低噪声放大器电路组态优化设计的关键．本文在晶体管三种组态Ｅｎ—Ｉｎ人噪声分析等方面给出了若干新结果．