MPGE—2视频编码流的码率变换技术的研究

比较了分析两种视频编码流的码率变换器结构的性能,提出了一种在图像内按宏块的复杂度分配目标码字,并直接控制交流ＤＣＴ系统编码比特数的码率控制算法。本文提出的码率控制算法优于ＴＭ５的码率控制算法。     

H.264中一种基于R-Q模型的自适应码率控制算法研究

提出一种新的基于帧复杂度的二级码率控制算法TSRCA（two-stage rate control algorithm）。总结码率控制算法的最新研究成果,分析码率控制基本原理,继而提出一种二级码率控制算法,以解决“蛋鸡悖论”。其次,用RDO模式选择中的比特数信息代替平均绝对残差MAD（mean absolute difference）来预测帧的复杂度,提高了预测的准确度。所提出的码率控制算法能够显著提高码率控制精度和编码性能。     

基于场景切换的HEVC码率控制算法

HEVC(High Efficiency Video Coding)采用的基于R-λ模型的码率控制算法在控制输出码率的精确和提高编码效率上都取得了良好的效果.然而该算法没有考虑到实际视频编码中场景切换的影响.提出一种新的针对场景切换的码率控制算法.结合帧间的亮度差及其变换趋势判断是否发生场景切换,在场景切换发生时对码率控制的参数以及编码结构都做出及时调整.实验表明,与HEVC自带的码率控制相比,所提出的码率控制算法能够有效应对视频序列中的场景切换,提高了编码质量,降低了编码复杂度,并且保持精确的输出码率.     

基于视频并行编码的码率控制算法研究

基于并行编码的特点,现有的基于串行编码的码率控制算法有其局限性,不能直接应用于并行编码。本文提出一种新的码率控制算法,在编码前将原始帧作为参考帧计算出各帧的SAD,然后利用已计算的SAD进行帧级比特分配和动态预测并行编码帧的比特,实现了并行编码的码率控制。通过测试基于串行编码的码率控制和本文提出的码率控制方案下PSNR和VBV情况,说明本文所提算法的可行性。     

H.264/AVC帧层码率控制算法的改进

为了提高码率控制在视频编码中的性能,本文提出了一种新的帧层R-Q码率控制算法模型。该模型直接通过H.264码率进行量化控制,但没有考虑复杂度测量估计,从一定程度上提高了码率控制的准确性。通过大量的理论推导与实验验证,提出的模型明显提高了峰值信噪比(P S N R),提高了图像的质量。     

R-Q模型宏块级精准度分析

R-Q模型对于率失真优化、码率分配、量化参数的选择产生重要影响,而宏块级码率分配、量化参数的选择有利于提高实时视频编码效率。简要介绍4种R-Q模型推导过程,详细比较、分析4种模型宏块级精准度,并对复杂度进行说明。实验证明:基于广义高斯分布的R-Q模型精准度最高,但其运算过于复杂,应用于编码比特数预测;而其他3种模型虽然精准度虽不高,但运算简单,应用于码率控制算法。为提出码率预测模型、改进码率控制算法及针对不同应用选择合适的码率控制算法提供了基础性分析。     

联合编码模式选择的码率控制算法

本文提出了一种丢包网络中联合信源信道码率控制算法.该算法克服了以往码率控制方法和误码复原技术互不关联的弊病,在统计率失真模型的基础上,联合最优地计算图像级量化参数和寻找最佳宏块编码模式,在给定的受限码率下能充分利用可用信道带宽,使得视频信源编码和信道传输总失真最小.实验结果表明该算法能够获得比传统算法更高的性能增益.     

基于线性模型的分级B帧比特分配改进算法北大核心

针对分级B帧编码结构,提出了一种基于比特分配线性模型的码率控制算法。通过实验发现不同时间级B帧平均比特数与P帧比特数呈良好的线性关系,利用此线性关系对B帧进行比特分配可以充分利用不同时间级B帧的特性,提高分级B帧结构码率控制的性能。实验结果表明,该算法与JVT-W042相比,对于大部分内容特性序列,平均ΔPSNR提高0.15 dB以上。     

基于线性模型的分级B帧比特分配改进算法

针对分级B帧编码结构,提出了一种基于比特分配线性模型的码率控制算法.通过实验发现不同时间级B帧平均比特数与P帧比特数呈良好的线性关系,利用此线性关系对B帧进行比特分配可以充分利用不同时间级B帧的特性,提高分级B帧结构码率控制的性能.实验结果表明,该算法与JVT-W042相比,对于大部分内容特性序列,平均△SNR提高0.15 dB以上.     

基于频域活动性的码率控制算法的研究

码率控制是恒定码率视频压缩编码系统的一个关键研究课题。本文提出了一种基于频域活动性的修正的TM5码率控制算法。该算法以TM5为基础，同时采用了一些有效的措施．诸如：频域括动性分析、场景变化分析、码字利用映像和强制缓存控制等。对所提出的修正的TM5码率控制算法．本文进行了计算机模拟实验，实验结果证明了本文所提出的算法可以有效地弥补现有的码率控制算法的不足，可适用于多种视频压缩的应用领域。     

Development of a New Robot Controller Architecture with FPGA-Based IC Design for Improved High-Speed Performance

In this paper, a new robot controller architecture is proposed to implement various complex control algorithms for improved high-speed performance. The main thrust of the research is to remove the servo control loop from the digital signal processor (DSP) and implement the high-speed servo loop in a field programmable gate array (FPGA). The main objective of this architecture is to utilize the ultra-high-speed hardwired logic of the FPGA to enhance the overall computational capability and relieve the computational load of the DSP for other tasks. The control algorithm is partitioned into a linear portion and a nonlinear portion. The linear portion with position/velocity feedback represents the major control loop and is implemented in the FPGA. The nonlinear portion acts as dynamic compensation to the linear portion to calculate model-related control gains/parameters, and it is implemented in the DSP. In tandem, with the newly developed control hardware architecture, an FPGA-based motion control integrated circuit (IC) is designed. Experiments are conducted on an industrial robot manipulator to compare the closed-loop performance with this new control architecture and the traditional one, when the same control algorithm is used. The experimental results demonstrate that the proposed new control architecture exhibits much improved motion performance indeed, especially in high-speed motions.     

Efficient algorithm and systolic architecture for modular division

A new efficient modular division algorithm suitable for systolic implementation and its systolic architecture is proposed in this article. With a new exit condition of while loop and a new updating method of a control variable, the new algorithm reduces the average of iteration numbers by more than 14.3% compared to the algorithm proposed by Chen, Bai and Chen. Based on the new algorithm, we design a fast systolic architecture with an optimised core computing cell. Compared to the architecture proposed by Chen, Bai and Chen, our systolic architecture has reduced the critical path delay by about 18% and the total computational time for one modular division by almost 30%, with the cost of about 1% more cells. Moreover, by the addition of a flag signal and three logic gates, the proposed systolic architecture can also perform Montgomery modular multiplication and a fast unified modular divider/multiplier is realised.     

Low-power adaptive pseudo noise code acquisition for spread-spectrum systems

A novel pseudo noise code acquisition combined with the newly proposed adaptive sampling rate and threshold control (ASTC) algorithm is derived for low-power spread-spectrum systems with complementary metal-oxide-semiconductor implementations. Low-power performance can be achieved by reducing the sampling rate of the proposed system while maintaining the system performance. The sampling rate is dynamically updated due to the change of the channel noise level. Under the assumptions that the channel is additive white Gaussian noise slow-fading channel, up to 74.3% reduction in power consumption compared to the conventional fixed-sampling rate and fixed-threshold architecture is demonstrated with insignificant increase of system complexity. The proposed architecture can be applied to the design of low-power and controllable-performance spread-spectrum communication systems.     

雷达目标角度跟踪环路滤波器设计新方法

角度跟踪环路在机载雷达对目标的距离、速度、角度3维联合跟踪中起着至关重要的作用。该文分析指出传统采用卡尔曼滤波算法形成角度跟踪环路对机动目标角度进行跟踪时跟踪精度低,角跟踪误差收敛速度慢的缺点,提出弯曲度检测跟踪环路滤波器(Bend Degree Tracking Loop Filter, BDTLF)设计方法,其利用弯曲度检测角度曲线拐点,自适应地调节环路滤波器环路等效噪声带宽,并以此来控制角度跟踪环路。此算法加快了角跟踪误差的收敛速度,减轻了拐点处的角度滤波扰动,保持了滤波性能的连续性。计算机仿真结果验证了该文方法相比于卡尔曼滤波算法、粒子滤波算法、-- 滤波算法及恒定系数环路滤波器方法,对弱机动目标角度跟踪具有更加出色的性能。     

Performance analysis of an all-digital BPSK direct-sequencespread-spectrum IF receiver architecture

A VLSI architecture for an all-digital binary phase shift keying (BPSK) direct-sequence (DS) spread spectrum (SS) intermediate frequency (IF) receiver is presented, and an in-depth performance analysis is given. The all-digital architecture incorporates a Costas loop for carrier recovery and a delay-locked loop for clock recovery. For the pseudorandom noise (PN) acquisition block, a robust energy detection scheme is proposed to reduce false PN locks over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. A 100 kbs information rate and a 12.7 Mchips/second PN code rate are assumed. The IF center frequency is 12.7 MHz and the IF sampling rate is 50.8 Msamples/second, which is the Nyquist rate for the 25.4 MHz bandwidth signal. Finite wordlength effects have been simulated to optimize the architecture, thereby minimizing the chip area, and results of the finite wordlength simulations demonstrate that the chip architecture achieves a bit error rate performance within 1 dB of theory in an additive white Gaussian noise channel     

High Precision Motion Control of Servo Drives

In this paper, we investigate the advantages and feasibility of motor control using very fast (in megahertz) switching in place of traditional amplifiers. We also propose integrated motion-control architecture based on discrete-event control approach to be implemented in digital logic at an equally high rate. A switching controller combines the current and motion feedback paths into a single loop. A model-based observer estimates the load torque. When compared to second-order controllers implemented with traditional amplifiers, the proposed design promises increased performance, better efficiency, and improved load estimation. Simple implementation makes concepts of switching control very attractive in motion-control systems like control of dc or ac servomotors. The control algorithm designed by the proposed approach can be easily implemented on field programmable gate array platforms.     

基于快速滤波算法的卷积神经网络加速器设计

为减少卷积神经网络(CNN)的计算量,该文将2维快速滤波算法引入到卷积神经网络,并提出一种在FPGA上实现CNN逐层加速的硬件架构。首先,采用循环变换方法设计行缓存循环控制单元,用于有效地管理不同卷积窗口以及不同层之间的输入特征图数据,并通过标志信号启动卷积计算加速单元来实现逐层加速;其次,设计了基于4并行快速滤波算法的卷积计算加速单元,该单元采用若干小滤波器组成的复杂度较低的并行滤波结构来实现。利用手写数字集MNIST对所设计的CNN加速器电路进行测试,结果表明：在xilinx kintex7平台上,输入时钟为100 MHz时,电路的计算性能达到了20.49 GOPS,识别率为98.68%。可见通过减少CNN的计算量,能够提高电路的计算性能。     

一种可控数字频率产生器的设计

本文提出了将DDS技术应用于接收机自动频率控制环路中可控数字频率产生器的一种实现方案,详细阐述了该产生器VLSI实现的算法和结构.最后对性能进行了仿真和分析.     

A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture

In this paper, we propose a new two-stage hardware architecture that combines the features of both parallel dictionary LZW (PDLZW) and an approximated adaptive Huffman (AH) algorithms. In this architecture, an ordered list instead of the tree-based structure is used in the AH algorithm for speeding up the compression data rate. The resulting architecture shows that it not only outperforms the AH algorithm at the cost of only one-fourth the hardware resource but it is also competitive to the performance of LZW algorithm (compress). In addition, both compression and decompression rates of the proposed architecture are greater than those of the AH algorithm even in the case realized by software     

Enhanced performance based on cross-layer design from physical to transport layers for multihop wireless networks

This paper puts forward a novel cognitive cross-layer design algorithms for multihop wireless networks optimization across physical,mediam access control(MAC),network and transport layers.As is well known,the conventional layered-protocol architecture can not provide optimal performance for wireless networks,and cross-layer design is becoming increasingly important for improving the performance of wireless networks.In this study,we formulate a specific network utility maximization(NUM)problem that we believe is appropriate for multihop wireless networks.By using the dual algorithm,the NUM problem has been optimal decomposed and solved with a novel distributed cross-layer design algorithm from physical to transport layers.Our solution enjoys the benefits of cross-layer optimization while maintaining the simplicity and modularity of the traditional layered architecture.The proposed cross-layer design can guarantee the end-to-end goals of data flows while fully utilizing network resources.Computer simulations have evaluated an enhanced performance of the proposed algorithm at both average source rate and network throughput.Meanwhile,the proposed algorithm has low implementation complexity for practical reality.