Improved microwave performance on low-resistivity Si substrates bySi+ ion implantation

Microwave characteristics of spiral inductors on low-resistivity Si substrates have been improved by implanting Si₂₈⁺ ions. Spiral inductors fabricated on these implanted substrates demonstrate better Q-value and microwave performance. The Q-value of inductor enhanced 60% on the implanted substrates than that of low resistivity Si substrates. An equivalent circuit model of inductor has been evaluated to discuss the effect of substrate loss     

Improved performance of Si-based spiral inductors

Conventional spiral inductors on silicon wafer have suffered low quality (Q) factor due to substrate loss. In this work, a technique that combines optimized shielding poly and proton implantation treatment is utilized to improve inductor Q-value. The optimized poly-silicon and proton-bombarded substrate have added 37% and 54% increment to the Q-value of inductors, respectively. If two techniques are combined, a phenomenal Q-value increment as high as 122% of 4-nH spiral inductors can be realized. The combination of the two means has created a multiplication of their individual contribution rather than addition. The technique used in this work shall become a critical measure to put inductors on silicon substrate with satisfactory performance for Si-based radio frequency integrated circuit applications.     

Flip chip assembled MEMS inductors

High performance suspended MEMS inductors produced using a flip chip assembly approach are described. An inductor structure is fabricated on a carrier and then flip chip assembled onto a substrate to form a suspended inductor for RF-IC applications with significant improvement in Q-factor and frequency of operation over the conventional IC inductors. A spiral MEMS inductor has been successfully produced on a silicon substrate with an air gap of 26 /spl mu/m between the inductor structure and the substrate. The inductance of the device was measured to be /spl sim/2 nH and a maximum Q-factor of 19 at /spl sim/2.5 GHz was obtained after pad/connector de-embedding.     

Multilevel-spiral inductors using VLSI interconnect technology

A multilevel-spiral (MLS) inductor structure for implementation in VLSI interconnect technology is presented. Inductances of 8.8 and 32 nH and maximum quality-factors (Q) of ~6.8 and 3.0, respectively, are achieved in a four-level metal BiCMOS technology, with four turns at each of the two or four stacked spiral coils and with an area of 226×226 μm². The comparison of the MLS inductors to different single-level-spiral (SLS) control devices shows that a MLS inductor provides the same inductance at ~50% dc resistance, but the maximum Q is typically measured at a lower frequency and the self-resonance frequency is reduced due to a high inter-wire capacitance     

High-Q factor three-dimensional inductors

In this paper, the great flexibility of three-dimensional (3-D) monolithic-microwave integrated-circuit technology is used to improve the performance of on-chip inductors. A novel topology for high-Q factor spiral inductor that can be implemented in a single or multilevel configuration is proposed. Several inductors were fabricated on either silicon substrate (/spl rho/ = 30 /spl Omega/ /spl middot/ cm) or semi-insulating gallium-arsenide substrate demonstrating, more particularly, for GaAs technology, the interest of the multilevel configuration. A 1.38-nH double-level 3-D inductor formed on an Si substrate exhibits a very high peak Q factor of 52.8 at 13.6 GHz and a self-resonant frequency as high as 24.7 GHz. Our 4.9-nH double-level GaAs 3-D inductor achieves a peak Q factor of 35.9 at 4.7 GHz and a self-resonant frequency of 8 GHz. For each technology, the performance limits of the proposed inductors in terms of quality factor are discussed. Guidelines for the optimum design of 3-D inductors are provided for Si and GaAs technologies.     

Improvement of the quality factor of RF integrated inductors bylayout optimization

A systematic method to improve the quality (Q) factor of RF integrated inductors is presented in this paper. The proposed method is based on the layout optimization to minimize the series resistance of the inductor coil, taking into account both ohmic losses, due to conduction currents, and magnetically induced losses, due to eddy currents. The technique is particularly useful when applied to inductors in which the fabrication process includes integration substrate removal. However, it is also applicable to inductors on low-loss substrates. The method optimizes the width of the metal strip for each turn of the inductor coil, leading to a variable strip-width layout. The optimization procedure has been successfully applied to the design of square spiral inductors in a silicon-based multichip-module technology, complemented with silicon micromachining postprocessing. The obtained experimental results corroborate the validity of the proposed method. A Q factor of about 17 have been obtained for a 35-nH inductor at 1.5 GHz, with Q values higher than 40 predicted for a 20-nH inductor working at 3.5 GHz. The latter is up to a 60% better than the best results for a single strip-width inductor working at the same frequency     

Modeling and Simulation of Spiral Inductors in Wafer Level Packaged RF/Wireless Chips

In this paper, embedded rectangular spiral inductors on Wafer-Level Packaged (WLP)RF/wireless chips were studied with 3D (three-dimensional) EM (electromagnetic)simulations. The performance of spiral inductors fabricated with various geometrical and technological parameterswas analyzed. It is shown that Q (the quality factor) and f _res (theself-resonance frequency) could be improved by using the thick insulator layer and thick/wide metal line,which are fabricated by WLP technology. The value of Q could be over 60 at 20 GHz for such embeddedcomponents, attesting a significant improvement compared to the conventional on-chip counterparts in CMOS. Throughthis study, optimal structures for such components are identified and guidelines for design and fabrications arederived. Finally, a method to estimate the inductance of rectangle spiral inductors is developed. It is useful todetermine the approximate structure of an inductor quickly before detailed 3D EM simulation, which may cost a longtime.     

Development of RF/microwave on-chip inductors using an organic micromachining process

The design and development of a micromachined spiral inductor using an organic micromachining process are presented. The process utilizes an ultra-thick negative photoresist SU-8 to elevate an inductor structure above a substrate. The micromachined inductors have been designed and fabricated on solid and hollow ground planes to, investigate the feasibility for achieving high Q-factors. The experimental results demonstrate that a micromachined inductor integrated on a Si substrate achieves a Q-factor of 19.3 at 2.1 GHz.     

Micromachined microwave planar spiral inductors and transformers

A new micromachined planar spiral inductor, with the strips suspended individually, has been fabricated in standard GaAs high electron-mobility transistor monolithic-microwave integrated-circuit technology through maskless front-side bulk micromachining. The electronic compatibility, the use of industrial integrated-circuit production lines, the straightforward and low-cost additional procedure for structure releasing, and the very short etching time required are the principal features related to such a novel inductor structure. Moreover, the air-gap layer created underneath the device and between the strips significantly reduces shunt and fringing parasitic capacitances, consequently increasing the performance and operating frequency range. Experimental measurements, carried out up to 15 GHz, before and after micromachining, showed for a 12-nH inductor an increase of the maximum Q factor from 5 (at 3 GHz) to about 20 (at 7 GHz), while the self-resonant frequency was shifted from 5 to 13 GHz. Furthermore, a structure with two interleaved spiral inductors, in a 1:1 transformer-like configuration, was also fabricated, and its performance verified in order to demonstrate the promising performance improvements provided by the proposed device. Finally, heating and mechanical characteristics associated with freestanding microstructures are briefly evaluated using finite-element method simulations     

Air Cavity Incorporation to LTCC Spiral Inductor for High Q-factor and SRF

We have devised a new LTCC spiral inductor incorporating an air cavity underneath for high Q-factor and high self-resonant frequency (SRF). The air cavity employed under the spiral reduces the shunt capacitance of the inductor, and results in high Q-factor and SRF of the embedded inductors. The optimized spiral inductor with the embedded air cavity shows a maximum Q of 51 and SRF of 9.1 GHz, while conventional spiral inductor has a maximum Q of 43 and SRF of 8 GHz with effective inductance of 2.7 nH.     

Micromachined high-Q inductors in a 0.18-μm copper interconnectlow-k dielectric CMOS process

On-chip spiral micromachined inductors fabricated in a 0.18-μm digital CMOS process with 6-level copper interconnect and low-K dielectric are described. A post-CMOS maskless micromachining process compatible with the CMOS materials and design rules has been developed to create inductors suspended above the substrate with the inter-turn dielectric removed. Such inductors have higher quality factors as substrate losses are eliminated by silicon removal and increased self-resonant frequency due to reduction of inter-turn and substrate parasitic capacitances. Quality factors up to 12 were obtained for a 3.2-nH micromachined inductor at 7.5 GHz. Improvements of up to 180% in maximum quality factor, along with 40%-70% increase in self-resonant frequency were seen over conventional inductors. The effects of micromachining on inductor performance was modeled using a physics-based model with predictive capability. The model was verified by measurements at various stages of the post-CMOS processing. Micromachined inductor quality factor is limited by series resistance up to a predicted metal thickness of between 6-10 μm     

Substrate noise coupling through planar spiral inductor

While precious studies on substrate coupling focused mostly on noise induced through drain-bulk capacitance, substrate coupling from planar spiral inductors at radiofrequency (RF) via the oxide capacitance has not been reported. This paper presents the experimental and simulation results of substrate noise induced through planar inductors. Experimental and simulation results reveal that isolation between inductor and noise source is less than -30 dB at 1 GHz. Separation by distance reduces coupling by less than 2 dB in most practical cases. Practical examples reveal an obstacle in integrating RF tuned-gain amplifier with sensitive RF receiver circuits on the same die. Simulation results indicate that hollow inductors have advantages not only in having a higher self-resonant frequency, but also in reducing substrate noise as compared to conventional inductors. The effectiveness of using a broken guard ring in reducing inductor induced substrate noise is also examined     

Q-factor definition and evaluation for spiral inductors fabricated using wafer-level CSP technology

A novel Q-factor definition and evaluation method are proposed for low-loss high-Q spiral inductors fabricated by using the wafer-level chip-size package (WLP) on silicon substrates, where the copper wiring technology with a polyimide isolation layer is used. In conventional Q-factor evaluation for inductors, a short-circuited load condition is used, where the Q factor is represented by using Y-parameters as Q=Im{1/Y/sub 11/}/Re{1/Y/sub 11/}. This conventional method provides a Q factor of 20 with 2-5-nH inductance around 3.9 GHz. However, since structures for the spiral inductors are asymmetrical, the short-circuited load condition and short-circuited source condition give different Q values, respectively. The Q-value differences of approximately 100% have often been observed in the WLP. The differences mainly come from differences in loss estimation. In a novel method, a complex conjugate impedance-matching condition is retained both at an input port and an output port of the inductor. The maximum available power gain (G/sub AMAX/) is introduced to evaluate the energy loss in one cycle. This condition provides a unique insertion loss of passive devices. Thus, the difference of the Q factor depends only on the difference of magnetic and electric energy. The difference of the Q value is reduced.     

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.     

Fabrication and performance of novel RF spiral inductors on silicon

This paper presents and discusses the fabrication and the performance of RF circular spiral inductors on silicon. The substrate materials underneath the inductor coil are removed by wet etching process. In the fabrication process, fine polishing of the photoresist is used to simplify the processes and ensure the seed layer and the pillars contact perfectly, and dry etching technique is used to remove the seed layer. The results show that Q-factor of the novel inductor is greatly improved by removing the silicon underneath the inductor coil. The spiral inductor for line width of 50 μm has a peak Q-factor of 17 at frequency of 1 GHz. The inductance is about 3.2 nH in the frequency range of 0.05-3 GHz and the resonance frequency of the inductors is about 6 GHz. If the strip is widened to 80 μm, the peak Q-factor of the inductor reduces to about 10 and the inductance is 1.5 nH in the same frequency range.     

Miniature 3-D inductors in standard CMOS process

The structure of a miniature three-dimensional (3-D) inductor is presented in this paper. The proposed miniature 3-D inductors have been fabricated in a standard digital 0.35-μm one-poly-four-metal (1P4M) CMOS process. According to the measurement results, the self-resonance frequency f_SR of the proposed miniature 3-D inductor is 34% higher than the conventional stacked inductor. Moreover, the inductor occupies only 16% of the area of the conventional planar spiral inductor with the same inductance and maximum quality factor Q_max. A 2.4-GHz CMOS low-noise amplifier (LNA), which utilized the proposed miniature 3-D inductors, has also been fabricated. By virtue of the small area of the inductor, the size and cost of the radio frequency (RF) chip can be significantly reduced     

Spiral inductors on Si p/p+ substrates with resonantfrequency of 20 GHz

Porous Si of up to 200 μm in thickness has been used to fabricate high-performance spiral inductors on heavily doped Si substrates (0.007 Ω-cm). Spiral inductors with L~5.7 nH are fabricated demonstrating Q_max~29 at 7 GHz and f_r>20 GHz. The resonant frequency (f_r) increases with increasing porous Si thickness and saturates beyond 120 μm. A corresponding decrease in total capacitance is observed. Q_max increases monotonically with porous Si layer thickness to beyond 200 μm. For inductors with a smaller footprint, Q_max begins to saturate at less than 100-μm thick porous Si     

Design of MCI single and symmetrical on-chip spiral inductors

In this paper, the MCI (multipath crossover interconnection) technique for octagon single and symmetrical spiral inductors has been presented to improve the quality factor. The metal wires of the single and symmetrical inductors formed by the top metal are divided into multiple segments according to the depth of the skin effects. The outermost path of the metal is crossover-interconnected to the innermost path by the underlayer metal and via The crossover technique makes the lengths of the total current paths between two ports approximately equal to each other. Therefore, the induced magnetic flux and resistance of each path can be balanced and the Q-factor of spiral inductors can be enhanced. The proposed MCI technique has been validated by the electromagnetic simulation with the 130-nm 1P6M SiGe BiCMOS process. For the devices with occupying areas of 240×240μm², results of electromagnetic simulation show that about 24% improvement in the Q-peak (3.3 GHz) of the MCI single inductor as compared to conventional single inductors (3.1 GHz), and about 88.1% improvement in the Q-peak (3.2 GHz) of the MCI symmetrical inductor as compared to conventional symmetrical inductors (1.8 GHz).     

On-chip solenoid inductors with high quality factor for high frequency magnetic integrated circuits

On-chip solenoid inductors for high frequency magnetic integrated circuits are proposed. The eddy current loss was reduced by dividing the inductor into three consecutive inductors connected in series. The inductor has an inductance of 1.1nH and the maximum quality factor (Q/sub max/) of 50.5. The self-resonant frequency and the operating frequency at Q/sub max/ are greater than 17.5GHz and 16.7GHz, respectively.     

MMIC用多层磁膜电感研究

采用磁控溅射生长磁膜工艺,结合BCB(苯并环丁烯)平坦化技术,首次制作了"金属线圈/磁膜/金属线圈(M/F/M)"和"磁膜/金属线圈/磁膜/金属线圈(F/M/F/M)"两种结构的多层磁膜电感,整个工艺与标准MMIC工艺兼容.在2 GHz处,"金属线圈/磁膜/金属线圈"结构电感的电感量为7.5 nH,品质因数为7.17,...