复合量子点MOSFET结构存储器的电路模拟

本文采用准经典近似的Monte Carlo方法对复合量子点MOSFET结构存储器的等效单电子电路进行了模拟.研究结果表明,由于台阶状的复合隧穿势垒的作用,存储器的存储时间特性可得到极大提高.我们进一步研究了N沟道锗/硅复合量子点MOSFET结构存储器的时间特性,得到其存储时间可长达数年,同时写擦时间可分别为μs和ns量级,从而这种新型的器件结构可以有效解决快速编程和长久存储间的矛盾.     

P-channel Ge/Si Hetero-nanocrystal Based MOSFET Memory

The charge storage characteristics of P-channel Ge/Si hetero-nanocrystal based MOSFET memory has been investigated and a logical array has been constructed using this memory cell. In the case of the thickness of tunneling oxide T_ox=2nm and the dimensions of Si- and Ge-nanocrystal D_Si=D_Ge=5nm, the retention time of this device can reach ten years(~1×10~8s) while the programming and erasing time achieve the orders of microsecond and millisecond at the control gate voltage |V_g|=3V with respect to N-wells, respectively. Therefore, this novel device, as an excellent nonvolatile memory operating at room temperature, is desired to obtain application in future VLSI.     

Ge/Si复合纳米结构电荷存储特性的模拟研究

这一研究工作模拟计算了 Ge/ Si复合纳米结构 MOSFET存储器的擦写和存储时间特性。结果表明 ,Ge/ Si复合纳米结构存储器在低压下即可实现 μs和 ns量级编程。与 Si纳米结构存储器相比 ,由于 Ge/ Si复合势阱的作用 ,器件的电荷保留时间提高了 3～ 5个量级 ,有效地解决了快速擦写编程与长久存储之间的矛盾 ,使器件的性能得到明显改善。     

Very High Carrier Mobility for High-Performance CMOS on a Si(110) Surface

In this paper, we demonstrate CMOS characteristics on a Si(110) surface using surface flattening processes and radical oxidation. A Si(110) surface is easily roughened by OH^- ions in the cleaning solution compared with a Si(100) surface. A flat Si(110) surface is realized by the combination of flattening processes, which include a high-temperature wet oxidation, a radical oxidation, and a five-step room-temperature cleaning as a pregate-oxidation cleaning, which does not employ an alkali solution. On the flat surface, the current drivability of a p-channel MOSFET on a Si(110) surface is three times larger than that on a Si(100) surface, and the current drivability of an n-channel MOSFET on a Si(100) surface can be improved compared with that without the flattening processes and alkali-free cleaning. The 1/f noise of the n-channel MOSFET and p-channel MOSFET on a flattened Si(110) surface is one order of magnitude less than that of a conventional n-channel MOSFET on a Si(100) surface. Thus, a high-speed and low-flicker-noise p-channel MOSFET can be realized on a flat Si(110) surface. Furthermore, a CMOS implementation in which the current drivabilities of the p-channel and n-channel MOSFETs are balanced can be realized (balanced CMOS). These advantages are very useful in analog/digital mixed-signal circuits.     

Enhancement-mode quantum-well GexSi1-x PMOS

The authors demonstrate the feasibility of a p-channel quantum-well MOSFET on a Ge_xSi_1-x/Si heterostructure. The advantages of the enhancement-mode p-channel MOSFET device compared to GeSi MODFETs are its high impedance, channel mobility, and channel transconductance. The device shows good saturation and cutoff behaviour. A saturation transconductance of 64 mS/mm was measured for a 0.7-μm channel device at a drain-to-source voltage of -2.5 V. The channel mobility was found to be higher than that of a similarly processed Si p-channel MOSFET     

基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

Charge trapping memory devices employing multi-layered Ge/Si nanocrystals for storage fabricated with ALD and PLD methods

The Ge/Si nanocrystals on ultra thin high-k tunnel oxide Al2O3 were fabricated to form the charge trapping memory prototype with asymmetric tunnel barriers through combining the advanced atomic layer deposition (ALD) and pulse laser deposition (PLD)techniques. Charge storage characteristics in such memory structure have been investigated using capacitance-voltage (C-V) and capacitance-time (C-t) measurements. The results prove that both the two-layered and three-layered memory structures behave relatively qualified for the multi-level cell storage. The results also demonstrate that compared to electrons, holes reach a longer retention time even with an ultra thin tunnel oxide owing to the high band offset at the valence band between Ge and Si.     

Characteristics of p-channel Si nano-crystal memory

In this work, the feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. By comparing the programming characteristics of devices with nano-crystals and devices without nano-crystals, the role of dots as storage node is presented. The programming and erasing mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. In case of erasing, the electron tunneling occurs from either the conduction band or the valence band. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time     

Inversion-channel Si/SiGe heterojunction field-effect transistor

The p-channel operation of a selfaligned heterojunction field-effect transistor (HFET) based on an Si/Si/sub 0.75/Ge/sub 0.25/ heterostructure is demonstrated. Extrinsic transconductance g/sub m/ greater than 8 mS/mm for a device with 1 mu m gate length was measured at 300 K. The high frequency 3 dB point has been measured to be 1.8 GHz.<>     

Programming characteristics of p-channel Si nano-crystal memory

In this work, the programming characteristics of a p-channel nano-crystal memory is studied. The hole tunneling component from the inversion layer and the electron tunneling component from the valence band in the nano-crystal were separated successfully by independent measurement of the current at the body terminal and at the source/drain terminal of the memory. For small gate voltage, the hole tunneling current is dominant during programming. However, for large programming voltage, the valence band electron tunneling from the dot into the substrate becomes dominant. Finally, the comparison of retention characteristics between programmed holes and electrons shows that holes have longer retention time     

Electrical characterization of germanium p-channel MOSFETs

In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.     

Optimization of alloy composition for high-performance strained-Si-SiGeN-channel MOSFETs

On-state and off-state performance of strained-Si-SiGe n-channel MOSFETs have been investigated as a function of SiGe virtual substrate alloy composition. Performance gains in terms of on-state drain current and maximum transconductance of up to 220% are demonstrated for strained-Si-SiGe devices compared with Si controls. Device performance is found to peak using a virtual substrate composition of Si/sub 0.75/Ge/sub 0.25/. MOSFET fabrication used high thermal budget processing and good gate oxide quality has been maintained for virtual substrates having Ge compositions up to 30%. Off-state characteristics are found to be more sensitive to strain relaxation than on-state characteristics.     

Fully depleted n-MOSFETs on supercritical thickness strained SOI

Strained silicon-on-insulator (SSOI) is a new material system that combines the carrier transport advantages of strained Si with the reduced parasitic capacitance and improved MOSFET scalability of thin-film SOI. We demonstrate fabrication of highly uniform SiGe-free SSOI wafers with 20% Ge equivalent strain and report fully depleted n-MOSFET results. We show that enhanced mobility is maintained in strained Si films transferred directly to SiO/sub 2/ from relaxed Si/sub 0.8/Ge/sub 0.2/ virtual substrates, even after a generous MOSFET fabrication thermal budget. Further, we find the usable strained-Si thickness of SSOI significantly exceeds the critical thickness of strained Si/SiGe without deleterious leakage current effects typically associated with exceeding this limit.     

A new half-micrometer p-channel MOSFET with efficient punchthrough stops

This paper describes design and characteristics of a new half-micrometer buried p-channel MOSFET with efficient punch-through stops. The approach for scaling down the buried p-channel MOSFET's is discussed by using two-dimensional process/device simulations and experimental results. The efficient punchthrough stops have realized high punchthrough resistance in half-micrometer dimensions without increasing the n-well concentration and extreme scaling of channel and source-drain junction depths. Moreover, this p-channel MOSFET shows the breakdown voltage to be as high as 10 V. The fabrication sequence is compatible with the conventional n-channel LDD MOSFET's.     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

硅纳米晶粒基MOSFET存储器的荷电特征研究

本文研究了硅纳米晶粒MOSFET存储器的荷电特征.器件阈值电压偏移达1.8V以上,并随着沟道宽度的变窄而增加,而与沟道长度基本无关.同时,阈值涨落也随宽度的变窄而增大.在20~300K测量温度范围内,器件阈值偏移和电荷的存储特性几乎不随温度变化,说明荷电过程主要由直接隧穿决定.进一步,在最窄沟道器件中观察到单电荷的荷电过程.     

第一性原理研究应变Si/(001)Si_(1-X)Ge_X能带结构

应变SiCMOS技术是当前研究发展的重点,其材料的能带结构是研究设计高速/高性能器件和电路的理论基础。基于密度泛函理论框架的第一性原理平面波赝势方法对双轴应变Si/(001)Si1-XGeX(X=0.1～0.4)的能带结构进行了研究,结果表明:应变消除了价带带边和导带带边的简并度;应变几乎没有改变电子有效质量,而沿[100]方向空穴有效质量随着Ge组份的增加而显著变小;导带劈裂能、价带劈裂能、禁带宽度与Ge组份X的拟合结果都是线性函数关系。以上结论为Si基应变MOS器件性能增强的研究及导电沟道的应力与晶向设计提供了重要理论依据。     

High-power conductivity-modulated FET's (COMFET's) with a p-type channel

In previous work, a conductivity-modulated field-effect transistor (COMFET) having drastically reduced on-resistance was described; that device was based on n-channel MOS technology. In this letter, we report the development of a complementary device-the p-channel COMFET. These new p-channel COMFET's have demonstrated dc on-resistance values as low as 0.07 Ω at 20 A (for a 3 mm × 3 mm pellet), while providing forward blocking voltages of 200-400 V. To our knowledge, this on-resistance value (normalized to the same active area) is lower than that of any p-channel power MOSFET (even those with blocking voltages of only 100 V) and as much as 30 times less than that of a p-channel MOSFET with a comparable blocking-voltage capability. Using suitable minority-carrier-lifetime control techniques, drain-current-decay times have been reduced from ≈ 30 µs to below 1 µs.     

Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching

A vertical ultrathin channel formation process for a vertical type double-gate (DG) MOSFET is proposed. Si wet etching using an alkaline solution has newly been found to be significantly retarded by introducing ion bombardment damage. We have also found that the ion-bombardment-retarded etching (IBRE) is independent of ion species and the implanted impurities can easily be transferred to be the dopants for source and drain regions of MOSFETs. By utilizing the IBRE, vertical type DG MOSFETs with a 12-nm-thick vertical channel were fabricated successfully. The fabricated vertical DG MOSFETs clearly exhibit the unique advantage of DG MOSFETs, i.e., high improvement of short-channel effect immunity by reducing the channel thickness. Thanks to the ultrathin channel, very low subthreshold slopes of 69.8 mV/dec. for a p-channel and 71.6 mV/dec for an n-channel vertical DG MOSFET are successfully achieved with the gate length of 100 nm.