Design and simulation of a nanoelectronic single-electron universal Control-Control-Not gate

A single-electron universal Control-Control-Not gate (CCN gate) is presented in this paper. Bits of information are represented by the presence or absence of single-electrons at conducting islands. The logic operation of the CCN gate as well as its XOR, AND, NAND and NOT operation is verified using simulation. The stability of its universal operation is analysed using a Monte Carlo method. Stability analysis using free energy diagrams and stability plots verify the correct and stable operation of the gate.     

Design and simulation of a nanoelectronic single-electron Control—Not gate

A nanoelectronic single-electron Control-Not gate is presented in this paper. Bits of information are represented by the presence or absence of single electrons at conducting islands. The logic operation of the gate is verified using simulation, whereas the stability of its operation is analyzed using Monte-Carlo method.     

Implementation of non-linear filters using nanoelectronic single-electron circuitry

Non-linear filters are large family of filters used in signal and image processing. They have found numerous applications such as in digital image restoration, speech processing and coding, digital TV applications, etc. In this paper, two binary non-linear filters, the three-point median filter and the 2×2-pixel morphological opening filter are designed using nanoelectronic single-electron circuitry. In single-electron circuits bits of information are represented by the presence or absence of single electrons at conducting islands. The two nanoelectronic filters are simulated using a Monte Carlo technique and their correct and stable logical operation is confirmed.     

Design and simulation of a nanoelectronic single-electron universal Fredkin gate

A single-electron universal Fredkin gate (F-gate) is presented in this paper. Bits of information are represented by the presence or absence of single electrons at conducting islands. The logic operation of the F-gate as well as its AND, OR, and NOT operation is verified using simulation. The stability of its universal operation is analyzed using a Monte Carlo method. Stability analysis using free-energy diagrams and stability plots verified the correct and stable gate operation. The operation temperature of the single-electron Fredkin is expected to rise as dimensions of the circuit's conducting islands are reduced.     

Design and simulation of a nanoelectronic single electron 2-4 decoder using a novel simulator

The design and simulation of a single-electron 2-4 decoder using a novel single electron circuit simulation tool named single-electron circuit simulator (SECS), is presented in this paper. In single electron circuits bits of information are represented by the presence or absence of single electrons at conducting or semiconducting islands. SECS utilizes the Monte Carlo method and the change in free-energy of the whole circuit determines the tunnel rates of possible tunnel events, providing thus a real time simulation of any arbitrary single-electron circuit. Furthermore, SECS is using the SPICE interface for schematic capture. SPICE models of single-electron circuit structures have been developed and, therefore, SECS can also be used for the design and simulation of hybrid microelectronic—single-electron circuits.     

Design and simulation of octal-to-binary encoder using capacitive single-electron transistors (C-SETs)

This paper presents an octal-to-binary encoder that is designed using capacitive single-electron transistors (C-SETs). The design parameters are calculated by considering each C-SET as a switching device in pull-up configuration. Logic circuit is based on voltage state logic. The designed circuit was simulated using SIMON 2.0, which is based on Monte Carlo and master equation (MC-ME) methods. The simulation results verify the operation of octal-to-binary encoder.     

一种优化的应用于无线通信模拟前端的模数转换器

本文基于无线通信模拟前端的特点,设计一个优化的10bit 80MS/s 的模数转换器。不同于传统的1.5bit每级的流水线结构,本设计实现2.5bit每级的优化结构。片上的低噪声参考电压缓冲器有利于实现SoC集成,宽带宽摆幅采样保持电路有利于在高输入信号频率条件下取得良好的动态性能。在0.18μm 1P6M的工艺平台上实现该设计,芯片核心面积为0.85mm₂. 测试结果表明,该模数转换器获得ENOB=9.4bit,SFDR=72dBc的性能。     

光学Sigma-Delta模数转换器的研究进展

采用光学模数转换技术已经成为高转换速率、高比特精度模数转换器(ADC)的发展趋势.光学Sigma-Delta ADC作为一种光学ADC,具有转换精度高和模拟电路简单等显著优点.介绍了光学Sigma-Delta ADC的基本原理,详细阐述了几种典型的光学Sigma-Delta ADC的系统结构,对不同结构的光学Sigma-Delta ADC的优缺点进行了归纳总结.     

高性能模数转换器ADS803与DSP的接口设计

介绍了高速模数转换器ADS803的性能、引脚和工作方式，并给出了它与数字信号处理器TMS320F206的两种接口设计方案。     

A novel time-based low-power pipeline analog to digital converter

A new power reduction technique for analog-to-digital converters is proposed in this paper. A novel current-mode algorithm which uses time to perform analog-to-digital conversion has been described and a 12 bit 100-ksample/s time-based pipeline analog to digital converter has been designed and simulated in standard 90-nm CMOS technology based on introduced structure. Employed circuit techniques include a continues-time comparator, bottom plate sampling, digital correction and a state machine. A time based-mechanism has been used for subtraction and amplification. Simulation results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio of 69.8 dB, a peak spurious-free dynamic range of 75 dB, a total harmonic distortion of 73 dB, and a peak integral nonlinearity of 0.85 least significant bits. The total power dissipation is 90 μW from a 3-V supply.     

高精度模数转换器的接口技术

为了保证高精度模数转换器的性能,在设计和使用高精度ADC的外围接口电路时应考虑到数据输出接口、基准电压模块、输入信号调理、电源管理、数字时序逻辑等多方面的因素,只有严格设计才能保证ADC的正常使用,并减小由于外围接口电路所带来的失调误差、增益误差等误差。本文结合具体实例,提出了高精度ADC的接口设计方案。     

Synthesis and functionalization of epitaxial quantum dot nanostructures for nanoelectronic architectures

We describe methods for assembly of quantum dots (QDs) into arrays of any symmetry, and methods for nanoscale doping of individual QDs. We have previously shown how the Ga⁺ focused ion beam (FIB) can template Si(1 0 0) surfaces for controlled Ge QD nucleation. Local Ga-induced reduction of the wetting layer thickness also suppresses QD nucleation away from the templating sites. This allows synthesis of arrays of any defined geometry and set of spatial frequencies, with positional control of each QD element to ca. 10 nm. We have also applied these methods to “quantum dot molecule” (QDM) structures, that comprise four QDs surrounding a central surface pit and that form spontaneously under conditions of limited adatom mobility in GeSi/Si(1 0 0). Again, the positions and spacings of the QDMs can be controlled by local FIB templating. This creates hierarchical order over multiple lengths scales, from ultra-small dimensions inaccessible to conventional lithography (i.e. nm for QD spacing to tens of nm for individual QD sizes), to much greater length scales (hundreds of μm) over which controlled arrays of QDMs can be fabricated. The ability to bring individual QDs in the QDM into very close proximity (of order nm) has potential applications to nanoelectronic architectures based on electron/hole tunneling or spin interactions. We are developing methods for electronic and magnetic functionalization of these nanostructures using a mass-selected FIB, where ions of different species can be separated from liquid metal alloy sources (e.g. Si from AuSi, B and As from PdAsB, and Mn and Ge from MnGe).     

10位逐次逼近型A/D转换器的芯片设计

介绍了一种10位、3M sample/s逐次逼近型A/D转换器的设计,描述了具有可变时钟电路结构的有效工作方式.该模数转换器在0.6 μ m双多晶硅、双金属层CMOS工艺上实现,芯片总面积为3.2mm2.转换器采用单5V电源供电,功耗仅为3 5mW.     

Design methodology for configurable analog to digital conversion using support vector machines

We apply a support vector machine (SVM) classifier to the design of analog to digital converters. Each output bit of the converter is the output of a binary classifier, which is a nonlinear SVM. The classifier effectively learns a folding characteristic for each bit, which is realized as the weighted sum of a set of kernel functions. In our proposal, the kernel does not need to be symmetric or positive definite, unlike in the case of a conventional SVM. This makes the approach more amenable to VLSI design, where such constraints are hard to satisfy. The SVM uses a set of binary weights, which allows the folding characteristics to be digitally corrected after fabrication. This facility is of considerable value in analog design in a deep sub micron era, where simulation models do not adequately capture the behavior of devices, or their variations. The proposed methodology reduces design time, can be automated and calibrated for process variations and ageing, by changing a set of digital scaling coefficients.     

Nonlinearity analysis of folded Multi-LSB decided resistor string digital to analog converter

A theoretical nonlinearity analysis of folded multi-LSB decided resistor string DAC is presented. By the derived theoretical equations, circuit designers can calculate the required resistor mismatch very quickly, thus reducing the design time. The Monte-Carlo simulation results agree well with the theoretical equations and confirm their accuracy.     

Analysis of a soft-switched PFC boost converter using analog and digital control circuits

This work presents a comparison between analog and digital (PIC16c73a) control types applied to the boost converter with a nondissipative snubber. Both control types use the bang-bang hysteresis current waveshaping control technique in order to achieve a quasi-unity power factor. The analog control applied presented a high power factor (0.998), high efficiency (92.87%), and low harmonic distortion [total harmonic distortion of current (THDI =2.84% and total harmonic distortion of current (THDV) =2.83%]. The digital control presented a high power factor (0.990), high efficiency (92.46%), and low harmonic distortion (THDI=5.09% and THDV=2.84%).     

On the generalization of composite memristive network structures for computational analog/digital circuits and systems

The unique adaptive properties of memory resistors (memristors) are ideal for use in computational architectures. Multiple interconnected memristors demonstrate complicated overall behavior which significantly improves the efficiency of logic operations via massive parallelism. Nowadays, within an ever-growing variety of memristive systems, most of the research has so far focused on the properties of the individual devices; little is known about the extraordinary features of complex memristive networks and their application prospects. The composite characteristics of regular and irregular memristive networks are explored in this work. A generalized concept for the construction of composite memristive systems, efficiently built out of individual memristive devices, is presented. A new type of threshold-dependent programmable memristive switches, presenting different electrical characteristics from their structural elements, is proposed. As an example of the introduced approach, a SPICE simulation-based evaluation of several programmable analog circuits is presented. The proposed circuit design approach constitutes a step forward towards novel memristor-based nanoelectronic computational systems and architectures.     

模数转换与波特率设置对大气激光语音通信质量的影响

从激光大气语音通信电路设计的角度分析了引起语音传输失真的主要因素:A/D转换器的选择和波特率的设置.实验表明:激光大气语音通信对A/D转换器的转换精度要求较高,即要保证语音通信质量,A/D转换器的转换精度应在8位以上;而对A/D转换器的转换速率要求较低,一般选择8 kHz或10 kHz的采样速率即可;在正确选择编码方式后,波特率设置为大于数字信号传输速率,可保证语音通信质量.     

数模混合电路中的"地跳动"问题研究

针对数模混合电路中接地问题进行研究。从集成芯片的角度讨论了“地跳动”问题的根源，然后运用得到的结论对一般的数模混合电路进行分析，提出解决的方案，使数字噪声对模拟电路的干扰降到最低。