Lateral punch-through TVS devices for on-chip protection in low-voltage applications

A novel lateral punch-through TVS (Transient Voltage Suppressor) structure addressed to on-chip protection in very low voltage applications is reported in this paper. Different lateral TVS structures have been studied in order to optimize the electrical performances related with the surge protection capability. Lateral TVS structures with a four-layer doping profile exhibit the best electrical performances, as in the case of vertical TVS devices. The dependence of the basic electrical characteristics on the technological and geometrical parameters is also analysed. Finally, the electrical performances of lateral TVS structures are compared with those of vertical punch-through TVS devices and conventional Zener diodes, being the leakage current level reduced two orders of magnitude in the case of the lateral architecture. Lateral TVS structures exhibits similar performance than vertical counterparts with the advantage of easiest on-chip integration.     

深槽TVS研究

以静电放电（ESD）以及其他一些电压浪涌形式随机出现的瞬态电压,通常存在于各种电子器件中。随着半导体器件日益趋向小型化、高密度和多功能。电子器件越来越容易受到电压浪涌的影响,甚至导致致命的伤害。从静电放电到闪电等各种电压浪涌都能诱导瞬态电流尖峰,瞬态电压抑制器（TVS）通常用来保护敏感电路受到浪涌的冲击。基于不同的应用。瞬态电压抑制器可以通过改变浪涌放电通路和自身的箝位电压来起到电路保护作用。为了节省芯片面积,并且获得更高的抗浪涌能力,深槽TVS的概念已经被提出和研究。深槽TVS的结面形成于纵向的深槽的侧壁,这样,在相同的芯片面积下,它有更多的有效结面积,即更强的放电能力。我们也可以预见,深槽TVS的小封装尺寸对应用于保护高端IC非常关键。     

Pin-pin ESD protection for electro-explosive device under severe human body ESD

Electrostatic discharge (ESD) may introduce huge damages to electro-explosive devices (EEDs). This paper studies the pin-pin ESD protection for EED under server human body ESD. We use the PSpice and MATLAB to simulate the ESD of EED protected with transient voltage suppressor (TVS), varistor, semiconductor arrester and capacitance. Moreover, we achieve the decay time, current waveforms, voltage waveforms and energy integration waveforms of the EED during the ESD, with different protections. Simulation results reveal that TVS succeeded in protecting bridgewire EED against the pin-pin ESD, while other three did not provide adequate protection. The pin-pin ESD experiments have been performed using the TVS and varistor. Experimental results show that, using the TVS protection, the EED is not firing under the severe 50 kV ESD voltage. However, by using varistor protection, the ESD protection capability increases by more than 90%, while the protection capability only enhances by 3.1%. The response time of the TVS, i.e. 10^− 12 s, is much faster than that of the varistor, i.e. 10^− 8 s.     

Comparison of p–n junction formed by BF2 and B implantation in silicon microstrip detector with low and high thermal budget: impact of fluorine on electrical characteristics

The influence of crystal damage on the electrical properties and the doping profile of the implanted p⁺–n junction has been studied at different annealing temperatures using process simulator TMA-SUPREM4. This was done by carrying out two different implantations; one with implantation dose of 10¹⁵ BF₂⁺ ions/cm² at an energy of 80 keV and other with 10¹⁵ B⁺ ions/cm² at 17.93 keV. Substrate orientation 1 1 1 of phosphorus-doped n-type Si wafers of resistivity 4 kΩ cm and tilt 7° was used, and isochronally annealing was performed in N₂ ambient for 180 min in temperature range between 400°C and 1350°C. The diode properties were analysed in terms of junction depth, sheet resistance. It has been found that for low thermal budget annealing, boron diffusion depth is insensitive to the variation in annealing temperature for BF₂⁺-implanted devices, whereas, boron diffusion depth increases continuously for B⁺-implanted devices. In BF₂⁺-implanted devices, fluorine diffusion improves the breakdown voltage of the silicon microstrip detector for annealing temperature upto 900°C.For high thermal budget annealing, it has been shown that the electrical characteristics of BF₂⁺-implanted devices is similar to that obtained in B⁺-implanted devices.     

In Situ Reversible Ionic Control for Nonvolatile Magnetic Phases in a Donor/Acceptor Metal‐Organic Framework

Reversible magnetic control by electrical means, which is highly desired from the viewpoint of fundamentals and technological applications such as data storage devices, has been a challenging topic. In this study, the authors demonstrate in situ magnetic phase switching between the ferrimagnetic and paramagnetic states of an electron‐donor/‐acceptor metal‐organic framework (D/A‐MOF) using band‐filling control mediated by the Li⁺‐ion migration that accompanies redox reactions, i.e., “magneto‐ionic control”. By taking advantage of the rechargeability of lithium‐ion battery systems, in which Li⁺‐ions and electrons are simultaneously inserted into/extracted from a cathode material, the reversible control of nonvolatile magnetic phases in a D/A‐MOF has been achieved. This result demonstrates that the combination of a redox‐active MOF with porous flexibility and ion‐migration capability enables the creation of new pathways toward magneto‐electric coupling devices in the field of ionics.     

Double injection in PπN silicon devices

Investigation of the d.c. electrical behavior of semiconductor P⁺πN⁺ double injection devices is presented. The samples studied were fabricated from indium-doped silicon partially compensated by shallow donor impurities and were biased into the double injection (post-breakdown) regime at a temperature of 77°K. A numerical computer solution of the steady-state characteristic has been completed in order to explain the experimental d.c. data. The analysis reveals that electron-hole scattering is largely responsible for the increase in bulk voltage with current. In order to obtain agreement between the numerical solution and the experimental data, the filamentary nature of the double injection current is demonstrated.     

A TCAD comparative study of power rectifiers: modified P-i-N vs. modified mosaic contact P-i-N diode

This paper presents the results of a TCAD comparative study of an modified P-i-N diode (M-PiN) vs. modified mosaic contact P-i-N diode (M-MCPD). The P⁺/N⁺ mosaic contact is formed on the anode’s surface by selective phosphorus and boron diffusion through its corresponding oxide mask. A significant reduction in the drift-region lifetime in the M-PiN rectifier is required to achieve the same short reverse recovery time observed in the M-MCPD rectifiers. The reduction in the reverse recovery time is mainly due to the fact that the M-MCPD rectifier has a smaller stored charge in the drift-region compared to the M-PiN rectifier. Since the forward voltage drop of the M-MCPD is not quite affected by different mosaic area ratios the M-MCPD rectifier exhibits a better trade-off between forward drop and switching characteristics compared to the M-PiN rectifier. The two-dimensional numerical study has been carried out using the circuit and system simulation programs from ISE-TCAD to realize the technological, electrical and mixed-mode simulation.     

Highly flexible and stable memristive devices based on hexagonal boron-nitride nanosheets: Polymethyl methacrylate nanocomposites

The current-voltage results for nonvolatile memristive devices based on hexagonal boron-nitride nanosheets:polymethyl methacrylate nanocomposites exhibit the characteristics of write-once-read-many-times in the voltage range from −3 to 3 V. The electrical characteristics remain unchanged even the devices are under highly bended states. After the devices had finished the “writing” process, they could be read more than 500 times under both flat and bending conditions. Both the high and the low resistance states could be maintained at almost constant levels for more than 1.5 × 10⁴ s, and the ON/OFF ratio of the devices remained about 10³. After more than 2 × 10³ bendings, the electrical properties of the devices remained almost the same.     

Technological Fabrication Features of Microwave Device with Schottky Barriers

At present, research and development of heterojunctions are conducted in the directions of searching for new compositions and technological regimes for the creation of ohmic and barrier transitions for gallium arsenide. The transition to silver-based metallization, which has large thermal and electrical conductivity comparing with gold and a relatively low diffusion coefficient to gallium arsenide, should improve the technical characteristics of the devices. One of the most important technological operations in the formation of Schottky ohmic contacts and barriers is thermal annealing. Silver to gallium arsenide contacts are made in vacuum by the method of thermal evaporation. The deposition and thermal treatment regimes for creating ohmic contacts of Ag–Ge–In/n–n⁺ GaAs with specific contact resistance ρ_c = (5...7)+10^–5 Ω.cm² are developed. The influence of the substrate temperature during the silver deposition and the annealing temperature on the height of the Schottky barrier Ag/n–n⁺ GaAs, the injection coefficient γ and the nonideality factor η is established.     

砷化镓气相掺硫外延和亚微米薄层的制备

本文介绍了Ga-AsCl_3-H_2体系,研究了气相外延时硫的掺杂行为,讨论了硫的掺杂机理和生长了亚微米薄层。制得的亚微米外延层的质量表明,表面形貌良好,缺陷少,重复性好。典型的电学性质为:当厚度≤0.4μm和浓度为1—2×10~(17)/cm~3时,击穿电压V_B=7—10V。在单层和多层外延结构中,界面浓度基本是突变的,过渡区约0.1μm。这些外延片已用于制备变容管和远红外探测器等。     

Resistive switching properties of a thin SiO2 layer with CeOx buffer layer on n+ and p+ Si bottom electrodes

Resistive switching properties of a 2-nm-thick SiO₂ with a CeO_x buffer layer on p⁺ and n⁺ Si bottom electrodes were characterized. The distribution of set voltage (V_set) with the p⁺ Si bottom electrode devices reveals a Gaussian distribution centered in 4.5 V, which reflects a stochastic nature of the breakdown of the thin SiO₂. Capacitance–voltage (C–V) measurements indicate the trapping of electrons by positively shifting the C–V curve by 0.2 V during the first switching cycle. On the other hand, devices with the n⁺ Si bottom electrodes showed a broad distribution in V_set with a mean value higher than that of p⁺ Si bottom electrode devices by 0.9 V. Although no charge trapping was observed with n⁺ Si bottom electrode devices, a degradation in interface states was confirmed, causing a tail in the lower side of the V_set distribution. Based on the above measurements, the difference in the V_set can be understood by the work function difference and the contribution of electron trapping.     

Bistable electrical switching and nonvolatile memory effect in mixed composite of oxadiazole acceptor and carbazole donor

Bistable electrical switching and nonvolatile memory devices with the configuration of indium tin oxide (ITO)/active layer/aluminum (Al) are reported. The active layer were prepared from the mixed compositions of 2-(4-tert-butylphenyl)-5-(4-biphenylyl)-1,3,4-oxadiazole, (PBD) and poly(N-vinylcarbazole) (PVK). The as-fabricated ITO/PBD:PVK/Al sandwiched devices exhibited rewriteable flash memory property. Due to the strong interaction between oxadiazole acceptor and carbazole donor, the devices demonstrate excellent performance. The memory devices can operate over a small voltage range, the absolute value of switching-on threshold voltage is less than 1 V and the switching-off threshold voltage is less than 3.5 V. The ON/OFF ratio of current switches in the range of 10⁴–10² during the variation of applied voltage and the two different resistance states can be maintained over 4 h.     

Gate‐Induced Massive and Reversible Phase Transition of VO2 Channels Using Solid‐State Proton Electrolytes

The use of gate bias to control electronic phases in VO₂, an archetypical correlated oxide, offers a powerful method to probe their underlying physics, as well as for the potential to develop novel electronic devices. Up to date, purely electrostatic gating in 3‐terminal devices with correlated channel shows the limited electrostatic gating efficiency due to insufficiently induced carrier density and short electrostatic screening length. Here massive and reversible conductance modulation is shown in a VO₂ channel by applying gate bias V_G at low voltage by a solid‐state proton (H⁺) conductor. By using porous silica to modulate H⁺ concentration in VO₂, gate‐induced reversible insulator‐to‐metal (I‐to‐M) phase transition at low voltage, and unprecedented two‐step insulator‐to‐metal‐to‐insulator (I‐to‐M‐to‐I) phase transition at high voltage are shown. V_G strongly and efficiently injects H⁺ into the VO₂ channel without creating oxygen deficiencies; this H⁺‐induced electronic phase transition occurs by giant modulation (≈7%) of out‐of‐plane lattice parameters as a result of H⁺‐induced chemical expansion. The results clarify the role of H⁺ on the electronic state of the correlated phases, and demonstrate the potentials for electronic devices that use ionic/electronic coupling.     

An isolated Al-poly Si-(p)Si-(n+)Si switching device

A new MISS switching device structure was designed and fabricated, which consists of Al/poly Si/p/n⁺/p-Si layers and is isolated by diffusing n-well to the buried n⁺ layer.The switching voltage increases with increasing junction area of the poly-Si junction and the n⁺p junction, due to surface recombination current in the emitter-base junction, respectively. The holding voltage is kept nearly constant of 0.9 V for the 886 Å poly Si devices.     

Alteration of gate oxides thickness for SOC level integration

The integration of entire system on a chip (SOC) is the major challenge for the semiconductor industries. The successful implementation of SOC will require innovation in both circuit design and fabrication technology. However, from a process technology point of view, it can be seen that in order to provide design flexibility each of the sub-system may require different gate oxide thicknesses. In this work, ¹⁹F⁺ implantation of variable doses on silicon is explored to achieve this goal. It has been observed that the differential oxide thickness can be achieved by varying the implanted dose of the fluorine on silicon, due to alteration in the oxidation rate. C–V and J–E characteristics are used to demonstrate the electrical behavior of fluorine implantation-based MOS devices. The stoichiometric composition analysis of dielectric materials is reported by FTIR measurements. The control over the oxide thickness, interface states, threshold voltage and stoichiometric composition of dielectric materials could play a vital role in the SOC level integration.     

Transient current spectroscopy and frequency dispersion studies of low temperature GaAs and Al0.3Ga0.7As metal-insulator-semiconductor diodes

Low temperature (LT)-grown GaAs and Al_0.3Ga_0.7As metal-insulator-n⁺-GaAs (MIN) diodes have been fabricated and their electrical properties analyzed. Studies were carried out to evaluate the interfacial quality of the LT layer and the underlying n⁺-GaAs layer using transient current spectroscopy (TCS) and capacitance-frequency (C-f) characterization. TCS studies on LT-GaAs revealed a high concentration of a continuum of states anda dominant electron trap with an activation energy of 0.52eV. In LT-Al_0.3Ga_0.7As, a shallow trap at 0.36eV and two deep level traps at 0.85eV and 1.12eV were observed. Frequency dispersion was observed to be less for LT-GaAs samples with an AlAs barrier layer than without an AlAs barrier layer. However, LT-Al_0.3Ga_0.7As MIN diodes displayed a smaller frequency dispersion than LT-GaAs MIN diodes. Upon further investigation into MISFET devices, it was found that LT-Al_0.3Ga_0.7As MISFET devices had better transconductance frequency dispersion characteristics than LT-GaAs MISFET devices did.     

pH, pK and pNa detection properties of SiO2/Si3N4 ISFET chemical sensors

This article reports the technological fabrication and the electrical characterisation of SiO₂/Si₃N₄ ion sensitive field effect transistors (ISFET) for the detection of H⁺, K⁺ and Na⁺ ions. ISFET chemical sensors show quasi-nernstian pH response with sensitivities around 54 mV/pH. pK and pNa measurements are also investigated, evidencing sensitivities lower than 20 mV/pH and non-nernstian pH-dependent phenomena for the highest K⁺ or Na⁺ concentrations (pK and pNa, respectively, lower than 4 and 3). It is shown that the detection properties of H⁺, K⁺ and Na⁺ ions are dependent on each other, being responsible for saturation effects for the highest concentrations. It is finally concluded that SiO₂/Si₃N₄ ISFETs are well adapted for the pH measurement, can be used for the pK or pNa measurements in the case of buffered solutions but are not fully suitable for multi-ion detection in the case of medical analysis.     

High-efficiency,low-cost solar cells on 3-inch silicon wafers

The present work describes practical ways of attenuating the severe limitations imposed by different kinds of areal inhomogeneities on the performance of large-area p⁺?n?n⁺ single-crystal silicon solar cells. The test devices were processed on 3-inch, lower-grade n-wafers and the minimization of the cells' cost was one of the desired objectives. A combination of simple design/technological approaches described in this work has ultimately led to the development of low-cost, high-efficiency (> 17%) 3-inch silicon solar cells with improved overall electro-optical performance. These devices possess short-circuit current densities similar to those of sophisticated laboratory samples prepared on high-quality, small-area silicon.     

OCVD carrier lifetime in PNN diode structures with axial carrier lifetime gradient

The OCVD (open circuit voltage decay) method is the generally used method for the determining of carrier lifetime in the structures of semiconductor devices. This paper is focused on power diode (P⁺NN⁺) structures, in which is realised a carrier lifetime gradient to influence the current and voltage waveforms during the reverse recovery process. A theoretical analysis of the general features of voltage decay courses in OCVD measurements on diode structures with an axial carrier lifetime gradient in the diode base is presented. Some results obtained from both simulations and experimental measurements are discussed in the paper.     

Reliability issues of offset drain transistors after different modes of static electrical stress

The reliability issues of Offset Drain Transistors (ODT's) after different modes of static electrical stress (high voltage uniform gate stress, high voltage drain stress and hot carrier stress) are presented. Besides, the evolution of the macroscopic electrical parameters of these devices after high voltage uniform gate stress, has been attributed quantitatively to the evolution of the bulk gate oxide trapping characteristics and the variation of the Si/SiO₂ interface state charge. Furthermore, qualification of these devices for application in non-volatile memory arrays as bit select transistor has been conducted.