VLSI多层互连可靠性第二部分：应力感应失效

一、引言应力迁移（stressmigration。，简称SM）的发现和研究始于1984年[1]。从那时起，就引起了各国学者的广泛重视，许多人对它进行了大量的研究，从现象、机制、物理模型、分析方法、影响因素以及对VLSI可靠性的影响等多方面进行了探索。但迄今为止，仍有许多方面未能得到满意的结果，成为当前VLSI可靠性研究的重要课题之一。至今，应力迁移尚无准确定整的定义，一般仿照电迁移的定义描述应力迁移的基本现象。即在一定的温度下，集成电路中的金属互连线在应力的作用下产生的物质扩散现象称为应力迁移（或称应力感应迁移）。由此造成…     

脉冲应力增强的NMOSFET's热载流子效应研究

 本文研究了交流应力下的热载流子效应,主要讨论了脉冲应力条件下的热空穴热电子交替注入对NMOSFET's的退化产生的影响.在脉冲应力下,阈值电压和跨导的退化增强.NMOSFET's在热空穴注入后,热电子随后注入时,会有大的退化量,这可以用中性电子陷阱模型和脉冲应力条件下热载流子注入引起的栅氧化层退化来解释.本文还定量分析研究了NMOSFET's退化与脉冲延迟时间和脉冲频率的关系,并且给出了详细的解释.在脉冲应力条件下,器件的热载流子退化是由低栅压下注入的热空穴和高栅压下热电子共同作用的结果.     

交流信号对亚微米CMOS集成电路可靠性的影响

介绍了交流信号对亚微米CMOS集成电路可靠性的影响,重点分析了亚微米CMOS集成电路中交流应力下的热载流子效应、电迁移、栅氧化层介质击穿效应。通过与直流应力下器件可靠性的对比,分析交流信号与直流信号对亚微米CMOS集成电路可靠性影响的差异。     

脉冲应力增强的NMOSFET′s热载流子效应研究

本文研究了交流应力下的热载流子效应 ,主要讨论了脉冲应力条件下的热空穴热电子交替注入对NMOSFET′s的退化产生的影响 .在脉冲应力下 ,阈值电压和跨导的退化增强 .NMOSFET′s在热空穴注入后 ,热电子随后注入时 ,会有大的退化量 ,这可以用中性电子陷阱模型和脉冲应力条件下热载流子注入引起的栅氧化层退化来解释 .本文还定量分析研究了NMOSFET′s退化与脉冲延迟时间和脉冲频率的关系 ,并且给出了详细的解释 .在脉冲应力条件下 ,器件的热载流子退化是由低栅压下注入的热空穴和高栅压下热电子共同作用的结果     

脉宽调制功率放大器可靠性考核与分析

主要介绍了脉宽调制（PWM）功率放大器的工作原理和对其进行可靠性研究的方法。对PWM功率放大器施加环境应力和电应力,并在不同工作环境下对其进行直流参数的测试,测得PWM功率放大器在不同条件下的输出电流、零输出电压和静态电流等直流参数,得出了PWM功率放大器在各自工作条件下直流参数的变化规律。考核环境应力和电应力等对PWM功率放大器可靠性的影响,对预测其使用寿命内的可靠性有重要的参考意义。     

激光冲击处理对AZ31B镁合金焊接件抗应力腐蚀的影响

为了研究激光冲击处理对镁合金焊接件应力腐蚀性能的影响,采用激光波长1064nm,脉冲宽度15ns,脉冲能量4J,光斑直径3mm的钕玻璃脉冲激光器,对AZ31B镁合金交流氩弧焊接件表面进行冲击处理。室温下采用三点加载的方式,在去离子水中对试样进行应力腐蚀实验。利用光学显微镜和透射电镜观测激光冲击试样微观结构,利用扫描电镜观测应力腐蚀断口。实验结果表明:根据优化的激光参数,能在试样表面制得纳米结构表层,样品表面纳米晶粒大小为35nm左右;激光冲击处理改变了试样表面的应力状态,由残余拉应力60MPa转变为残余压应力-125MPa;激光冲击处理后自腐蚀电位增大88mV,腐蚀电流减小了73.4%,从而降低试样腐蚀倾向;未激光冲击的试样在浸没了192h后出现应力腐蚀开裂,而激光冲击的试样在浸没了10个月后未出现裂纹,这表明激光冲击处理能够提高AZ31B镁合金焊接件抗应力腐蚀的能力。     

集成电路互连线电迁移测试方法与评价

介绍了研究集成电路互连线电迁移的两种方法：加速寿命试验和移动速度试验。对加速寿命试验进行了分析和评价。分析表明,加速寿命试验方法存在高应力条件与正常工作条件下互连线电迁移中金属离子扩散机制不同、BLACK方程的使用范围有限、受试件特殊结构影响和电阻温度系数TCR随温度变化等问题。介绍了一种改进方法。详细介绍了移动速度试验,指出了其在互连线电迁移研究中的应用。     

不同钝化层对硅基铝金属膜应力影响的研究

采用光偏振相移干涉原理测量了硅基上不同钝化层下铝膜应力的变化.研究表明:不同的钝化层对铝膜的应力影响不同.SiO2钝化层下的铝膜应力最小,而钝化层为聚酰亚胺的铝膜应力最大.200 ℃下退火4 h后,应力减小明显,且分布趋向均匀.同时采用有限元法对不同钝化层的铝膜进行了应力模拟,模拟结果与实验结果相符.     

低翘曲度ITO透明导电膜玻璃的工艺研究

研究了不同厚度ITO膜的大尺寸超薄导电玻璃的翘曲度,ITO膜形成期间基片温度对ITO膜层晶体化程度的影响及不同基片温度下形成的ITO膜层在不同的退火条件下的退火前、后的电阻率和膜压应力.实验发现,ITO膜层的很高的压应力是导致导电膜玻璃翘曲的直接原因;采用室温沉积非晶ITO膜,然后经高温热退火可获得低膜压应力多晶相ITO膜.基于实验结论,提出了一种适合批量生产的低翘曲度ITO膜导电玻璃的制备工艺.     

激光冲击参数对残余应力场影响的三维数值模拟

数值模拟是预测激光冲击残余应力场、研究激光冲击参数对残余应力场影响的一种有效方法。采用显式动力有限元软件ANSYS/LS-DYNA对激光冲击处理(LSP)40Cr钢残余应力场进行三维数值模拟;建立了激光冲击处理40Cr钢残余应力场有限元分析(FEA)模型,实现了激光冲击处理40Cr钢残余应力场的数值模拟;模拟研究了激光功率密度、激光脉冲持续时间、激光光斑尺寸对40Cr钢残余应力场的影响。数值模拟结果表明,残余应力模拟值与实测值之间有着较好的一致性;在激光脉冲持续时间一定的条件下,要想获得最大的表面残余压应力,存在一个最佳的激光功率密度;在激光功率密度一定并且脉宽大于45ns的情况下,表面残余压应力随激光脉冲持续时间的增加而减小;在激光功率密度、激光脉冲持续时间一定的条件下,表面残余压应力随光斑直径增大而增大。     

Electromigration assessment for power grid networks considering temperature and thermal stress effects

With technology scaling, reliability has emerged as a major design constraint for very-large-scale integrated circuits. Many prior works have investigated electromigration (EM) on full-chip power grid interconnects. However, most of the published results were obtained under the assumption of uniformly distributed temperature and/or residual stress across interconnects. In this paper, we demonstrate the implementation of novel methodology and flow for full-chip EM assessment on the multi-layered power grid networks of a 32 nm test-chip and investigate the impacts of the within-die temperature and thermal stress variations on the failure rate. The proposed approach is based on recently developed physics-based EM models and the EM-induced IR-drop degradation criterion that replaces the traditional conservative weakest segment method. The cross-layout temperature distribution caused by power dissipations in devices and by interconnect Joule heating has been characterized and taken into account in the full-chip EM assessment methodology. Results of the simulations performed on the analyzed multi-layered power/ground nets show that traditional assumption of the uniform average temperature leads to inaccurate predictions of the time-to-failure. Furthermore, the consideration of thermal stress variation results in a retarded EM induced degradation.     

Failure mechanisms of solder interconnects under current stressing in advanced electronic packages: An update on the effect of alternating current (AC) stressing

The relentless pursuit of miniaturization and integration in electronic industry has put challenges on the reliability of electronic products in aspects of the ever more severe environmental loadings, for example, thermal, electrical, and mechanical stresses. The failure mechanism of solder interconnects under direct current (DC) stressing has been studied and summarized as electromigration (EM), thermomigration (TM), Joule heating, stress-related mechanical degradation. However, the current flow through some paths for example clock buses and signal lines is bidirectional, i.e. alternating current (AC). The damage made in the positive half will be partly healed in the negative half, leading to less EM issues than that in DC stressing. Except for the TM damage, the thermal cycling will also induce thermal-mechanical fatigue issues under AC stressing. Considering these different failure mechanisms between DC and AC stressing, a better understanding of AC stressing will assist in finding out the root cause of failures in practical use. In this review, we discuss the research activities on the effect of AC stressing and their focus on the microstructure evolution of solder or metal interconnects. We firstly explained the discrepancies of reported temperature distribution and analyzed the possible reasons. We then discuss about microstructure evolution of interfacial intermetallic compounds under both DC and AC stressing, as well as the effect of various frequency. Finally, we discuss the failure mechanisms of solder interconnects under AC stressing, especially the unique thermal fatigue. The outlook of AC stressing study has also been discussed.     

A proposal for a standard procedure for moderately accelerated electromigration tests on metal lines

This work is aimed at proposing a standard procedure for moderately accelerated Electromigration (EM) tests applied to interconnection lines of the present and the next future generation of integrated circuits. The procedure has been tested on one metal level test structures using an Al-alloy metallization scheme, but can be easily applied to other materials as well as to metal lines with vias. Different existing standards have been taken into consideration to define this proposal: ASTM F1260-89, JEDEC JESD33-A, JESSI AC41. In the PROPHECY project, the focus was on wafer level reliability evaluation with fast methods, but fast EM methods using extremely accelerated stress conditions usually induce side-effects which can invalidate the results. As a consequence, this procedure suggests the use of moderately accelerated tests, together with a method for reducing the number of tests needed for a complete EM characterization. This procedure gives advice on the test structures to be used and on the preliminary steps to be performed before the EM tests. A measurement system, complying with the requirements of this procedure, is also briefly described. The methods described in this document apply to both package- and wafer-level measurements. In order to validate this procedure, EM tests have been performed on JESSI AC41 specimens.     

CBB65型交流金属化薄膜电容器交流声的控制

CBB65型金属化聚丙烯交流电容器的薄膜之间由于存在间隙,薄膜在电磁力的作用下发生周期性形变,导致薄膜共振,从而引起了交流声。通过试验研究了卷绕压力和热处理条件对交流声的影响。结果发现:选用厚度偏差4%内的薄膜材料、控制卷绕压力为30N,在真空100℃下对芯子进行热处理、保温5h后缓慢冷却,可使电容器交流声控制在允许范围30dB以下,且无一失效。     

保护膜材料对AC PDP放电特性的影响

利用所研制的模拟AC PDP放电特性测量装置，对（CaSr)O,(MgSr)O等不同材料形成的保护膜对AC PDP放电特性的影响进行了研究，确定了新颖膜材料的选择方向，探索了使用高发射性能保护膜材料所必须解决的问题，研究结果表明，用（CaSr)O等混合氧化物制成的保护膜的AC PDP具有比单一氧化物低的工作电压和好的老化特性，但工作电压稳态范围却较窄。研究结果还表明氧化物混合的比例不同，ACPDP的工作电压和稳态范围不同，大约在CaO(或MgO)与SrO的重量比达到1：3时，器件的工作电压最低。     

Electromigration studies on Sn(Cu) alloy lines

The Cu alloying effect in the Sn(Cu) solder line has been studied. The Sn0.7Cu solder line has the most serious electromigration (EM) damage compared to pure Sn and Sn3.0Cu solder lines. The dominant factor for the fast EM rate in Sn0.7Cu could be attributed to the relatively small grain size and the low critical stress, i.e., the yielding stress of the Sn0.7Cu solder line. Also, we found that the shortest Sn0.7Cu solder line, 250 μm, has the most serious EM damage among three solder lines of different lengths. The back stress induced by EM might not play a significant role on the EM test of long solder lines. A new failure mode of EM test was observed; EM under an external tensile stress. The external stress is superimposed on the stress profile induced by EM. As a result, the hillock formation was retarded at the anode side, and void formation was enhanced at the cathode.     

一种低功耗原边反馈AC/DC转换器

低待机功耗、高效率的绿色电源已成为未来电源技术发展的方向,国际上已经正式提出六级能效标准。提出了一种采用常规工艺实现的原边反馈AC/DC转换器电路,解决了传统原边反馈AC/DC转换器元器件多、待机功耗大以及用高压特殊工艺实现低待机功耗的成本昂贵等问题。该原边反馈AC/DC转换器能够满足六级能效标准。     

部分耗尽SOI MOSFETs中沟道的非对称掺杂效应

利用二维模拟软件对部分耗尽SoI器件中的非对称掺杂沟道效应进行了模拟.详细地研究了该结构器件的电学性能,如输出特性,击穿特性.通过本文模拟发现部分耗尽SOI非对称掺杂沟道相比传统的部分耗尽SOI,能抑制浮体效应,改善器件的击穿特性.同时跟已有的全耗尽SOI非对称掺杂器件相比,部分耗尽器件性能随参数变化,在工业应用上具有可预见性和可操作性.因为全耗尽器件具有非常薄的硅膜,而这将引起如前栅极跟背栅极的耦合效应和热电子退化等寄生效应.     

部分耗尽SOI MOSFETs中沟道的非对称掺杂效应

利用二维模拟软件对部分耗尽SoI器件中的非对称掺杂沟道效应进行了模拟.详细地研究了该结构器件的电学性能,如输出特性,击穿特性.通过本文模拟发现部分耗尽SOI非对称掺杂沟道相比传统的部分耗尽SOI,能抑制浮体效应,改善器件的击穿特性.同时跟已有的全耗尽SOI非对称掺杂器件相比,部分耗尽器件性能随参数变化,在工业应用上具有可预见性和可操作性.因为全耗尽器件具有非常薄的硅膜,而这将引起如前栅极跟背栅极的耦合效应和热电子退化等寄生效应.     

金属化薄膜电容器交流声机理及消声技术研究

阐述了CBBFJ型金属化聚丙烯烯膜交流电容器交流声产生的根源，深入分析了其形成机理，并探讨了有效的解决途径。