Multiple-Constraint Driven System-on-Chip Test Time Optimization

The cost of testing SOCs (systems-on-chip) is highly related to the test application time. The problem is that the test application time increases as the technology makes it possible to design highly complex chips. These complex chips include a high number of fault sites, which need a high test data volume for testing, and the high test data volume leads to long test application times. For modular core-based SOCs where each module has its distinct tests, concurrent application of the tests can reduce the test application time dramatically, as compared to sequential application. However, when concurrent testing is used, resource conflicts and constraints must be considered. In this paper, we propose a test scheduling technique with the objective to minimize the test application time while considering multiple conflicts. The conflicts we are considering are due to cross-core testing (testing of interconnections between cores), module testing with multiple test sets, hierarchical conflicts in SOCs where cores are embedded in cores, the sharing of the TAM (test access mechanism), test power limitations, and precedence conflicts where the order in which tests are applied is important. These conflicts must be considered in order to design a test schedule that can be used in practice. In particular, the limitation on the test power consumption is important to consider since exceeding the system's power limit might damage the system. We have implemented a technique to integrate the wrapper design algorithm with the test scheduling algorithm, while taking into account all the above constraints. Extensive experiments on the ITC'02 benchmarks show that even though we consider a high number of constraints, our technique produces results that are in the range of results produced be techniques where the constraints are not taken into account.     

Scheduling analysis of time-constrained dual-armed cluster tools

Cluster tools, each of which consists of several single-wafer processing chambers and a wafer handling robot, have been increasingly used for diverse wafer fabrication processes. Processes such as some low pressure chemical vapor deposition processes require strict timing control. Unless a wafer processed at a chamber for such a process leaves the chamber within a specified time limit, the wafer is subject to quality problems due to residual gases and heat. We address the scheduling problem for such time-constrained dual-armed cluster tools that have diverse wafer flow patterns. We propose a systematic method of determining the schedulable process time range for which there exists a feasible schedule that satisfies the time constraints. We explain how to select the desirable process times within the schedulable process time range. We present a method of determining the tool operation schedule. For more flexible scheduling under the time constraints, we propose a modification of the conventional swap operation in order to allow wafer delay on a robot arm during a swap operation. We compare the performance of the new swap strategy with that of the conventional swap strategy.     

Wafer-Level Modular Testing of Core-Based SoCs

Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to screen defective dies. However, since test time is a major practical constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can be applied to the die under test. We present an optimal test-length selection technique for wafer-level testing of core-based SoCs. This technique, which is based on a combination of statistical yield modeling and integer linear programming, allows us to determine the number of patterns to use for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. We also present a heuristic method to handle large next-generation SoC designs. Simulation results are presented for five of the ITC'02 SoC Test benchmarks, and the optimal test-length selection approach is compared with the heuristic method.     

A Petri Net Method for Schedulability and Scheduling Problems in Single-Arm Cluster Tools With Wafer Residency Time Constraints

With wafer residency time constraints for some wafer fabrication processes, such as low pressure chemical–vapor deposition, the schedulability and scheduling problems are still open. This paper aims to solve both problems. A Petri net (PN) model is developed for the system. This model describes when the robot should wait and a robot wait is modeled as an event in an explicit way. Thus, to schedule a single-arm cluster tool with wafer residency time constraint is to decide how long a robot wait should be. Based on this model, for the first time, we present the necessary and sufficient conditions under which a single-arm cluster tool with residency time constraints is schedulable, which can be checked analytically. Meanwhile, a closed form scheduling algorithm is developed to find an optimal periodic schedule if it is schedulable. Also, a simple method is presented for the implementation of the periodic schedule for steady state, which is not seen in any previous work.      

Resource-constrained loop list scheduler for DSP algorithms

We present a new algorithm for resource-constrained scheduling for digital signal processing (DSP) applications when the number of processors is fixed and the objective is to obtain a schedule with the minimum iteration period. This type of scheduling is best suited for moderate speed applications where conservation of area and power is more important than speed. We define and make use of newgraph dependent constraints to obtain a lower bound estimate on the iteration period for any data-flow graph. By satisfying these constraints before performing the scheduling task, we can restrict the design space and can generate valid schedules in less time than previously reported. The graph dependent constraints provide a more accurate lower bound estimate on the iteration period than previously published results. This new scheduling algorithm exploits the iterative nature of DSP algorithms and uses aniterative-loop based scheduling approach. This resource scheduling algorithm has been incorporated in the Minnesota ARchitecture Synthesis (MARS) system. Our approach exploits inter-iteration and intra-iteration precedence constraints and incorporates implicit retiming and pipelining to generate optimal and near optimal schedules.This research was supported by the Advanced Research Projects Agency under grant number F33615-93-C-1309 and the office of Naval Research under contract number N00014-91-J-1008.     

Integrating Through-Wafer Interconnects With Active Devices and Circuits

Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside of the wafer utilizing the TWIs; the electrical performance of the circuitry must be unchanged as a result of the TWI processing; and the processing must be as cost effective as possible. With these three goals in mind, several options for creating TWIs were considered. This paper explores the various processing options and describes in detail, the final process flow that was selected for testing, the accompanying masks that were designed, the actual processing of the wafers, and the electrical test results.     

Fast algorithms for test optimization of core based 3D SoC

The use of 3D-IC technology has become quite widespread in designing core-based systems-on-chip (SoCs). Concomitantly, testing of cores and inter-layer through-silicon-vias (TSVs) spanning through different layers of 3D chips has become an important problem in the manufacturing cycle. Testing 3D-SoCs is more challenging compared to their 2D counterparts because of the complexity of their design and power management issues. Also, the test procedure demands substantially more power than what is required in the normal functional mode, and hence, stringent thermal constraints during test need to be fulfilled to safeguard future performance and reliability of the chip. Since the overall 3D infrastructure depends on routing layer assignments, core allocation, and the geometry of TSV locations, these parameters should be given due consideration while designing the test-access-mechanism (TAM) that aims for minimizing overall test time satisfying power and TSV constraints. In this paper, we present a three-stage algorithm for reducing the test time in automated post-bond core-based 3D-SoCs, under a set of given constraints on test power, TAM-width, and the number of available TSVs. The proposed algorithm, when run on several ITC-02 SoC benchmarks, outperforms the algorithms presented in earlier work with respect to CPU-time, and additionally, reduces test time in many instances.     

Development of a novel stack package to fabricate high density memory modules for high-end application

A new thinking has been spreading rapidly throughout the microelectronics community in the development and application of 3D stack package. Based on the concept, the application of the 3D stack package to high density memory modules makes DRAM provides major opportunities in both miniaturization and integration for advanced and portable electronic products. In order to meet the increasing demands for smaller, higher functionality-integrated and low cost package, this paper presents a packaging method for multi-chip IC without the problem of warpage and pin leakages. Multiple chips are packaged into a single package by stacking up the chips vertically, in which the packaging method is based on the standard wire bond technology with the use of longer bonding wire, appropriate epoxy for delamination and special care in wafer thinning. The presented method promotes the yield of the packaged IC and also successfully reduces the package size. However, special circuit techniques are required to maintain the normal operation of the packaged IC, as well as to maintain the compatible operating speed and power consumption. The reliability of the IC packaged with the presented method has been examined and it verifies the high performance of the presented method.     

Optimization and validation of thermal management for a RF front-end SiP based on rigid-flex substrate

This paper mainly presents a new 3D stacking RF System-in-Package (SiP) structure based on rigid-flex substrate for a micro base station, with 33 active chips integrated in a small package of 5cm × 5.5cm × 0.8cm. Total power consumption adds up to 20.1 Watt. To address thermal management and testability difficulties of this RF SiP, a thermal test package is designed with the same package structure and assembly flow, only replacing active chips with thermal test dies (TTDs). Optimization and validation of thermal management for the thermal test package is conducted. Effects of the structure, chip power distribution, and ambient temperature aspects on the thermal performance are studied. Thermal vias designed in the organic substrate provide a direct heat dissipation path from TTDs to the top heatsink, which minimizes junction temperature gap of the top substrate from 31.2 °C to 5.3 °C, and enables junction temperatures of all the chips on the face to face structure to be well below 82 °C. Chip power distribution optimization indicates placing high power RF parts on the top rigid substrate is a reasonable choice. The ambient temperature optimizes with forced air convection and cold-plate cooling method, both of which are effective methods to improve thermal performances especially for this micro base station application where environment temperature may reach more than 75 °C. The thermal management validation is performed with a thermal test vehicle. Junction temperatures are compared between finite-volume-method (FVM) simulation and thermal measurement under the natural convection condition. The accordance of simulation and measurement validates this thermal test method. Junction temperatures of typical RF chips are all below 80 °C, which shows the effectiveness of thermal management of this RF SiP.     

Online Scheduling of Integrated Single-Wafer Processing Tools With Temporal Constraints

This paper addresses the issues of online scheduling for integrated single-wafer processing tools with temporal constraints. The integrated single-wafer processing tool is an integrated processing system consisting of single-wafer processing modules and transfer modules. Certain chemical processes require that the wafer flow satisfies temporal constraints, especially, postprocessing residency constraints. This paper proposes an online scheduling method that guarantees both logical and temporal correctness for the integrated single-wafer processing tools. First, mathematical formulation of the scheduling problem using temporal constraint sets is presented. Then, an online, noncyclic scheduling algorithm with polynomial complexity is developed. The proposed scheduling algorithm consists of two subalgorithms: FEASIBLE_SCHED_SPACE and OPTIMAL_SCHED. The former computes the feasible solution space in the continuous time domain, and the latter computes the optimal solution that minimizes the completion time of the last operation of a newly inserted wafer.     

Aggregation convergecast scheduling in wireless sensor networks

We consider the problem of scheduling in wireless sensor networks for the purposes of aggregation convergecast. We observe that existing schemes adopt essentially a two phase approach, consisting of, first, a tree construction and, second, a scheduling phase. Following a similar approach, we propose two new improvements, one to each of the two phases. Starting with a new lower bound on the schedule length, we make use of it in the tree construction phase. The tree construction phase consists of solutions to instances of bipartite graph semi-matchings. The scheduling phase is a weight-based priority scheme that obeys dependency (tree) and interference constraints. Our extensive experiments show that, overall, our proposed solution not only outperforms all previously proposed solutions in terms of schedule length, but it also significantly extends the network’s lifetime.     

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems

Dynamic voltage scaling has been widely acknowledged as a powerful technique for trading off power consumption and delay for processors. Recently, variable-frequency (and variable-voltage) parallel and serial links have also been proposed, which can save link power consumption by exploiting variations in the bandwidth requirement. This provides a new dimension for power optimization in a distributed embedded system connected by a voltage-scalable interconnection network. At the same time, it imposes new challenges for variable-voltage scheduling as well as flow control. First, the variable-voltage scheduling algorithm should be able to trade off the power consumption and delay jointly for both processors and links. Second, for the variable-frequency network, the scheduling algorithm should not only consider the real-time constraints, but should also be consistent with the underlying flow control techniques. In this paper, we address joint dynamic voltage scaling for variable-voltage processors and communication links in such systems. We propose a scheduling algorithm for real-time applications that captures both data flow and control flow information. It performs efficient routing of communication events through multihops, as well as efficient slack allocation among heterogeneous processors and communication links to maximize energy savings, while meeting all real-time constraints. Our experimental study shows that on an average, joint voltage scaling on processors and links can achieve 32% less power compared with voltage scaling on processors alone     

Analysis of Wafer Sojourn Time in Dual-Arm Cluster Tools With Residency Time Constraint and Activity Time Variation

When scheduling cluster tools under wafer residency time constraints, wafer sojourn time in a processing module should be carefully controlled such that it is in a permissive range. Activity time variation often results in wafer sojourn time fluctuation and makes an originally feasible schedule infeasible. Thus, it is very important to know how the wafer sojourn time changes when activity time varies. With bounded activity time variation considered, this paper conducts a detailed analysis of wafer sojourn time variation in dual-arm cluster tools. To do so, a Petri net (PN) model and a real-time control policy are presented. Based on the PN model, real-time operational architecture, and real-time control policy, this paper analyzes the effect of activity time variation on wafer sojourn time delay at a process module and presents its upper bounds. The upper bounds are given in an analytical form and can be easily evaluated. With the wafer sojourn time analysis, it is possible to develop an effective method for schedulability analysis and optimal steady-state scheduling. An example is used to show the applications of the proposed approach.      

A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm

In this paper a mathematical formulation and an efficient solution, of the embedded core-based system-on-chip (SOC) test scheduling problem (ECTSP) is presented. The ECTSP can be stated as follows; given a chip with N _C cores each having a test T _i; where T _i takes time to execute on a test access mechanism (TAM) of width w _j, and a constraint W on the number of top-level test pins; calculate the TAM assignment vector and the schedule for each test T _i, such that the completion time of the full chip test is minimized. All existing approaches have solved the ECTSP by solving the TAM partition and scheduling problem sequentially. In this paper we present an unified approach to solve the ECTSP. We present the first report of a design of reconfigurable core wrapper which allows for a dynamic change in the width of the test access mechanism (TAM) executing a core test. An automatic procedure for the creation of DfT hardware required for reconfiguration using a graph theoretic representation of core wrappers is also presented. For the case of reconfigurable wrappers, efficient algorithms to compute the schedule are presented based upon some recent results in the field of malleable task scheduling. Cases in which the degree of reconfigurability are constrained are considered; the case when only a single core can have reconfigurable wrapper, a schedule with zero TAM idle time can be found in time O(N _C(N _C + W)lgW), and the case when only 2 different wrapper configurations are allowed can be solved in time O(N _C ³). Comparison with existing results on benchmark SOCs show that our algorithms outperform state-of-art ILP formulations not only in schedule makespan, but also significantly reduce computation time.     

Rate-optimal schedule for multi-rate DSP computations

In this paper we present a novel framework ofmulti-rate scheduling of signal processing programs represented by regular stream flow graphs (RSFGs). The main contribution of this paper is translating the scheduling problem of RSFGs into an equivalent problem in the domain of Karp-Miller computation graphs. A distinct feature of our scheduling framework—called themulti-rate software pipelining—is to allow maximum overlapping of operations from successive iterations, subject only to precedence constraints caused by data dependences. p ]We demonstrate that the scheduling of regular stream flow graphs can be formulated as a mathematical problem by capturing data dependences between two actors as a precedence relation between the firing of these actors. Using linear schedules, the problem is further translated into a linear program formulation. An efficient solution for the linear programming problem is obtained by first constructing what is called theprecedence graph. A polynomial-time solution is obtained by observing that the optimal computation rate is theminimum cost-to-time ratio cycle (MCTRC) in the precedence graph and using the well-established solution methods for the MCTRC problem. Finally, to minimize the buffer requirement for the obtained rate-optimal schedule, a graph coloring method based on thecyclic interval graph representation has been proposed.     

Optimal scheduling of coordinated multipoint transmissions in cellular networks

In this paper, we study the optimal scheduling problem in coordinated multipoint (CoMP) transmission–based cellular networks. We consider joint transmission and coordinated scheduling together in CoMP transmission–based cellular networks and develop an optimization framework to compute the optimal max‐min throughput and the optimal scheduling of the transmissions to the users. The optimization problem is found to be a complex linear program with number of variables in for a cellular network of N users and K cells. We solve the optimization problem for several network instances using an optimization tool. The numerical results show that the optimal CoMP transmission provides a significant throughput gain over a traditional transmission. We find that in optimal scheduling the fraction time of coordinated scheduling is higher than that of joint transmission. To solve the optimization problem without any optimization tool, we propose a heuristic algorithm. The performance of the heuristic algorithm is evaluated and found to be provided throughput around 97% of the optimal throughput. Further, we extend the optimization framework to study joint scheduling and power allocation (JSPA) problem in CoMP transmission–based cellular networks. We numerically solve the JSPA problem for the network instances and demonstrate that the optimal power allocation at the base stations is not binary for a significant fraction of time of scheduling. However, the gain in max‐min throughput by the optimal JSPA technique over the optimal scheduling technique is not significant.     

Scheduling tests for VLSI systems under power constraints

This paper considers the problem of testing VLSI integrated circuits in minimum time without exceeding their power ratings during test. We use a resource graph formulation for the test problem. The solution requires finding a power-constrained schedule of tests. Two formulations of this problem are given as follows: (1) scheduling equal length tests with power constraints and (2) scheduling unequal length tests with power constraints. Optimum solutions are obtained for both formulations. Algorithms consist of four basic steps. First, a test compatibility graph is constructed from the resource graph. Second, the test compatibility graph is used to identify a complete set of time compatible tests with power dissipation information associated with each test. Third, from the set of compatible tests, lists of power compatible tests are extracted. Finally, a minimum cover table approach is used to find an optimum schedule of power compatible tests     

STEAC: A Platform for Automatic SOC Test Integration

The lack of electronic design automation tools for system-on-chip (SOC) test integration increases SOC development time and cost, so SOC test integration tools are important in the success of promoting SOC. We have stressed practical SOC test integration issues, including real problems found in test scheduling, test input/output (I/O) reduction, timing of functional test, scan I/O sharing, etc. In this paper, we further consider the requirement of integrating at-speed testing of embedded cores - to detect timing-related defects, our test architecture is equipped with at-speed test capability. Test scheduling is done based on our test architecture and test access mechanism, considering I/O resource constraints. Detailed scheduling further reduces the overall test time of the system chip. All these techniques are integrated into an automatic flow to facilitate SOC test integration. The test integration platform has been applied to both academic and industrial SOC cases. The chips have been designed and fabricated. The measurement results justify the approach - simple and efficient, i.e., short test integration cost, short test time, and small hardware and pin overhead.     

Joint optimization of power scheduling and rate-distortion performance in one-helper problem

We consider the many-help-one problem, also called m-helper problem, for the special case of m = 1 where one source provides partial side information to the fusion center (FC) to help reconstruction of the other correlated source. Both correlated sources communicate information about their observations to the FC through an orthogonal multiple access channel (MAC) without cooperating with each other. First, we characterize the optimal tradeoff between the transmission cost, that is, power, and the distortion D. Then, we consider a joint optimization of source coding and power scheduling from an information theory perspective, where the power scheduling is verified using Shannon capacity formula and the source-coding problem is analyzed using rate-distortion theory. We show that the joint optimization in the Gaussian one-helper problem can be solved analytically. We provide closed-form expressions for the optimal distortion and the optimal power scheduling in terms of the cost weights. Copyright © 2008 John Wiley & Sons, Ltd.     

Opportunistic scheduling for multiclass services with different QoS constraints in wireless data networks

In this letter, we focus on the problem with the objective to maximize the system performance, while guaranteeing specified QoS constraints for multiple user classes in wireless data networks. First, we propose two opportunistic scheduling algorithms that exploit time-varying channel conditions for the special two-constraint case, and then propose an opportunistic scheduling algorithm for the general case. Simulation results illustrate that the proposed scheduling algorithms guarantee the different constraints, and achieve high-system performance that is close to the true optimal value using a known general-purpose optimization package, lingo.