Design‐oriented model for power‐driven design optimization of SC‐ΣΔ modulators

A behavioral model for switched‐capacitors sigma‐delta modulators, suitable for power‐driven design, is presented. Because of the oversampling behavior of this kind of analog‐to‐digital converters, transistor‐level simulations are extremely time consuming. Thus, accurate behavioral models are mandatory in the preliminary design steps to cut the development time. However, when the power consumption of the modulator is pushed down to the absolute minimum level, second‐order effects affecting the settling behavior of the switched‐capacitor integrator must be taken into account. Furthermore, by means of an accurate noise model, based on a second‐order transfer function of the amplifier, a global power minimization is achieved, and the optimum partitioning between the switch and op‐amp noise is obtained. In spite of the improved accuracy, the proposed model requires only a few parameters of the amplifier in the integrator. This allows to easily link the model to an external set of circuit equations, to be derived for the specific amplifier used in the modulator. The model was used in the design of a third‐order modulator in an STM 90‐nm technology. The silicon samples exhibit an effective resolution of 15.2‐b with a 500‐Hz output rate, an oversampling ratio of 500, and a Schreier figure‐of‐merit of 162 dB, with a 38‐μW power consumption at 1.2‐V supply.     

Why‐ and how‐ to integrate Verilog‐A compact models in SPICE simulators

This article presents a fast and accurate way to integrate and validate Verilog‐A compact models in SPICE‐like simulators. Modifications in the models' Verilog‐A source code may be required prior to their conversion into low‐level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog‐A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models. Copyright © 2012 John Wiley & Sons, Ltd.     

Analysis of the floating‐gate transistor using the charge sheet model

The multiple‐input floating‐gate transistor is a semiconductor device that has found wide application in digital and analog electronic integrated circuits. Simulating an electronic circuit is an essential step in the design flow, prior to manufacturing. Therefore, an advanced model for the multiple‐input floating‐gate transistor is needed for analog design. This paper shows a method for adapting the charge sheet model for advanced models of the device. In addition, the problem of obtaining the drain to source current numerically as a function of external voltages is addressed. Furthermore, important plots are presented in order to clarify the behavior of the concerned device. The small signal analysis of the device is included. This summary may be interesting to those seeking to model the multiple‐input floating‐gate transistor, looking for alternatives to analog electronic design, needing low operating voltage, generating new design strategies, or wishing to understand of the operation of the device or the use of alternatives to implement analog circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

A general SPICE compatible circuit model for single‐electron devices and application to bit‐error‐rate calculations

The main purpose of this paper is study of the single‐electron devices (SEDs) behavior, having metal islands, in the time domain. On this basis, some new conceptions, such as division of islands in independent type and dependent type and introduction of multi‐dimensional state space for a SED, have been presented. Then, a new circuit model is introduced for SEDs in general N‐dimensional case. This model is based on the orthodox theory and the solution of the time‐dependent master equation with the capability of installation in the HSPICE software. Hence, one can simulate behavior of the compound circuits including SEDs and other circuit elements by help of this model. Another interesting characteristic of the introduced circuit model is the possibility of using it in calculation of bit error rate in single‐electron logical gates considering both the time and the temperature effects. The behavior of various SEDs in low frequencies is studied, and the results are compared with the results of SIMON, often used as a reference. Furthermore, the time‐dependent results of these devices in high frequencies are calculated and compared with the analytic results for step inputs. These comparisons indicate accuracy and validity of the model. Finally, the model is used for simulating time‐dependent behavior of some single‐electron logic gates, and their total error rate are calculated. Copyright © 2013 John Wiley & Sons, Ltd.     

Numerical investigation of the main factor promoting chaotic power swing in a single‐machine,infinite‐bus power system model with the AVR

This paper presents numerical results on bifurcations and chaotic behavior in a fundamental power system model, a single‐machine infinite‐bus system model with generator excitation control by the first‐order lag AVR. The numerical analysis mainly focuses on revealing the parameter value region where the chaotic behavior is observed. It is shown that the partially linearized model, which is derived by linearizing all of the nonlinear elements except the AVR limiter, exhibits similar bifurcations and chaos. Several simulation results indicate that the mechanisms producing the chaotic behaviors and the bifurcations are the same both in the linearized model and in the original single‐machine infinite‐bus system model for parameter value variation which does not move the equilibrium point from the reference point used for the linearization. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 142(2): 21–28, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10090     

电力系统数据模型描述语言E

为满足电力系统数据模型的高效描述和大量在线数据的高效交换,研发了数据模型描述语言E,它采用面向对象技术,兼容面向关系技术,吸收了XML的优点;在描述100节点CIM模型时,E语言的效率比XML高13.6倍;E语言已在电力调度系统成功应用.     

Modeling of switching frequency instabilities in buck‐based DC–AC H‐bridge inverters

In this paper, the dynamical behavior of a full bridge DC–AC buck inverter controlled by fixed frequency and PWM is studied. After showing that the system can undergo both period‐doubling and Neimark–Sacker bifurcation at the fast scale (switching period) by using the exact switching model, an exact solution discrete‐time model able to predict both instability phenomena is derived. The model is obtained without making the quasi‐static approximation and it can be used to obtain the useful operation region in the multi‐dimensional design parameter space from time domain simulations in a very fast and accurate manner. Based on the study of the system, some design guidelines are provided. Copyright © 2010 John Wiley & Sons, Ltd.     

Generalized predictive control for improving intersample performance

This paper proposes a design method of the Generalized Predictive Control (GPC) strategy which can take account of intersample behavior as well as sampled behavior. To this end, a discrete‐time equivalent plant model and cost function for a continuous‐time plant incorporated with zero‐order hold and discrete‐time controller are derived, and the modified discrete‐time GPC is designed. To verify the effectiveness of our proposed method, the controller is applied to a benchmark problem of a hard‐disk drive. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Simple and accurate approaches to implement the complex trans‐conductance suited for time‐domain simulators for small‐signal and large‐signal table‐based models

This paper focuses on the implementation of table‐based models of high‐frequency transistors for time‐domain simulators at microwave and mm‐wave frequencies. In this frequency range, the channel is not capable of responding to the excitation instantaneously therefore, a delay‐time exists between the channel response and the channel excitation. This delay is represented by a complex trans‐conductance in terms of circuit elements. The high‐frequency models of transistors are required to have the implementation of complex trans‐conductance, where the complex part accounts mathematically for the delay‐time between the channel response and the channel excitation. This paper presents simple and accurate approaches to incorporate the complex trans‐conductance in both small‐signal and large‐signal table‐based models for time‐domain simulators (MOS‐AK International Meeting. Eindhoven, Netherlands, April 2008). Implementation approach for each model, small‐signal and large‐signal, is presented in separated sections. In the first step, the delay is realized by the introduction of an ideal transmission line between the channel excitation and the channel response. As transmission lines are not generally suitable for time‐domain simulations, a lumped element equivalent network is introduced in the second step. The latter approach is fully compatible with time‐domain simulators but frequency limitation, determined by the delay‐time value itself, is introduced. Then the implementation of the complex trans‐conductance in large‐signal model is introduced. In terms of large‐signal behavior, delay‐time is important to achieve a non‐quasi static model. Yet again there is limitation in terms of the frequency range that is determined by the delay value itself. The methodology is illustrated on the small‐signal and the large‐signal equivalent circuit of a Multi‐Fin MOSFET transistor. Simulations are carried out by Cadence Spectre and Agilent ADS simulators, and comparisons are carried out between the simulation results and the measurements. Copyright © 2010 John Wiley & Sons, Ltd.     

Evaluation of costs for procuring reserve capacity in a deregulated power system using multi‐agent model

In this paper, we assume 2 models for securing reserve capacity. One is “Commitment‐based Security Model” and the other is “Reserve Market‐based Security Model.” In Commitment‐based security model, ISO commits procurement of reserve energy to a particular generation company. Meanwhile, in Reserve market‐based security model, ISO procures reserve energy through reserve market. The main object of this research is to investigate which model will be preferable for the viewpoint of consumer's cost. To compare these models, two things are considered in this paper. One is bidding behavior of agents which bids to energy market and reserve market. To consider this, Q‐Learning of multi‐agent model is used. Also, the Unit Commitment (UC) is considered to calculate generation cost. This is to calculate the cost for securing reserve power more precisely. © 2009 Wiley Periodicals, Inc. Electr Eng Jpn, 167(1): 18– 25, 2009; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20705