CMOS high‐precision loser‐take‐all circuit

This paper presents a new current‐mode CMOS loser‐take‐all circuit. The proposed circuit consists of a basic cell that allows implementation of a multi‐input configuration by repeating the cell for each additional input. A high‐speed feedback structure is employed to determine the minimum current among the applied inputs. The significant feature of the circuit is its high accuracy and high‐speed operation. Additionally, the input dynamic range of the circuit can be efficiently controlled via the biasing current. HSPICE simulation results are presented to verify the performance of the circuit, where under a supply voltage of 2.5 V, bias current of 100 µA, and frequency of 10 MHz, the input dynamic range increases within 0–100 µA and the corresponding error remains as low as 0.4%. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

0.5‐V bulk‐driven OTA and its applications

A new 0.5‐V bulk‐driven operational transconductance amplifier (OTA), designed in 50 nm CMOS technology, is presented in the paper. The circuit is characterized by improved linearity and dynamic range obtained for MOS devices operating in moderate inversion region. Some basic applications of the OTA such as a voltage integrator and a second‐order low‐pass filter have also been described. The filter is compared to other low‐voltage filters presented in the literature. Copyright © 2013 John Wiley & Sons, Ltd.     

A novel analog switch for high‐precision switched‐capacitor applications

The performance of a switched‐capacitor circuit strongly depends on its analog switches. This paper introduces a new technique to design a high‐precision analog metal‐oxide‐semiconductor switch for switched‐capacitor applications. The accuracy of analog switches is a critical parameter to determine overall performance of the discrete‐time analog systems. To satisfy the accuracy requirements of the switch, a novel technique to minimize the charge injection and clock feedthrough errors by using a very simple structure is proposed. Moreover, an innovative approach to increase the OFF resistance of the switch and consequently minimizing its leakage current is presented. To evaluate the performance of the proposed switch, simulations are done in TSMC 0.18μm standard complementary metal‐oxide‐semiconductor technology with BSIM3V3 device models. The ON and OFF resistances of the switch are one of the most important factors that should be considered while investigating analog switches. The ON resistance of the proposed switch is less than 560Ω over entire input signal range which completely satisfies the tracking bandwidth requirements. In addition, since the proposed switch provides an ultrahigh OFF resistance in the range of several GΩs, the leakage current of the proposed switch is negligible. Simulation results also show that switch‐induced errors are significantly eliminated by using the proposed cancellation technique. The output error charge due to charge injection and clock feedthrough over a wide range of input signal variation is very low (less than 1.6 fC). Moreover, simulation results show that the proposed switch achieves signal to noise plus distortion ratio of 80.55 dB, effective number of bits of 13.08, total harmonic distortion of ?81.41 dB, and spurious‐free dynamic range of 87.7 dB for a 2.5‐MHz sinusoidal input of 800‐mV peak‐to‐peak amplitude at 200‐MHz sampling rate with a 1.8‐V supply voltage. Consequently, the simulation results verify that the proposed switch can significantly improve the dynamic and static performances of a switched‐capacitor circuit.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

Physics‐based model of lithium‐ion batteries running on a circuit simulator

The authors developed a physics‐based equivalent circuit model of a lithium‐ion battery (LIB) whose parameters are continually updated, reflecting the theoretical calculation results of the Butler‐Volmer equation, diffusion equations of the lithium‐ion and lithium, and Nernst equations of the liquid and solid phases. The developed model was applied to the charge/discharge simulations of an LIB, and the experimental and simulated results of constant current discharges and pulsed‐charge/discharge were found to be in excellent agreement. In particular, using the developed model, analyzing transient responses of the LIB derived from the transition of the electric double layer charging to the electrode reaction is possible. These results demonstrate that the electrochemical performance of an LIB can be calculated on a circuit simulator using the developed model.     

A design methodology for power‐efficient reconfigurable SC ΔΣ modulators

This paper presents a methodology to design reconfigurable switched‐capacitor delta‐sigma modulators (ΔΣMs) capable of keeping their corresponding power efficiency figures constant and optimal for a set of resolutions and signal bandwidths. This method is especially suitable for low‐bandwidth, medium‐to‐high‐resolution specifications, which are common in biomedical application range. The presented methodology is based on an analytic model of all different contributions to the power dissipation of the ΔΣM. In particular, a novel way to predict the static power dissipated by integrators based on class A and class AB operational transconductance amplifier is presented. The power‐optimal solution is found in terms of filter order, quantizer resolution, oversampling ratio, and capacitor dimensions for a targeted resolution and bandwidth. As the size of the sampling capacitors is crucial to determine power consumption, three approaches to achieve reconfigurability are compared: sizing the sampling capacitors to achieve the highest resolution and keep them constant, change only the first sampling capacitor according to the targeted resolution, or program all sampling capacitors to the required resolution. The second approach results in the best trade‐off between power efficiency and simplicity. A reconfigurable ΔΣM for biomedical applications is designed at transistor level in a 0.18‐µm complementary metal–oxide–semiconductor process following the methodology discussed. A comparison between the power estimated by the proposed analytic model and the transistor implementation shows a maximum difference of 17%, validating thus the proposed approach. Copyright © 2014 John Wiley & Sons, Ltd.     

A wideband time‐based continuous‐time sigma‐delta modulator with 2nd order noise‐coupling based on passive elements

Embedding the time encoding approach inside the loop of the sigma‐delta modulators has been shown as a promising alternative to overcome the resolution problems of analog‐to‐digital converters in low‐voltage complementary metal‐oxide semiconductor (CMOS) circuits. In this paper, a wideband noise‐transfer‐function (NTF)‐enhanced time‐based continuous‐time sigma‐delta modulator (TCSDM) with a second‐order noise‐coupling is presented. The proposed structure benefits from the combination of an asynchronous pulse width modulator as the voltage‐to‐time converter and a time‐to‐digital converter as the sampler to realize the time quantization. By using a novel implementation of the analog‐based noise‐coupling technique, the modulator's noise‐shaping order is improved by two. The concept is elaborated for an NTF‐enhanced second‐order TCSDM, and the comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed structure. To further confirm the effectiveness of the presented structure, the circuit‐level implementation of the modulator is provided in Taiwan Semiconductor Manufacturing Company (TSMC) 90 nm CMOS technology. The simulation results show that the proposed modulator achieves a dynamic range of 84 dB over 30 MHz bandwidth while consuming less than 25 mW power from a single 1 V power supply. With the proposed time‐based noise‐coupling structure, both the order and bandwidth requirements of the loop filter are relaxed, and as a result, the analog complexity of the modulator is significantly reduced. Copyright © 2015 John Wiley & Sons, Ltd.     

一种新颖的全数字式双向恒流源电路的设计

针对采用蓄电池作为后备电源的系统,设计出一套新颖的双向工作恒流电路。该电路既可实现蓄电池对低压负载的大电流放电,又可以对蓄电池本身进行恒流充电。同时,本文提出了一套全数字化控制方案,不仅实现了双向电路的恒流控制,而且对蓄电池本身进行了能量管理,使电路具有浮充和欠压保护等功能。另外,通过软件编程,采用数字控制可以很方便地实现电路的恒流、恒压、恒功率等控制功能,从而使电路具有很强的实用性。实验采用TI公司的F2407ADSP芯片作为控制核心,结果表明,该数控电路具有很好的恒流效果,可以用于电力、通讯系统的后备电源中。     

A dynamic‐biasing 4× charge pump based on exponential topology

A 4× charge pump using exponential topology is proposed and implemented. Comparing to the conventional implementations, the proposed circuit suppresses the reverse current effectively without using different threshold‐voltage transistors and additional capacitors. Also, the body effect found in the charge transfer switches is eliminated. The proposed charge pump is analyzed with the state‐space method and fabricated using 0.35 µm complementary metal–oxide–semiconductor process. Results show that the output voltages close to the ideal one, and a maximum power efficiency of 95% was recorded. Copyright © 2013 John Wiley & Sons, Ltd.     

一款电流模控制电荷泵的设计及其稳定性分析

设计了一款电流模控制电荷泵,它与传统的电压模控制电荷泵相比具有更好的稳定性。该电路基于TSMC 0.6um标准CMOS工艺进行设计, Spectre仿真结果表明,电路在10mA~100mA全负载范围内增益较高,输出极点一直为主极点,且相位裕度大于60°,输出可以稳定在-7V并具有很好的稳定性及负载瞬态响应特性     

汽车免维护蓄电池充电接受能力的分析

充电接受能力是汽车蓄电池重要性能之一 ,汽车蓄电池充电接受能力差表现为放电容量逐次减少、深放电后充电困难、充电的水耗增加以及寿命短等 ,实际上 ,充电接受能力与许多性能指标相关 ,并有较大的影响通过对板栅合金、添加剂、固化、化成以及电解液密度等多方面的研究和分析 ,找出了一些影响充电接受能力的相关因素。结果表明 :增加正板栅的锡含量 ,特别是当锡含量大于 1%时 ,蓄电池充电接受能力明显提高 ,会显著提高长期放置后 ,放电再充电能力 ;电解液的密度与单体开路电压有着E =0 84 +d的近似关系 ,因此 ,密度高 ,开路电压高。在恒压下充电 ,恒压值与开路电压之间的差值缩小 ,充电能力变差 ;负极铅膏中添加剂对充电接受能力有大的影响 ,添加木素比腐植酸的电池充电接受能力差 ,1— 2酸对充电接受能力有负面影响。固化参数的控制、化成状态对充电接受能力有一定影响通过对这些因素的控制和调节 ,可达到最佳的充电接受性能     

A new rule for MESFET gate charge division based on the energy conservation principle

The energy conservation problem in the MESFET gate charge model is presented. The energy conservation requirement leads to symmetrical transcapacitances in contradiction to the commonly accepted approaches. The transcapacitance symmetry is completely independent of device symmetry. The resulting small‐signal capacitances are reciprocal. Reciprocal capacitances are often considered charge non‐conservative because they do not contain transcapacitances, but in this approach reciprocity is the result of transcapacitance symmetry and the charge conservation problem is avoided since the charge‐based model includes the transcapacitances. A method for dividing the MESFET gate charge into gate‐drain and gate‐source portions based on the energy conservation rule is developed, and the method is applied to the well‐known Statz gate charge as an example. Copyright © 2004 John Wiley & Sons, Ltd.     

Application of dynamic counter circuits in programmable digital pixel sensor architectures

In this paper, a high dynamic range digital pixel sensor (DPS) is presented. Each pixel receives light illumination and converts the intensity level to a digital code. The analog‐to‐digital conversion is performed in‐pixel. The pixel structure incorporates light to pulse signal converter and compact in‐pixel dynamic counter to convert the pulse signal to binary coded data. Different variations of the custom design dynamic counters are analyzed in a 0.18 µm technology, and their application in the DPS is investigated. It is shown that due to the limited clock frequency required in the sensor pixel, the dynamic counter can be incorporated as a pulse to binary code converter. Performance specifications such as power consumption, dynamic range and resolution of the presented structure are investigated using a 100 × 100 pixel sensor. The presented sensor is an effective solution for use in digital field programmable smart image sensors and vision chips since the pixel output is a regular binary code while no global digital counter bus is required. The fill factor of the presented design remains close to that of typical DPSs. Copyright © 2013 John Wiley & Sons, Ltd.     

Dynamic joint model of capacitive charge pumps and on‐chip photovoltaic cells for CMOS micro‐energy harvesting

On‐chip energy harvesting by means of integrated photovoltaic cells in standard CMOS technology can be successfully used to recharge or power‐up integrated circuits with the use of charge pumps for voltage boosting. In this paper, a tool to facilitate the design of such structures is proposed consisting of an accurate model of the joint dynamics of the micro‐photovoltaic cell and a capacitive DC/DC converter in the slow‐switching limit regime. The model takes into account both the top and bottom parasitic capacitances of the flying capacitors. We assume a classical model for the photodiode whose photogenerated current is extracted from device‐level simulations. The joint model is verified by circuit‐level simulations achieving high accuracy and computation time savings of up to 1700×. The joint model shows that the voltage generated by an integrated photovoltaic cell connected to a capacitive DC/DC converter is not constant even under constant illumination. This phenomenon can only be reproduced through the joint model and failing to take it into account results in an error in the estimation of the time needed by the DC/DC converter to reach a given output voltage. We also demonstrate that the maximum output voltage reached by a DC/DC converter in the slow‐switching limit regime when a photovoltaic cell is used as energy transducer depends on the switching frequency. Finally, the applicability of the model is illustrated through the optimization of time response and charge efficiency for the Dickson, Fibonacci, and exponential topologies in the case of implantable devices. Copyright © 2016 John Wiley & Sons, Ltd.     

Discharger using cascaded switched capacitor converters and selectable intermediate taps for electric double‐layer capacitors

Electric double‐layer capacitors (EDLCs) offer several advantages over traditional batteries, such as a long cycle life, high power capability, and good low‐temperature performance. However, their major drawbacks, such as low specific energy and large voltage variation due to charge/discharge cycling, necessitate the use of high‐efficiency power conversion electronics that can be used to efficiently discharge EDLCs and thus completely utilize the precious stored energy. In this study, we propose a novel discharger for EDLCs; this discharger uses cascaded switched capacitor converters (SCCs) and selectable intermediate taps. Although the voltage conversion ratio of SCCs is fixed, the load voltage can be maintained within a desired range by the selectable intermediate taps. The circuit configuration, operating principles, and procedure for designing SCCs and selectable intermediate taps are presented. Experimental tests were performed using an EDLC module and a 200‐W prototype of the discharger. The obtained results showed that the 60‐V EDLC could be discharged to 30 V with an average efficiency of 96% when the load voltage was maintained within the range of 30 to 40 V. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 183(3): 37–45, 2013; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.22281     

High‐tuning‐range CMOS band‐pass IF filter based on a low‐Q cascaded biquad optimization technique

A design procedure for high‐order continuous‐time intermediate‐frequency band‐pass filters based on the cascade of low‐Q biquadratic cells is presented. The approach is well suited for integrated‐circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivity to component variations. A trade‐off between noise and maximum linear range is also met. A novel, wide‐tuning‐range transconductor topology is also described. Based on these results, a 10‐pole band‐pass filter for a code division multiple‐access satellite receiver has been designed and tested. The filter provides tunable center frequency (f₀) from 10 to 70 MHz and exhibits a 28‐MHz bandwidth around f₀ = 70 MHz with more than 39‐dB attenuation at f₀/2 and 2f₀. Third‐order harmonic rejection is higher than 60 dB for a 1‐Vpp 70‐MHz input, and equivalent output noise is lower than 1 mV_rms. The circuit is fabricated in a 0.25‐µm complementary metal oxide semiconductor process, and the core consumes 12 mA from a 2.5‐V supply, offering the best current/pole ratio figure. The die area resulted to be 0.9 × 1.1 mm². Copyright © 2014 John Wiley & Sons, Ltd.     

Dynamics of charge‐pump phase‐locked loops

Certain problems in the existing treatment of the stability of charge‐pump phase‐locked loops are identified and addressed in this work. New results concerning the instability, stability, and asymptotic stability of charge‐pump phase‐locked loops are obtained by means of Lyapunov's direct and indirect methods. Closer consideration of the local dynamics provides further insight into the system's patterns of behavior. In particular, the influence of circuit parameters on the nature of the steady‐state orbits is investigated. Copyright © 2012 John Wiley & Sons, Ltd.     

A wideband low‐spur 0.18‐µm CMOS phase‐locked loop with bandwidth calibration

This paper presents a 0.18‐µm complementary metal‐oxide‐semiconductor wideband phase‐locked loop with low reference spurs. The dual‐level charge‐pump current calibration technique is proposed to maintain a constant loop bandwidth for wide operation frequency range and achieve low reference spurs. The first level charge‐pump current calibration is seamlessly incorporated in the automatic frequency band hopping control and the mechanism also ensures enough negative transconductance for the voltage‐controlled oscillator to function throughout the whole frequency range. The charge‐pump current mismatch is calibrated by the second level charge‐pump current calibration combined with the pulse‐width scaling technique. The operation frequency range of the phase‐locked loop covers from 4.7 GHz to 6.1 GHz. The measured phase noise is?116 dBc/Hz at 1‐MHz offset and the reference spurs are below?66.8 dBc. Copyright © 2015 John Wiley & Sons, Ltd.     

Electrical Breakdown and Space Charge Formation at High‐Temperature Region in Long‐Time Heating Treatment PVC

Polyvinyl chloride (PVC) is widely used as an insulating material in various electrical products. It is reported that an exothermic reaction reaching temperatures above 150 °C can be caused by overload currents or inferior electrical wire connections before the ignition of electrical products. The exothermic phenomenon may cause deterioration of insulating properties in PVC due to its chemical decomposition. It is necessary to clarify the degradation of insulating properties in PVC under thermal stress exceeding 150 °C for the safe use of electric products. In this investigation the space charge distribution and conduction current in the heat‐treated PVC sheet were measured in the range from room temperature to 200 °C in the presence of a dc electric field, using a high‐temperature PEA system. Positive charge injection and increasing conduction currents were observed before breakdown above 100 °C in 100 °C 300‐h heat‐treated samples and in non–heat‐treated samples. The results indicate the thermal breakdown process from the analysis of conduction currents and electric fields. In samples exposed to higher temperatures (150 °C 100 h), the breakdown strength deteriorated strongly in the range from room temperature to 90 °C. Increases in conduction current were observed in the entire temperature range before breakdown of the 150 °C 100‐h heat‐treated PVC. This indicates that heat treatment above 150 °C degrades the breakdown properties in the range from room temperature to 90 °C due to thermal decomposition accompanied by dehydrochlorination in PVC. The electric field is intensified near the cathode due to positive charge accumulation, and the breakdown strength begins to deteriorate only above 90 °C. This shows that thermal stress exceeding 150 °C causes deterioration of insulating properties and that the breakdown process is affected by space charge formation in PVC.