All‐pass dispersion synthesis using microwave C‐sections

A closed‐form iterative procedure for synthesizing quasi‐arbitrary phase responses with cascaded microwave C‐section all‐pass phasers is presented. The synthesis consists in mapping the transmission poles of the cascaded C‐section structure onto the transmission poles of the specified transfer function, where the latter poles are computed using a closed‐form polynomial generation method. The real and complex transmission poles of the specified transfer function are realized using C‐sections of different lengths and different couplings coefficients. The proposved synthesis is validated by both full‐wave analysis and measured multilayer prototypes. Copyright © 2013 John Wiley & Sons, Ltd.     

All‐pass filters using DDCC‐ and MOSFET‐based electronic resistor

The main motivation in this paper is to draw attention to the tunability and input‐signal amplitude limitations when a nonlinear device is used as a resistor. For this purpose, two first‐order all‐pass filters are proposed using differential difference current conveyor (DDCC), a capacitor and a resistor without element‐matching restriction. These all‐pass filter circuits can be made electronically tunable with electronic resistors. Tunability and input‐signal amplitude limitations of the proposed circuits due to the operational restrictions of the electronic resistors are examined. PSPICE simulations confirm the validity and the practical utility of the proposed circuits. Copyright © 2010 John Wiley & Sons, Ltd.     

High input impedance voltage‐mode first‐order all‐pass sections

This paper proposes six new first‐order voltage‐mode all‐pass sections (VM‐APSs) based on three general topologies. Each circuit uses two differential voltage current conveyors and three grounded passive components. All the circuits possess high input impedance and easy control of pole frequency either by a simple matching of resistors (two equal‐valued resistors) for the three canonical circuits or by a single resistor for three non‐canonical circuits. PSPICE simulation results using real device 0.5µ CMOS parameters are given to validate the proposed circuits. Copyright © 2007 John Wiley & Sons, Ltd.     

CMOS‐controlled inverting CDBA with a new all‐pass filter application

In this study, new active elements called inverting current differencing buffered amplifier (ICDBA) and current‐controlled ICDBA (C‐ICDBA) are presented. Unlike current differencing buffered amplifier (CDBA), their voltage transfer ratio between the Z and W terminals are equal to minus one. Furthermore, CMOS implementations of the C‐ICDBA and current‐controlled CDBA (C‐CDBA) are shown. Moreover, a novel first‐order all‐pass filter is proposed to show advantages and new circuit producing capability of the ICDBA/C‐ICDBA. Lastly, an electronically tunable band‐pass filter is given as an application example using the presented all‐pass filter. The measured and simulation results are in good agreement with the theoretical ones. Copyright © 2010 John Wiley & Sons, Ltd.     

Modelling,design and realization of micromachined millimetre‐wave band‐pass filters

This paper describes the design, the realization and the experimental characterization of a micromachined band‐pass filter with a working frequency of 38GHz. The synthesis of the structure has been carried out by means of the image parameter representation of two‐port networks. A coupled line coplanar configuration has been adopted for the filtering network. The good agreement between theoretical and experimental results demonstrates the validity of the proposed design approach. Copyright © 2003 John Wiley & Sons, Ltd.     

PMSM Sensorless Control Based on Position Estimation Correction Using All‐Pass Filters

This paper proposes a novel flux estimation method for the position sensorless control of permanent magnet synchronous motors (PMSMs). In general, the stator flux linkage for position estimation in PMSMs is obtained using the pure integration of voltages. The infinite dc gain of the pure‐integrator, however, causes numerical drifts in the obtained stator flux linkage due to the dc offset in the input of this integrator. To address this problem, a quasi‐integrator is often substituted instead of the pure integrator to restrict the dc gain, leading to another problem in which the phase characteristics vary according to the operating frequency. As a result, the ideal phase characteristics (?90° constant) cannot be held, and the position estimation performance deteriorates. Therefore, this paper proposes a phase characteristic correction method for quasi‐integrators using all‐pass filters, which achieves extremely precise estimation under transient conditions as well as in steady state.     

A mixed‐mode KHN‐biquad using DVCC and grounded passive elements suitable for direct cascading

In this paper a mixed‐mode (input and output signals can be current or voltage) Kerwin–Huelsman–Newcomb (KHN) biquad with low/high input impedance and high/low output impedance depending on the type of the corresponding signal (current/voltage) is presented. The circuit is constructed using three differential voltage current conveyors (DVCCs), two grounded capacitors and three grounded resistors. The circuit simultaneously provides bandpass (BP), highpass (HP) and lowpass (LP) responses when the output is current and notch, BP and LP responses when the output is voltage. The notch and allpass responses can be obtained by connecting appropriate output currents directly without using additional active elements. Because of the low input and high output impedance of the circuit for current signals and the high input and low output impedance for voltage signals, it can be used in cascade for realizing higher‐order filters. SPICE simulation results are given to verify the theoretical analysis. Copyright © 2008 John Wiley & Sons, Ltd.     

Design of IIR linear‐phase nonuniform‐division filter banks with signed powers‐of‐two coefficients

This paper deals with the minimax design of two‐channel linear‐phase (LP) nonuniform‐division filter (NDF) banks using infinite impulse response (IIR) digital all‐pass filters (DAFs) with signed powers‐of‐two (SPT) coefficients. Based on the theory of two‐channel NDF banks using two IIR DAFs, the design problem is appropriately formulated to result in an appropriate Chebyshev approximation for the desired phase responses of the IIR DAFs. Through a frequency sampling and iterative approximation method, the optimization problem for finding the SPT coefficients for the IIR DAFs can be solved by utilizing a weighted least‐squares approach in conjunction with a coordinate rotational digital computer (CORDIC) algorithm. The resulting two‐channel SPT coefficient NDF banks can possess approximately LP response without magnitude distortion. Several simulation examples are presented for illustration and comparison. Copyright © 2008 John Wiley & Sons, Ltd.     

Two‐dimensional recursive digital filters with nearly circular‐symmetric magnitude response and approximately linear phase

This paper presents a general structure using 1‐D and two‐dimensional (2‐D) recursive digital all‐pass filters (DAFs) for the design of 2‐D recursive circularly symmetric digital low‐pass filters (CS‐DLFs). The general structure is a cascade of two stages composed of all‐pass building blocks. The first stage is a parallel connection of a 2‐D recursive DAF with a symmetric half‐plane (SHP) support for its filter coefficients and a 2‐D pure delay block. The second stage composed of a parallel connection of a 1‐D recursive DAF and a 1‐D pure delay block is used for eliminating the unwanted pass‐band induced by the first stage. As a result, the design of a 2‐D CS‐DLF in either the least‐squares or the minimax sense can be formulated in a simple linear optimization problem in terms of the weighted‐phase response error for each DAF. Design results with nearly circularly symmetric magnitude response and approximately linear phase are also provided for illustration and comparison. Copyright © 2010 John Wiley & Sons, Ltd.     

New designs of low/high‐pass and mid‐pass/stop FIR digital filters

New designs of highly efficient low/high‐ and mid‐pass/stop (centre‐symmetric band‐pass/stop) FIR non‐recursive digital filters are presented. The designs are based on the modulation property of DFT, applied to the already presented MAXFLAT halfband low‐pass filters. The presented filters have explicit formulas for their tap‐coefficients, and therefore are very easy to design. They have highly smooth frequency response and wider transition regions like MAXFLAT filters. The design formulae are modified to give new classes of low/high‐ and mid‐pass/stop filters, for which, like in equiripple filters, the transition bandwidth can be reduced by increasing the size of ripple on magnitude response. It is shown, with the help of design examples, that the performance of these filters is comparable to that of equiripple filters. Copyright © 2001 John Wiley & Sons, Ltd.     

Wave log‐domain filters using lattice sections

In this paper, the design of log‐domain filters with uncommon transfer functions is considered, using the wave log‐domain design method. To this end, the concept of log‐domain wave equivalent of a lattice section is introduced, as a new building block, in order to enable the design of filters with transfer functions dealing with amplitude and phase response at the same time. This building block is very useful when the phase and the group delay response of the filter is significant. The functionality of this design approach is verified through a design example and simulation results. Copyright © 2010 John Wiley & Sons, Ltd.     

Phase error analysis in CMOS injection‐coupled LC quadrature oscillator (IC‐QO)

This paper presents a novel approach to study the phase error in source injection coupled quadrature oscillators (QOs). Like other LC QOs, the mismatches between LC tanks are the main source of phase error in this oscillator. The QO is analyzed where the phase error and oscillation frequency are derived in terms of circuit parameters. The proposed analysis shows that the output phase error is a function of injection current and the current of source equivalent capacitor. As a result, it is shown that increasing of tail current and LC tank quality factor decreases the phase error. Derived equations show that the phase error can be cancelled and even controlled by adjusting bias currents. To evaluate the proposed analysis and consequent designed QO, a 5.5 GHz CMOS QO is designed and simulated using the practical 0.18 µm TSMC CMOS technology. The experiments show good agreement between analytical equations and simulation results. Copyright © 2013 John Wiley & Sons, Ltd.     

A reconfigurable high ultimate rejection inductorless band‐pass filter by the use of N‐path passive mixers

In this paper, a band‐pass filter with a tunable bandwidth and the center frequency is introduced, which employs N‐path and N × M‐path passive mixer structures, for multiband multistandard wireless receivers. The center frequency of the proposed filter is tunable from 0.1 to 1 GHz, while its bandwidth is also adjustable from 6% to 34% of the center frequency at 100 MHz. The passband ripple is reduced by applying a Miller compensation technique, resulting in a worst‐case ripple of only 1.6 dB over the entire tuning range. An additional eight‐path filter is also utilized at the input of the circuit, which highly improves the out‐of‐band rejection of the filter as well as its out‐of‐band linearity. The noise figure and the input return loss are, respectively, better than 5 and 10 dB, and depending on the desired center frequency, the total power consumption of the proposed filter varies from 41 to 70 mW.     

A three‐phase voltage‐source PWM inverter system characterized by sinusoidal output voltage with neither common‐mode voltage nor normal‐mode voltage

This paper deals with an inverter system integrating a small‐rated passive EMI filter with a three‐phase voltage‐source PWM inverter. The purpose of the EMI filter is to eliminate both common‐mode and normal‐mode voltages from the output voltage of the inverter. The motivation of this research is based on the well‐known fact that the higher the carrier or switching frequency, the smaller and the more effective the EMI filter. An experimental system consisting of a 5‐kVA inverter, a 3.7‐kW induction motor, and a specially designed passive EMI filter was constructed to verify the viability and effectiveness of the EMI filter. As a result, it is shown experimentally that both three‐phase line‐to‐line and line‐to‐neutral output voltages look purely sinusoidal as if the inverter system were an ideal variable‐voltage, variable‐frequency power supply when viewed from the motor terminals. This results in complete solution of serious issues related to common‐mode and normal‐mode voltages produced by the inverter. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 145(4): 88–96, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10206     

A 5 GHz quadrature relaxation oscillator with mixing for improved testability or compact front‐end implementation

We demonstrate by measurements on a test circuit that a 5 GHz relaxation oscillator with accurate quadrature outputs and low phase‐noise can be obtained, and that these favorable properties can be preserved while the mixing function is performed by this oscillator. This is useful either to measure the quadrature error at a low frequency, or to implement a low‐intermediate frequency (IF) or zero‐IF (homodyne) radio frequency front‐end. Copyright © 2008 John Wiley & Sons, Ltd.     

A family of memristor‐based reactance‐less oscillators

In this paper, we present for the first time a family of memristor‐based reactance‐less oscillators (MRLOs). The proposed oscillators require no reactive components, that is, inductors or capacitors, rather, the ‘resistance storage’ property of memristor is exploited to generate the oscillation. Different types of MRLO family are presented, and for each type, closed form expressions are derived for the oscillation condition, oscillation frequency, and range of oscillation. Derived equations are further verified using transient circuit simulations. A comparison between different MRLO types is also discussed. In addition, detailed fabrication steps of a memristor device and experimental results for the first MRLO physical realization are presented. Copyright © 2013 John Wiley & Sons, Ltd.     

Output‐capacitorless segmented low‐dropout voltage regulator with controlled pass transistors

This article presents a low quiescent current output‐capacitorless quasi‐digital complementary metal‐oxide‐semiconductor (CMOS) low‐dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade‐off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post‐simulated in HSPICE in a 0.18 µm CMOS process to supply a stable load current between 0 and 100 mA with a 40 pF on‐chip output capacitor, while consuming 4.8 μA quiescent current. The dropout voltage of the LDO is set to 200 mV for 1.8 V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively. Copyright © 2015 John Wiley & Sons, Ltd.     

A study of the least mean p‐th adaptive notch filter

In this paper we propose a least mean p‐th adaptive notch filter that has a cost function of E[e^p(n)], where e(n) is the estimation error. The structure of the adaptive filter is a tandem connection of the second‐order adaptive notch filter with an all‐pass filter. In general, the bandwidth of the notch filter should be extremely small from the theoretical and practical viewpoints. However, the convergence speed of the weight becomes slow if the bandwidth is reduced. The transfer function of the notch filter has the following special characteristic, that is, zero in the center frequency and unity in other frequencies. The equivalent broad bandwidth can be obtained when the cost function is chosen as E[e^p(n)]. Higher convergence speed and excellent stationary performance are obtained using the combination of E[e^p(n)]. Finally, the convergence performance of the estimation accuracy is verified by the computer simulation. © 2004 Wiley Periodicals, Inc. Electr Eng Jpn, 150(3): 46–53, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20045     

FDCCII‐based electronically tunable voltage‐mode biquad filter

In this work, a voltage‐mode biquad filter realizing low‐pass, band‐pass and high‐pass characteristics is presented. The proposed filter, which employs two FDCCIIs, two grounded capacitors and two NMOS transistors, provides electronic tunability with the control voltage applied to the gate. NMOS transistors act as linear resistor. Furthermore, the proposed circuit still enjoys realization using a low number of active and passive components, no requirement with the component choice conditions to realize specific filtering functions, high input impedance, and low active and passive sensitivities performance. Simulation results using SPICE program are given to show the performance of the filter and verify the theory. Copyright © 2010 John Wiley & Sons, Ltd.     

CMOS high‐precision loser‐take‐all circuit

This paper presents a new current‐mode CMOS loser‐take‐all circuit. The proposed circuit consists of a basic cell that allows implementation of a multi‐input configuration by repeating the cell for each additional input. A high‐speed feedback structure is employed to determine the minimum current among the applied inputs. The significant feature of the circuit is its high accuracy and high‐speed operation. Additionally, the input dynamic range of the circuit can be efficiently controlled via the biasing current. HSPICE simulation results are presented to verify the performance of the circuit, where under a supply voltage of 2.5 V, bias current of 100 µA, and frequency of 10 MHz, the input dynamic range increases within 0–100 µA and the corresponding error remains as low as 0.4%. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.