1.5-V square-root domain second-order filter with on-chip tuning

A novel square-root domain (SRD) second order filter with automatic tuning control is described. The tuning system is based on a master-slave configuration, where the master is a SRD current-mode magnitude locked loop. The control circuitry allows tuning of the cut-off frequency as well as the quality factor and gain of the filter. The basic building blocks of the complete system are implemented employing a design strategy based on the inherent nonlinear characteristic of Class-AB linear transconductors. A proper biasing scheme in such transconductors leads to operation with very low supply voltages (as low as V/sub GS/+2V/sub DSsat/). Simulation and numerical results together with measurements from a fabricated prototype in a 0.8-/spl mu/m CMOS technology are included in order to validate the design technique proposed.     

3.3-V, 200-Ms/s BiCMOS comparator for current-mode interpolationusing a transconductance stage

This paper presents the design of a low-power, low-voltage latched comparator, suitable for current-mode interpolation, using transconductors instead of current mirrors. Thanks to this approach, higher immunity to device mismatch and overall improved dynamic performance were achieved. The proposed comparator was integrated in a 0.8 μm bipolar complementary metal-oxide-semiconductor technology and implemented in a 200 Ms/s analog/digital converter with 8 bit resolution on a 1 V differential range at 3.3 V supply     

Low-Voltage CMOS Nonlinear Transconductors and Their Application to Companding Current-Mode Filters

Two novel nonlinear CMOS transconductors that can be employed for building CMOS current-mode filters are presented and their performances compared to formerly proposed topologies aimed at the same goal. The first one is based on a previous topology proposed by the authors, where a new biasing procedure leads to an improved performance for low supply voltages. The second one follows a novel approach, based on cascading a transresistor and a transconductor. The analysis is complemented with a more general approach based on the identification of translinear loops present in the circuit. Both nonlinear transconductors can operate at supply voltages as low as one V _GS plus two V _DS of a saturated MOSFET. CMOS current-mode filters based on these blocks are built following companding techniques, and their correct operation is validated by simulation and experimental results.     

Differential pair transconductor linearisation via electronically controlled current-mode cells

Use of the linearising current-mode cell (LCMC) concept is presented to design highly linear differential pair transconductors compatible with standard CMOS technology. The linearity an input voltage range of the proposed circuits are significantly improved over those of the conventional source-coupled differential pair biased by a current sink. The SPICE simulation results show that, for a power supply of +or-5 V, the linearity error is less than 0.2 Omega over +or-4 V differential input range.<>     

A 1-V integrated current-mode boost converter in standard 3.3/5-V CMOS technologies

A 1-V integrated CMOS current-mode boost converter implemented in a standard 3.3/5-V 0.6-/spl mu/m CMOS technology (V/sub TH//spl ap/0.85 V), providing power-conversion efficiency of higher than 85% at 100-mA output current, is presented in this paper. The high-performance boost converter is successfully developed due to three proposed low-voltage circuit structures, including an inductor-current sensing circuit for current-mode operation with accuracy of higher than 94%, a precision V-I converter for compensation-ramp generation in current-mode control, and a VCO providing supply-independent clock and ramp signals. Moreover, a proposed startup circuit enables proper converter startup within a sub-1-V supply condition.     

A Transformation Method from Voltage-Mode OP-Amp-RC Circuits to Current-Mode Gm-C Circuits

A new transformation method is presented and used to transform voltage-mode op-amp-RC circuits to current-mode Gm-C ones. The proposed method enables the generation of high-performance Gm-C filters that benefit from the advantages of good and well-known op-amp-RC structures and the advantages of the current-mode circuits, and at the same time feature electronic tunability, high frequency capability, and monolithic integration ability. An attractive feature of the proposed method is that it results in Gm-C structures with only grounded capacitors in spite of the presence of floating capacitors in the original op-amp-RC circuits and it utilizes a small number of transconductors. Moreover, simultaneous multiple outputs are easily available in the transformed current-mode Gm-C circuits.     

1.5 V tunable Square-Root Domain filter

A novel approach to the design of low-voltage CMOS Square-Root Domain filters is presented. It is based on the large-signal behaviour of a well-known class-AB linear transconductor. A first-order filter is built employing three such transconductors, featuring simplicity and compactness. Measurement results for an experimental prototype in 0.8 /spl mu/m CMOS validate the technique proposed. The filter operates with a single supply voltage of 1.5 V and can be tuned in more than one decade.     

Realization of a 1-V active filter using a linearization techniqueemploying plurality of emitter-coupled pairs

A low voltage (1 V), low-power (100 μW), and low-frequency (9 kHz) fifth-order fully integrated active low-pass filter (LPF) using a bipolar technology is described. Novel highly linear transconductors consisting of N emitter-coupled pairs were designed for low-voltage operation. The linear input range is expanded to about 100 mV_p-p at 1% error with N=4, which is about twice that of the conventional linearization technique. The filter is basically a gyrator-capacitor type, in which gyrators are implemented by using the linearized transconductors. Large time constants were realized with very low current (540 nA/transconductor) owing to the high transconductance-to-operating-current ratio of the linearized transconductors. Measured results show a passband ripple of 1.5 dB, a minimum stopband rejection of 70 dB, and a dynamic range of 56 dB, despite a very high nominal impedance (400 kΩ). Practical limitations of this approach are also discussed, such as the sensitivity of the linearized transconductors against process variations, noise, and frequency limitations     

Digitally programmable CMOS transconductor for very high frequency

This paper describes a new approach for realizing digitally programmable VHF/UHF transconductors compatible with pure digital CMOS technologies. A programmable/tunable transconductor, based on a parallel connection of unit cascode cells, is used to implement a fully balanced current-mode G_m–C integrator to operate over the 30–200 MHz range with more than 70 dB of dynamic range for 1% of THD.     

Design of micropower class AB transconductors: A systematic approach

A systematic design approach to achieve micropower class AB CMOS transconductors is presented. It includes techniques to get rail-to-rail operation and continuous transconductance tuning, based on floating and Quasi-Floating Gate transistors. Application of the proposed design approach leads to a new family of high-performance power-efficient class AB CMOS transconductors. To illustrate the feasibility of this approach, 12 transconductors derived from this common framework have been designed and fabricated in a 0.5 μm CMOS technology. Measurement results show THD values for 2 V inputs of −56 dB for a static power of 300 μW and silicon area <0.07 mm².     

Low-voltage CMOS transconductance cell based on parallel operationof triode and saturation transconductors

A new linearity improvement technique for CMOS triode transconductors is presented. The idea is based on the parallel operation of CMOS triode and saturation region transconductors. Simulation results indicate that 0.01% THD and linearity is possible with 800 mV peak-to-peak input differential signals and 1.5 V supply voltage     

Pico-A/V range CMOS transconductors using series-parallel current division

A simple design procedure for very small transconductors with extended linear range, using series-parallel division of current, is presented. It is based on a previously reported one-equation all-region transistor model. Using this technique, a 33 pico-A/V transconductor equivalent to a 30 G/spl Omega/ resistor is demonstrated.     

Design and performance of tunnel collector HBTs for microwave power amplifiers

AlGaAs/GaAs/GaAs and GaInP/GaAs/GaAs n-p-n heterojunction bipolar transistors (HBTs) are now in widespread use in microwave power amplifiers. In this paper, improved HBT structures are presented to address issues currently problematic for these devices: high offset and knee voltages and saturation charge storage. Reduced HBT offset and knee voltages (V/sub CE,os/ and V/sub k/) are important to improve the power amplifier efficiency. Reduced saturation charge storage is desirable to increase gain under conditions when the transistor saturates (such as in over-driven Class AB amplifiers and switching mode amplifiers). It is shown in this paper that HBT structures using a 100-/spl Aring/-thick layer of GaInP between the GaAs base, and collector layers are effective in reducing V/sub CE,os/ to 30 mV and V/sub k/ measured at a collector current density of 2/spl times/10/sup 4/ A/cm/sup 2/ to 0.3 V (while for conventional HBTs V/sub CE,os/=0.2 V and V/sub k/=0.5 V are typical). A five-fold reduction in saturation charge storage is simultaneously obtained.     

Compact current-mode loop filter for PLL applications

A novel capacitance scaling technique is proposed to reduce on-chip capacitor area using a dual-path self-biased current-mode filter. The capacitor multiplier is obtained by the relative ratio of charge-pump currents I/sub cp2//(I/sub cp2/-I/sub cp1/), rather than the scaling ratio I/sub cp2//I/sub cp1/. Compared with the original current-mode filter, the demonstrated loop filter of 250 pF capacitance is achieved with only 25 pF (90% die area saving), and the resistor area is reduced by 50% owing to reuse of the degenerated resistor R/sub G/.     

A 1.5 V Current-Mode CMOS RMS-to-DC Converter

A very low voltage, current-mode CMOS RMS-to-DC converter is presented. It is fully designed using MOS Translinear techniques. More specifically, its main building blocks are a squarer/divider and a geometric-mean cell which are obtained by using simple second-order MOS Translinear loops in a folded configuration, leading to a very regular and compact implementation. A novel biasing technique is employed for such loops, allowing them to operate at supply voltages as low as 1.5 V. Experimental results for a prototype IC demonstrating the correct operation of the circuit are included.     

Cascadable current-mode single CCII biquads

A new configuration for the realisation of current-mode single-CCII-biquad (SCB) filters with high output impedance is presented. It can synthesise lowpass, bandpass, highpass, notch, and allpass filtering functions with a single CCII connected to five passive RC one-port elements. The quality factor, Q, and the central frequency, omega /sub 0/, of the proposed SCBs are insensitive to the current tracking error of the CCII. These SCBs have the advantages of low passive sensitivities and independently adjustable omega /sub 0/ or Q.<>     

Self-aligned InP DHBT with f/sub /spl tau// and f/sub max/ over 300 GHz in a new manufacturable technology

We report self-aligned indium-phosphide double-heterojunction bipolar transistor devices in a new manufacturable technology with both cutoff frequency (f/sub /spl tau//) and maximum oscillation frequency (f/sub max/) over 300 GHz and open-base breakdown voltage (BV/sub ceo/) over 4 V. Logic circuits fabricated using these devices in a production integrated-circuit process achieved a current-mode logic ring-oscillator gate delay of 1.95 ps and an emitter-coupled logic static-divider frequency of 152 GHz, both of which closely matched model-based circuit simulations.     

A current-mode bit-block circuit applicable to low-voltage, low-power pipeline video-speed A/D converters

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 m device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.     

A State-Space Approach to Intermodulation Distortion Estimation in Fully Balanced Bandpass Gm– C Filters With Weak Nonlinearities

A state-space approach to estimating intermodulation distortion in bandpass G_m-C filters with fully balanced, weakly nonlinear transconductors is introduced. It results in compact analytic expressions applicable to G_m-C filters of any order. For verifying the theory, two G_m-C filters with fully balanced weakly nonlinear transconductors have been designed using Cadence. They have been simulated in SpectreS as well as modeled and simulated in Simulink. Theory and simulation results are found in good agreement     

Low-voltage CMOS current-mode preamplifier: analysis and design

This paper presents the analysis and design of a new low-voltage fully balanced differential CMOS current-mode preamplifier for multi-Gbps series data communications. The minimum supply voltage of the proposed preamplifier is V/sub T/+V/sub sat/. The preamplifier employs a balanced configuration to achieve large bandwidth and to minimize the effect of bias-dependent mismatches. Two new bandwidth enhancement techniques, namely inductive series peaking and current feedback that are specific to low-voltage CMOS current-mode circuits, are introduced. The inductive series peaking technique utilizes the resonant characteristics of LC networks to achieve both a flat frequency response and maximum bandwidth. Current feedback extends bandwidth, lowers input impedance, and improves dynamic range. The employment of both techniques further increases the bandwidth, reduces the value of the series peaking inductor, and improves noise performance of the pre-amplifier at high frequencies. The preamplifier has been designed using a 0.18-/spl mu/m 6-metal 1-poly 1.8-V CMOS technology. Simulation results from Spectre with BSIM3.3 device models that account for device parasitics demonstrate that the preamplifier has a flat frequency response with 25.3 dB dc current gain or equivalently 60 dB/spl Omega/ transimpedance gain with a 50-/spl Omega/ load and bandwidth of 2.15 GHz.