减少RC充电电路能量损失的方法研究

减少RC充、放电电路中能量的损失,可以降低能源的消耗,提高电源的利用率,也可以减少器件的功耗。通过利用多个电源和二极管的非线性,给出了RC充电电路中减少能量损失的方法和理论计算,在理想二极管开关状态下,利用无限多个电源可以使RC充电电路中能量损失减少到零。这对于大容量、高电压的充放电电路、以电容为主的储能电路及设备是非常有用的。最后给出了应用实例。     

Switching Activity Minimization in Iterative LDPC Decoders

LDPC codes can be designed to perform extremely close to the Shannon limit. Achieving such performance with high energy efficiency is now a main goal in the research community. This work combines knowledge of LDPC decoder message statistics, provided by density evolution, with knowledge of the physical implementation of decoders to predict switching activity in the decoder interconnect. In this work we provide results for the switching activity on the interconnect for fully parallel decoders. However, our model can be applied to partially parallel and serial implementations, and is not limited to interconnect. It is shown that switching activity can vary by as much as 300%, depending on several hardware design choices. Results of this work validate the usefulness of the presented model for providing designers with an understanding of how their decoder implementation choices affect power consumption for any size of LDPC code. This knowledge can be used for making design choices that minimize decoder power consumption very early in the hardware design process.     

Generic Description and Synthesis of LDPC Decoders

Through a rapid survey of the architecture of low-density parity-check (LDPC) decoders, this paper proposes a general framework to describe and compare the LDPC decoder architectures. A set of parameters makes it possible to classify the scheduling of iterative decoders, memory organization, and type of check-node processors and variable-node processors. Using the proposed framework, an efficient generic architecture for nonflooding schedules is also given.     

Photonic Quantum Dual-Containing LDPC Encoders and Decoders

We propose encoder and decoder architectures for quantum low-density parity-check (LDPC) codes suitable for all-optical implementation, based on controlled-not (CNOT) and Hadamard gates only. Given the fact that the CNOT gate can be implemented using directional couplers, and Hadamard gate by using $pi$ -hybrid, the proposed encoders/decoders architectures are suitable for implementation in integrated optics. In addition, we propose several quantum LDPC codes based on balanced incomplete block designs.      

Architecture and Finite Precision Optimization for Layered LDPC Decoders

Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, two main issues affect performance and area of practical implementations: quantization and memory. Quantization can strongly degrade performance and memory area can constitute up to 70% of the total area of the decoder implementation. This is the case of the DVB-S2,-T2 and -C2 decoders when considering long frames. This paper is then dedicated to the optimization of these decoders. We first focus on the reduction of the number of quantization bits and propose solutions based on the efficient saturation of the channel values, the extrinsic messages and the a posteriori probabilities (APP). We reduce from 6 to 5 the number of quantization bits for the channel and the extrinsic messages and from 8 to 6 the APPs, without introducing any performance loss. We then consider the optimization of the size of the extrinsic memory considering a multiple code rates decoder. The paper finally presents an optimized fixed-point architecture of a DVB-S2 layered decoder and its implementation on an FPGA device.     

Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders

In this brief, a new algorithm that can efficiently generate all the control signals for the shuffle network used in flexible low-density parity-check (LDPC) decoders is proposed. Employing the proposed algorithm, the hardware complexity of the controller of shuffle networks using the Benes network structure can be significantly reduced. In addition, a low-complexity reconfigurable shuffle network architecture for flexible LDPC decoders is developed. Both the Benes network and the controller can be tailored to fit specific applications. Consequently, an efficient shuffle network for WiMAX LDPC decoders is presented. Synthesis results demonstrate that with the SMIC 0.18-$muhbox{m}$ complementary metal–oxide–semiconductor process, the total gate count of the proposed shuffle network is only 16 000. The area saving is between 26.6% and 71.1% compared to related works in the literature.      

Multicore and Manycore Implementations of ADMM-based Decoders for LDPC Decoding

The alternate direction method of multipliers (ADMM) algorithm has recently been proposed for LDPC decoding based on linear programming (LP) techniques. Even though it improves the error rate performance compared with usual message passing (MP) techniques, it shows a higher computation complexity. However, a significant step towards LP LDPC decoding scalability and optimization is made possible since the ADMM algorithm acts as an MP decoding one. In this paper, an overview of the ADMM approach and its error correction performances is provided. Then, its computation and memory complexities are evaluated. Finally, optimized software implementations of the decoder to take advantage of multi/many-core device features are described. Optimization choices are discussed and justified according to execution profiling figures and the algorithm’s parallelism levels. Experimentation results show that this LP based decoding technique can reach WiMAX and WRAN standards real time throughput requirements on mid-range devices.     

Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders

Turbo decoders inherently require large hardware for VLSI implementation as a large amount of memory is required to store incoming data and intermediate computation results. Design of highly efficient Turbo decoders requires reduction of hardware size and power consumption. In this paper, finite precision effects on the performance of Turbo decoders are analyzed and the optimal word lengths of variables are determined considering tradeoffs between the performance and the hardware cost. It is shown that the performance degradation from the infinite precision is negligible if 4 bits are used for received bits and 6 bits for the extrinsic information. The state metrics normalization method suitable for Turbo decoders is also discussed. This method requires small amount of hardware and its speed does not depend on the number of states. Furthermore, we propose a novel adaptive decoding approach which does not lead to performance degradation and is suitable for VLSI implementation.     

Optimal Datapath Widths Within Turbo and Viterbi Decoders for High Area- and Energy-Efficiency

Datapath widths in state-of-the-art Turbo and Viterbi decoder implementations depend on estimated upper bounds of the differences of processed metrics. Aiming at highest area and energy efficiency, this paper presents guidelines for designing Turbo and Viterbi decoder datapaths with minimal widths. This is based on maximum absolute values of branch, state and path metric differences within theMax-Log-MAP respectively Viterbi decoding algorithm applying modulo normalization. The proposed methodology for determining the maximum absolute values covers punctured as well as n-input binary convolutional and Turbo codes so it accommodates higherradix add-compare-select operations. Maximum absolute values of metric differences and minimum datapath widths are presented for the 3GPP-LTE, DVB-RCS2 and IEEE-802.16 (WiMAX) compliant Turbo decoders and for the IEEE-802.11 (Wi-Fi), IEEE-802.16 (WiMAX) and 3GPP-LTE compliant Viterbi decoders. Besides, a new dynamic branch-metric saturation scheme is presented, which enables a further datapath width reduction within Turbo decoders. In total, a datapath width reduction of two bits (?20 %) is achieved applying radix-4 Max-Log-MAP arithmetic. An overall area-time-energy complexity reduction of 31% is achieved for a soft-input soft-output decoder and of 24% for the LTE Turbo decoder.     

基于FFT-BP算法的多元域LDPC码译码器设计与FPGA实现

GF(q)域上的LDPC码是二进制LDPC码的扩展,它具有比二进制LDPC码更好的纠错性能。FFT-BP算法是高效的LDPC码译码算法,本文在GF(4)域上探讨该算法的设计与实现。本文的创新之处在于,根据FFT-BP算法的特点设计了一种利用Tanner图进行信息索引的方式,简化了地址查询模块的设计。实验表明,在归一化信噪比为2.6dB时,译码器的误码率可达到10-6。     

Finite-Dimensional Bounds on Zm and Binary LDPC Codes With Belief Propagation Decoders

This paper focuses on finite-dimensional upper and lower bounds on decodable thresholds of Zopf_m and binary low-density parity-check (LDPC) codes, assuming belief propagation decoding on memoryless channels. A concrete framework is presented, admitting systematic searches for new bounds. Two noise measures are considered: the Bhattacharyya noise parameter and the soft bit value for a maximum a posteriori probability (MAP) decoder on the uncoded channel. For Zopf _m LDPC codes, an iterative m-dimensional bound is derived for m-ary-input/symmetric-output channels, which gives a sufficient stability condition for Zopf_m LDPC codes and is complemented by a matched necessary stability condition introduced herein. Applications to coded modulation and to codes with nonequiprobably distributed codewords are also discussed. For binary codes, two new lower bounds are provided for symmetric channels, including a two-dimensional iterative bound and a one-dimensional noniterative bound, the latter of which is the best known bound that is tight for binary-symmetric channels (BSCs), and is a strict improvement over the existing bound derived by the channel degradation argument. By adopting the reverse channel perspective, upper and lower bounds on the decodable Bhattacharyya noise parameter are derived for nonsymmetric channels, which coincides with the existing bound for symmetric channels     

The Development of Turbo and LDPC Codes for Deep-Space Applications

The development of error-correcting codes has been closely coupled with deep-space exploration since the early days of both. Since the discovery of turbo codes in 1993, the research community has invested a great deal of work on modern iteratively decoded codes, and naturally NASA's Jet Propulsion Laboratory (JPL) has been very much involved. This paper describes the research, design, implementation, and standardization work that has taken place at JPL for both turbo and low-density parity-check (LDPC) codes. Turbo code development proceeded from theoretical analyses of polynomial selection, weight distributions imposed by interleaver designs, decoder error floors, and iterative decoding thresholds. A family of turbo codes was standardized and implemented and is currently in use by several spacecraft. JPL's LDPC codes are built from protographs and circulants, selected by analyses of decoding thresholds and methods to avoid loops in the code graph. LDPC encoders and decoders have been implemented in hardware for planned spacecraft, and standardization is under way.     

Design and Architecture of Low‐Latency High‐Speed Turbo Decoders

In this paper, we propose and present implementation results of a high‐speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix‐4, center to top, parallel decoding, and early‐stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real‐time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix‐4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field‐programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.     

Turbo Coded OFDM for Reducing PAPR and Error Rates

A selective-mapping (SLM) scheme which does not require the transmission of side information and can reduce the peak to average power ratio (PAPR) in turbo coded orthogonal frequency-division multiplexing (OFDM) systems is proposed. The candidates of the proposed SLM are respectively generated by a turbo encoder using various interleavers. The waiver of side information can avoid the degradation of error rate performance which results from the incorrect recovery of side information at receiver in the conventional SLM OFDM system.     

基于EXIT图的Turbo均衡LDPC码性能分析及优化研究

EXIT图是用来分析级联系统中外信息迭代交换的重要工具,本文将Brink的基于EXIT图的优化MIMO信道LDPC码的思想推广到用于Turbo均衡的LDPC码性能分析及码结构设计优化中。文章首先给出了基于互信息的接收机具体分析模型,接着分别讨论了接收机分析模型中两个单元的EXIT曲线:线性MMSE均衡器和VND(variable node decoder)的联合EXIT曲线,CND(check node variable)的EXIT曲线的详细计算步骤。进一步以获得的EXIT曲线为基础,提出了用于Tur- bo均衡的LDPC码的码结构优化算法,EQVAC-EXIT(EQVAC:equalizer VND and CND)算法,算法能够自动地进行码集噪声门限值计算及优化次数分布对的搜索。最后的数值仿真结果表明,(3,6)正则码及优化得到的非正则码的噪声门限值距离Narayanan的结果仅相差0．03dB左右,优化得到的边的次数分布及节点的次数分布与Narayanan的结果相比也很接近。     

节能降耗呼唤绿色IT

在今年的G8峰会前夕,我国政府公布了外界期待已久的《中国应对气候变化国家方案》。该方案被形容为中国应对气候变化的“根本大法”,历经多年策划、起草,将进一步明确中国作为一个负责任的发展中大国,应对全球气候变化挑战的国家姿态。     

基于生成矩阵的LDPC/Turbo码的构造及内外迭代译码新技术

提出了一种新的LDPC／Turbo码（简称L／T码）,及采用内外迭代译码新技术的简便实用的译码器。L／T码将原来Turbo编码中的两个子编码器分别用RSC码和LDPC码来代替,并由一个交织器连接。解码采用软输入／软输出的最大后验概率算法迭代执行,利用外信息的传递,每个子译码器都可以充分利用另一个在上一步计算中得到的结果。仿真在加性白高斯信道下进行,并将其结果和传统方法进行了比较。     

Concurrent Error Detection in Reed–Solomon Encoders and Decoders

Reed-Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, self-checking RS encoder and decoder architectures are presented. The RS encoder architecture exploits some properties of the arithmetic operations in GF(2^m). These properties are related to the parity of the binary representation of the elements of the Galois field. In the RS decoder, the implicit redundancy of the received codeword, under suitable assumptions explained in this paper, allows implementing concurrent error detection schemes useful for a wide range of different decoding algorithms with no intervention on the decoder architecture. Moreover, performances in terms of area and delay overhead for the proposed circuits are presented.     

台达有源前端助力某油田节能降耗

本文主要介绍了台达有源前端在抽油机上的应用,AFE2000既可以提高工效,增加采油量,又可以节约电能,保护电机及设备。