一种基于闩锁结构的高速电压比较器

文章结合高速A/D转换器的研究设计了一种新型高速、高精度集成闩锁比较器,针对提高集成闩锁型电压比较器的性能,讨论了比较器失效、速度-功耗优化、时钟反馈噪声等设计问题.该比较器有较高的输入电阻,对高频时钟的反馈噪声有较好的抑制性能,采用"电容中和技术"补偿预放大级带宽后更加适用于高速应用的需要.文中给出了详细的性能分析以及采用PSPICE仿真的模拟结果.     

Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects

We propose a new path delay fault model called the transition path delay fault model. This model addresses the following issue. The path delay fault model captures small extra delays, such that each one by itself will not cause the circuit to fail, but their cumulative effect along a path from inputs to outputs can result in faulty behavior. However, non-robust tests for path delay faults may not detect situations where the cumulative effect of small extra delays is sufficient to cause faulty behavior after any number of extra delays are accumulated along a subpath. Under the new path delay fault model, a path delay fault is detected when all the single transition faults along the path are detected by the same test. This ensures that if the accumulation of small extra delays along a subpath is sufficient to cause faulty behavior, the faulty behavior will be detected due to the detection of a transition fault at the end of the subpath. We discuss the new model and present experimental results to demonstrate its viability as an alternative to the standard path delay fault model. We describe an efficient fault simulation procedure for this model. We also describe test generation procedures. An efficient test generation procedure we discuss combines tests for transition faults along the target paths in order to obtain tests that satisfy the requirements of the new model.     

CMOS Multistage Preamplifier Design for High-Speed and High-Resolution Comparators

This brief describes a design technique for multistage preamplifiers of the type commonly used in high-performance comparators. Following the examination of multistage preamplifier responses in both the spectral and time domains, and a consideration 1/f noise attenuation in topologies employing offset storage capacitors, a procedure for optimizing both the number of stages and the offset storage capacitance is presented. As a demonstration vehicle, a comparator with a 13-Msample/s conversion rate and 200-muV minimum input resolution is designed for realization in a 0.4-mum CMOS technology under the constraint of a power dissipation of 250 muW when operating from a 2.5-V supply. In this design, the effective input signal is 33 muV for the minimum input resolution of 200 muV due to signal corruption from circuit noise and residual error from incomplete settling     

ASIC设计自动化最新工具—FPGA开发系统

本文介绍了ASIC设计自动化最新工具——FPGA开发系统的软、硬件支撑环境,FPGA的概况,特点和基本结构,FPGA系列器件和工作频率以及在微机FPGA开发系统上如何进行ASIC电路的设计,最后给出一个设计实例的流程。     

A New Timing-Driven Placement Algorithm Based on Table-Lookup Delay Model

An algorithm is presented for obtaining placements of cell-based very large scale integrated circuits, subject to timing constraints based on table-lookup model. A new timing delay model based on some delay tables of fabricators is first simplified and deduced; then it is formulated as a constrained programming problem using the new timing delay model. The approach combines the well-known quadratic placement with bottom-up clustering, as well as the slicing partitioning strategy, which has been tested on a set of sample circuits from industry and the results obtained show that it is very promising.     

基于伪测量方程模型库的延迟量测滤波

信息在传感器网络传输过程中会出现延迟、错序和丢包等现象,如何充分地利用这些信息对有效提高状态估计精度非常重要。针对现有延迟量测滤波方法中存在的问题,本文基于所建立的伪测量方程模型库,提出一种用于处理延迟量测的滤波方法。首先,利用线性定常系统的参数时不变特性,在测量值有限延迟条件下建立伪测量方程模型库;然后,基于当前时刻到来的延迟或即时测量数据,在模型库中选取与之对应的测量方程模型,并结合系统状态模型,建立系统状态的预测估计器或滤波估计器或滤波融合估计器。仿真对比验证了新方法的有效性与最优性。     

A New Timing-Driven Placement Algorithm Based on Table-Lookup Delay Model

There have been extensive studies on timing-driven placement in recent years.Theapproaches toward this problem fall into two main categories:net-based and path-based.In a typical net-based one,potential critical paths and acceptable d...     

CMOS缓冲器的时延估算模型

随着集成电路生产工艺的进展，互连线在集成电路设计中的影响越来越大。为了减小互连线的影响，通常在芯片互连中插入缓冲器，但这样做会增加时延。因此，为了精确地对系统进行时延估计，必须对缓冲器的时延进行估算。基于Sakurai的器件模型，提出了一种新的缓冲器时延估算模型。     

A Quantized Delay Buffer Model for Single-Wavelength Fiber Delay Line Buffer

The fiber delay line (FDL) buffer is widely used in optical packet switching networks for contention solution. In this paper, a quantized delay buffer model is proposed to analyze the performance of the single-wavelength FDL buffer. Considering the delay quantization in the FDLs, the delay time and the waiting time of the packet are discussed. Without specific assumptions of the packet arrival process and length distribution, the model presents a generic approach to study the delay time distribution and modify the integral equation for the waiting time distribution. Analytic and exact results of the two aforementioned distributions can be obtained without any approximation. The accuracy of the model is validated through simulation.     

全并行A／D转换器中电压比较器的设计

本文介绍了一种用于全并行(闪烁型)A/D转换器的电压比较器的设计,并对闩锁比较级的设计作了具体分析。该电路具有高频、高增益和低功耗等特点。采用氧化物隔离双极工艺,最小特征尺寸为3μm,晶体管的f_T为3.5GHz。该比较器满足S10214位并行A/D转换器的指标要求。     

低踢回噪声锁存比较器的分析与设计

设计了一种低踢回噪声锁存比较器，着重分析和优化了比较器的速度和失调电压。在0.35μm CMOS工艺条件下，采用Hspice对电路进行了模拟。结果表明，比较器的最高工作频率为200MHz，分辨率在6位以上，灵敏度为0．3mV；在2．5V电源电压下，功耗为70μW。     

一种新型混合信号时钟延时锁定环电路设计

给出了数字时钟管理器(DCM)中的一种新型时钟延时锁定环电路(Clock Delay Locked Loop)的设计,为高速同步数据采集系统提供可靠的时钟解决方案。该电路设计是基于延时锁定环(DLL)原理上,采用混合信号电路设计方案来实现。设计中的数字电路控制模块,通过对改进后的电荷泵中的附加开关工作时间的精确控制来实现对输入时钟信号所需延时的精确控制,从而得到所需的延时。该电路不会累积相位误差,具有良好的噪声敏感度。电路采用0.18μm的CMOS工艺,工作电压1.5V,可管理的时钟信号最高频率为360MHz,延时范围为1T,延时精度为T/32。     

一种基于广义KL距离和几何曲率的模型选择准则

模型选择的目标就是识别产生给定数据的模型.通常模型的好坏由模型的泛化能力来度量,而泛化能力包含模型对给定数据的拟合度和模型复杂度两个方面.本文从信息几何的观点使用定义在流形上的广义KL距离来度量模型的拟合度;另一方面从微分几何的观点用曲率的概念来度量模型的内在复杂度;因此,拟合度和复杂度的表示都具有在参数变换下保持不变的特点.通过理论分析,我们证明了用于表示模型预测能力的未来残差与模型固有曲率的关系.由此提出了一种新的基于广义KL距离和曲率的模型选择准则KLCIC.该准则不仅考虑了样本大小、参数个数和函数形式等影响复杂度的因素,而且具有非常清晰直观的几何意义.实验结果表明该方法的有效性.     

一种新的基于查找表的时钟性能驱动的增量式布局算法

提出了一种新的时钟性能驱动的增量式布局算法,它针对目前工业界较为流行的标准单元布局,应用查找表模型来计算延迟.由于在布局阶段较早地考虑到时钟信息,可以通过调整单元位置,更有利于后续的有用偏差时钟布线和偏差优化问题.来自于工业界的测试用例结果表明,该算法可以有效地改善合理偏差范围的分布,而对电路的其它性能影响很小.     

一种新的基于查找表的时钟性能驱动的增量式布局算法

提出了一种新的时钟性能驱动的增量式布局算法,它针对目前工业界较为流行的标准单元布局,应用查找表模型来计算延迟.由于在布局阶段较早地考虑到时钟信息,可以通过调整单元位置,更有利于后续的有用偏差时钟布线和偏差优化问题.来自于工业界的测试用例结果表明,该算法可以有效地改善合理偏差范围的分布,而对电路的其它性能影响很小.     

A Comprehensive Delay Model for CMOS CML Circuits

MOS-transistor-based current-mode logic (CML)-type (MCML) circuits in high-speed circuit applications often operate as low-swing analog circuits rather than fully switched digital circuits. At these high-speed operations, the effect of the finite input signal slope on the delay of MCML gates significantly increases mainly due to incomplete current steering. Hence, for such cases, the conventional RC delay model which is based on ideal step input assumption fails to track the delay of MCML circuits with errors as high as 40% when a design is optimized for high-speed. In this paper, a comprehensive delay model is proposed that accurately predicts the delay of MCML circuits for all types of operation from low-speed and fully switched to high-speed and low-swing applications by including the input slope effect (ISE) into the conventional RC delay model. Furthermore, the proposed model is extended to multilevel complex logic gates without losing the general RC delay model format. Theoretical results are compared with Spice simulations in a 0.13-$mu{hbox {m}}$ CMOS technology. Results show that the error in delay of the proposed model is less than 20% for all practical designs. The proposed model is still sufficiently tractable to be use in back-of-envelope calculations that achieve close-to-optimum solutions without running extensive parametric simulations. In addition to the achieved accuracy and preserved simplicity, the proposed model enhances the intuitive understanding of MCML gates that simple RC delay model fails to provide.      

基于通用航迹起始模型的一步延迟新算法

针对杂波环境下的快速目标航迹起始问题,提出一种新的航迹起始算法,该算法结合了一种新的航迹起始模型和一步延迟航迹起始算法的优点。其主要思想是在普通航迹起始模型的基础上,增加了一级中间航迹,并采用一步延迟航迹起始算法,利用相邻两个采样周期的量测,计算累积新息,剔除虚假航迹、分裂航迹。仿真结果表明:该算法比一般的逻辑算法设计灵活性更强,虚假航迹起始概率也明显下降。     

一种软件自动测试成本的估算控制模型

根据已有的投资回报(ROI)分析模型,结合COCOMO度量结果,在充分考虑回归测试时测试程序维护成本的基础上,提出一种软件自动测试成本估算控制模型.该模型首先提出了平均维护代价因子的概念,并准确地计算出它的阈值,然后通过这个阈值选择合理的测试方式、控制测试成本,从而为整个测试过程提供动态指导和正确的决策方法.     

Design for Small Delay Test - A Simulation Study

Early Life Failures (ELFs) are becoming an important reliability issue in state-of-the-art technologies. ELFs can be indicated by Small Delay Faults (SDFs), however, some SDFs may not be detectable even with modern at-speed tests. For these hidden SDFs, Faster-than-at-Speed Test (FAST) provides a solution. However, FAST imposes new challenges on the test method. Unknown logic values (X-values) are a major challenge in FAST, due to the increased frequencies. A special Design-for-FAST architecture relying on an accordingly adjusted scan configuration and a simple, but efficient X-masking scheme can support X-tolerant compaction in the context of FAST. This work analyzes the trade-offs of this concept within the framework of a standard industrial workflow and presents a comprehensive case study. Simulation results indicate that for some designs, the conventional synthesis workflow does not produce optimal circuit behavior under FAST. In these cases, the Design-for-FAST approach can increase the fault efficiency, while at the same time reducing the amount of X-values in the test responses considerably.