Issues concerning charged device model ESD verification modules − the need to move to alumina

In this work, we demonstrate that both capacitance and inductance must be the central parameters associated with the charged device model (CDM) waveform verification modules. We also propose a change from the previously used FR-4 dielectric material substrate to a more stable alumina. This improves waveform repeatability and will lead to better correlation of test results. This paper completes the groundwork for a full ESDA CDM device testing standard.     

Identification of the physical signatures of CDM induced latent defects into a DC–DC converter using low frequency noise measurements

In this paper, it is demonstrated that low frequency noise measurements are an efficient tool for the detection of latent defects induced by CDM stress in a complex circuit such as a DC–DC converter. This technique is able to detect the presence of a defect whereas classical electrical testing techniques such as Iddq or functionality test fail. In addition, a correlation between the noise signature and the nature of the defect is established. In particular, the presence of trapped charges in the oxides is clearly identified.     

Test structures and testing methods for electrostatic discharge: results of PROPHECY project

The goal of one PROPHECY subtask was to find a set of realistic test patterns for electrostatic discharge (ESD) and propose an appropriate testing method. Starting with basic test structures, a systematic analysis of the layout parameters dependence of the ESD hardness of various CMOS technologies tested according to the Human Body Model (HBM), Transmission Line Pulser (TLP) and socketed Charged Device Model (CDM) hardness has been carried out. Main emphasis has been given to the correlation between results obtained by the different test methods i.e. HBM and TLP, as well as between HBM and socketed CDM. The results obtained on the basic test structures, which are representative of an analogue technology, are compared (i) with results on optimised test patterns, which more realistically emulate the structure of the actual integrated circuits, and (ii), finally with results on several products. It is shown that the results of a careful analysis of the test patterns can be applied to real pads, and at the end, even to products.     

Simulation study for the CDM ESD behaviour of the grounded-gate nmos

The parasitic bipolar transistor inherent to grounded gate nMOSts is modelled accounting for the specific conditions applied by CDM ESD stress. The impact of the gate length on the CDM-specific bipolar saturation mode is addressed. The different operation modes occurring during CDM ESD stress translate to self-heating which explains the observed test results.     

Test circuits for fast and reliable assessment of CDM robustness of I/O stages

CDM hardening during the development of technology, devices, libraries and finally products differs significantly from the process well-established for HBM. This paper introduces a method on the basis of specialized CDM test structures including protection elements and sensitive monitor elements. These test structures mimic typical CDM-sensitive circuits found by physical failure analysis over the years. Manufactured in five different technologies, structures were assembled in both a regular package and a new package emulator. CDM stress tests, very-fast TLP tests, transient interferometric mapping, device simulation, and failure analysis lead to new insights in the complex interdependencies during CDM and underline the need of CDM-specific test structures.     

Using charged device model testing to eliminate real-world ESD failures

Of 30 bipolar, BiCMOS, and CMOS monolithic, integrated circuit products that were ESD classified to the socketed Charged Device Model (CDM), 27 had ≥500 V withstand voltages and experienced no real-world CDM failures. Two of the three focus products with < 500 V withstand voltages initially had numerous manufacturing-induced CDM failures. Analysis of these two products showed that both socketed and non-socketed CDM testing induced damage at the same failure sites as identified on real-world CDM failures. However, only non-socketed CDM testing consistently reproduced the subtle damage observed on the real-world failures. On one of the focus products, the more severe damage induced by socketed CDM testing resulted in an open circuit rather than the resistive short that occurred on both the non-socketed and real-world CDM failures.Once the physics of CDM failure on the three focus products were fully understood, the ESD redesigns were relatively straightforward. On all three products, diffused series resistors and/or clamping devices with fast response times were added to the pins with inadequate CDM robustness. For each product, these redesigns boosted the socketed CDM withstand voltages for the previously susceptible pins to ≥1500 V and eliminated real-world CDM failures.Based on this work, a combined socketed and non-socketed CDM test approach is proposed for classifying/evaluating products and driving CDM robustness improvements. Guidelines for CDM testing and CDM improvement programs are also provided.     

Charged device model metrology: limitations and problems

The inconsistent readings of various charged device model (CDM) test heads indicates severe metrology problems exist. Test head-to-test head response times vary by factors of two to three and no independent calibration method exists. CDM waveforms depend upon the total measurement system. This paper discusses the problems and methods necessary to the accurate capture of CDM waveforms.     

Dangerous parasitics of socketed CDM ESD testers

HBM, non-socketed and socketed CDM testing were performed on HF-ICs. By applying HBM and non-socketed CDM stress weak pins were located by selective stress. Socketed CDM, however, caused a damage at the weak pins, even when they were excluded from testing. Socketed and non-socketed CDM caused the same electrical failure signature. After insulating the weak pins from the tester circuitry, these pins survived the socketed CDM test without damage and the failure threshold increased. This behaviour is explained by the discharge of the parasitic tester capacitance through the weak pins, while other pins are tested.     

CDM tests on interface test chips for the verification of ESD protection concepts

The CDM failure threshold of microelectronic components are determined by the peak value of the discharge current. The requirements of the market, however, are given in terms of potential. In addition, it is not known how the CDM susceptibility of an IC is affected by its core circuitry. This paper introduces an idea how CDM protection concepts can be checked by tests on an interface test chip to guarantee satisfying product qualifications.     

Reproducibility of field failures by ESD models — Comparison of HBM, socketed CDM and non-socketed CDM

Two types of IC's with field failures explainable only by ESD damage could be identified. A comparative study with failures caused by HBM, socketed CDM and non-socketed CDM clearly shows, that the failure type of one IC could only be simulated with CDM stress. Socketed as well as non-socketed CDM reproduced exactly the same gate oxide damage at one edge of a specific input transistor as it is known by field failure analysis. Although similar threshold voltages are not expected for both kinds of CDMs because of their different discharge pulse forms, in this case they are found to be almost equal.     

Real-world printed circuit board ESD failures

ICs that are robust to ESD at the component-level may be damaged by ESD at the board-level. Two case studies show that real-world Charged Board Model (CBM) ESD damage is typically more severe than Human Body Model (HBM) or Charged Device Model (CDM) ESD damage. Consequently, CBM damage can be easily mistaken for electrical overstress (EOS) damage. A high-capacitance yet compact Printed Circuit Board (PCB) evaluation board facilitates qualitative CBM testing using conventional CDM test systems. Based on the case studies and test results, guidelines are provided on how to minimize the likelihood of real-world CBM failures.     

Grounded-gate nMOS transistor behavior under CDM ESD stressconditions

This paper contains a systematic study into the effects of design and process variations on the behavior of the grounded-gate nMOS transistor under CDM ESD stress conditions. The correlation of both electrical behavior and physical failure is evaluated for socketed CDM, nonsocketed CDM, and HBM ESD stress models. It is shown that a new compact transistor model, concerning its application for the simulation of CDM behavior, is employed in electro-thermal simulation to explain the experimental results     

Turn-on speed of grounded gate nMOS ESD protection transistors

The turn-on speed of nMOS transistors (nMOST) is of paramount importance for robust Charged Device Model (CDM) protection circuitry. In this paper the nMOST turn-on time has been measured for the first time in the sub-halve nanosecond range with a commercial e-beam tester. The method may be used to improve CDM-ESD hardness by investigating the CDM pulse responses within circuit. Furthermore it is shown that the CDM results of various protection layouts can be simulated with a SPICE model.     

Detection of clipped code-division multiplexed signals

Code-division multiplexing (CDM) is a robust transmission scheme recently adopted for satellite multimedia broadcasting systems. A drawback of CDM is its high peak-to-average power ratio, which can be reduced by clipping the baseband CDM signal. However, clipping introduces in-band noise that may considerably degrade system performance. Proposed is an iterative decision-directed technique for detecting clipped CDM signals. The performance of the algorithm is studied by means of computer simulation. Simulation results show that the proposed technique can provide significant performance improvement compared to a conventional (linear) detection of clipped CDM signals.     

Investigating the CDM susceptibility of IC’s at package and wafer level by capacitive coupled TLP

The method of the capacitive coupled transmission line pulsing (CC-TLP) is applied to a product IC at package level and for the first time at wafer level. The investigated product showed a field failure which could be reproduced by the CDM. The application of the CC-TLP to the product at package and wafer level also reproduced the field failure. Furthermore the measured failure currents correlate very well with the failure currents under CDM conditions.     

MIMO-OFDM-CDM系统低复杂度Turbo检测

提出了将码分复用(CDM)模块看作系统等效信道的一部分,从而在MIMO-OFDM-CDM系统中引入Turbo迭代检测的措施。使用Turbo迭代检测可以通过解码器和解调器之间软信息的多次迭代提高译码的性能。根据CDM模块的特点,提出了将等效多天线之间的干扰视为高斯噪声,从而降低Turbo迭代检测算法复杂度的措施。仿真结果表明,在系统中使用Turbo迭代检测可以在有限次迭代后达到比传统算法更低的误码率。     

Process influence on product CDM ESD performance

Effective ESD protection circuit design has become challenging due to rapid advances in process technology. This study was launched to address those concerns in deep sub-micron technologies and to look for a process windows that preserve CDM ESD robustness for a given ESD protection designs. Experimental results for 0.18 μm integrated CPU’s together with process window effects on CDM robustness are presented and discussed. The correlation between electrical characteristics and some of the common failure modes are described. It is shown that transistor off current lower than critical value can lead to degradation in time and an eventual secondary breakdown in a parasitic NPN transistor that results in unexpected CDM sensitivity.     

Verification of CDM circuit simulation using an ESD evaluation circuit

In this work, the capability of circuit simulation to predict CDM robustness of integrated circuits and to determine weak circuit elements is studied. The applicability is demonstrated for an ESD evaluation circuit designed to enable the analysis and optimization of ESD protection strategies in an early design phase during the introduction of a new technology. CDM circuit simulation is compared to the measurement results of variations of this circuit in two different package types. Failure locations are verified with physical failure analysis. The failure locations and CDM failure levels were reproduced accurately with circuit simulation for all circuit and package variations.     

Study of CDM specific effects for a smart power input protection structure

A Charged Device Model (CDM) specific ESD failure mechanism is discussed for an input protection structure in a smart power technology. The input structure shows unexpected dependency of the CDM robustness on design variations of the input resistor. This paper demonstrates that circuit simulation reproduced the complex failure mechanism accurately after elements like package parameters, substrate resistance, parasitic pn-junctions and the resistance of parasitic physical layers were considered. The importance of accurately modeling these factors for achieving meaningful conclusions for CDM failure mechanisms and CDM robustness from circuit simulation is presented. For validation of the proposed simulation setup, results from circuit simulation are compared to measurements and device simulation.     

A novel digital FM receiver for mobile and personal communications

A digital baseband receiver called zero-intermediate frequency zero-crossing demodulator (ZIFZCD) was developed for digital FM signal detection. ZIFZCD is applicable to many worldwide mobile and personal communications systems. In addition, ZIFZCD offers lower power consumption and simpler implementation, compared to the conventional analog implementation [e.g., a limiter-discriminator integrator and dump (LDI)] and the conventional digital implementation [e.g., the cross-differentiate-multiply demodulator (CDM)]. This paper introduces the ZIFZCD and reports the bit-error rate (BER) of the ZIFZCD under both static and fading environments. The analyzed and simulated BER results show that the ZIFZCD is comparable to the conventional CDM for narrowband digital FM with a modulation index of 0.5, and the ZIFZCD is significantly better than the CDM for wideband digital FM with a modulation index larger than 1.5